WO2009123450A1 - Arrangement and method for etching silicon wafer - Google Patents

Arrangement and method for etching silicon wafer Download PDF

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Publication number
WO2009123450A1
WO2009123450A1 PCT/NL2009/050162 NL2009050162W WO2009123450A1 WO 2009123450 A1 WO2009123450 A1 WO 2009123450A1 NL 2009050162 W NL2009050162 W NL 2009050162W WO 2009123450 A1 WO2009123450 A1 WO 2009123450A1
Authority
WO
WIPO (PCT)
Prior art keywords
etching
wafer
etching solution
belt
arrangement
Prior art date
Application number
PCT/NL2009/050162
Other languages
French (fr)
Inventor
Martien Koppes
Arno Ferdinand Stassen
Jan Hendrik Bultman
Original Assignee
Stichting Energieonderzoek Centrum Nederland
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stichting Energieonderzoek Centrum Nederland filed Critical Stichting Energieonderzoek Centrum Nederland
Publication of WO2009123450A1 publication Critical patent/WO2009123450A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67075—Apparatus for fluid treatment for etching for wet etching
    • H01L21/67086—Apparatus for fluid treatment for etching for wet etching with the semiconductor substrates being dipped in baths or vessels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67706—Mechanical details, e.g. roller, belt
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/6776—Continuous loading and unloading into and out of a processing chamber, e.g. transporting belts within processing chambers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to an etching arrangement for etching a silicon wafer with an upper surface and a lower side according to the preamble of claim 1.
  • Silicon wafers thin slices are used for the production of solar energy cells. After cutting the wafer from an 'ingot', this is first treated with an etching agent during a so- called structure etching process. This removes any damages to the surface caused by cutting. Subsequently, the side which is later used to form the back of the solar energy cell is polished with the use of another etchant. The other side, which will later form the front of the solar cell, is not polished, so that it remains rough and thus restricts reflection by incident light.
  • a silicon wafer is conveyed through a chemical etching bath by means of upper and lower rollers.
  • the wafer is full immersed so that both the upper surface and lower surface are etched.
  • the upper surface of the wafer later forms the back of a solar cell and the lower surface of the wafer later forms the front side of the solar cell.
  • both the upper surface and the lower surface of the wafers are etched simultaneously.
  • etching occurs quicker on grain boundaries than on the silicon grains. This means that a structure of deep grooves is formed on the upper surface of the wafer. In order to polish this surface completely smooth, this surface, which later forms the back of the solar cell, a lot of silicon needs to be removed by etching in order to remove these grooves. Structure etching on the upper surface is therefore not desirable.
  • the wafer floats as it were on the surface of the etchant so that only the lower surface is etched. This may lead to the occurrence of chemicals contacting the front surface of the wafer, for example, as a result of flow, splashing or foam formation of/in the etchant.
  • etching on one side may also be achieved by masking the slices with a special tape and by subsequently texturing the wafers in a machine for etching both sides.
  • the disadvantage of this method is that it is very laborious, as a piece of tape must be attached to each wafer and then be removed again. It is an objective of the present invention to provide an etching arrangement for the single-sided etching of silicon wafers, wherein the above disadvantages of the prior art are eliminated.
  • the arrangement is arranged in that the upper surface of the wafer is masked before the wafer comes into contact with the etching solution.
  • the acid etchant resistant belt is made from plastic, for example
  • Teflon is a plastic which is flexible and can therefore be easily mounted under some degree of tension over the upper rollers. Moreover, Teflon is resistant to acid etchants such as, for example, hydrogen fluoride, hydrogen peroxide and nitric acid.
  • the invention also relates to a method for etching a silicon wafer with an upper surface and a lower surface, comprising:
  • Fig. 1 shows a schematic cross-section of a section of an etching arrangement according to an embodiment of the invention
  • Fig. 2 shows a schematic cross-section of a section of an etching arrangement according to a further embodiment of the invention
  • Figure 1 shows a schematic cross-section of a section of an etching arrangement 1 according to an embodiment of the invention.
  • the etching arrangement 1 comprises an etching bath 2 filled with an etching solution 3.
  • the etching arrangement comprises a conveyance means for conveying one or more wafers through the etching bath.
  • the conveyance means in the embodiment shown, comprises a number of upper rollers 4c-4o and lower rollers 5a-5r.
  • the upper rollers 4c-4o are rotatably arranged in a first row of rollers.
  • a number of lower rollers are arranged to rotate beneath the row of upper rollers. These lie in a second row of rollers, as shown in Figure 1.
  • the etching arrangement 1 also comprises drive means for driving the upper and lower rollers.
  • the drive means (not shown) may comprise a number of gear wheels which are driven in turn by an electric motor, as known by those skilled in the art.
  • the upper rollers 4c-4o and the lower rollers 5a-5r are arranged in the first and seconds rows in such a manner that when the rollers are appropriately driven, a wafer 6 is conveyed between the first and the second row along a specific path. This path runs through the etching solution 3 in the etching bath 2.
  • the etching solution 3 contained in the etching bath 2 may comprise chemicals such as HF in a concentration of between 1 and 70%, HNO3 in a concentration of between 1 and 95% and possibly also additives such as water, sulphuric acid, phosphoric acid and/or surfactants.
  • a typical temperature of the etching solution 3 is between 5 and 50 0 C.
  • the etching arrangement 1 also comprises a flexible synthetic belt 7 which is mounted around a number of upper rollers 4d-4m.
  • the flexible belt is manufactured from a synthetic material which is resistant to the etching solution(s) used in the etching bath.
  • the structure of the synthetic material is such, that the upper surface of the wafer with which it comes into contact is sealed off from etching solutions during at least a first portion of its passage through the etching bath.
  • a suitable synthetic material is Teflon, for example.
  • a wafer can be introduced into the path which runs through the etching solution 3.
  • the wafer that has followed a path through the etching solution can be removed at a second station 21.
  • the upper surface of the wafer 6 will adhere to the belt 7 if it comes into contact with the belt 7 due to the pressure exerted on the wafer 6 and on the belt 7 by the upper and lower rollers. In this manner, the upper surface of the wafer 6 is shielded and the upper surface of the wafer 6 does not come into contact with the etching solution 3. This results in a single-sided etching process, wherein only the lower surface of the wafer 6 is etched.
  • FIG. 2 shows a cross-section of an etching arrangement according to a second embodiment.
  • the etching arrangement 1 also comprises a cleaning bath 9 through which the belt 7 is conveyed via a further conveyance means which may, for example, comprise one or more rollers 12, 13, 14.
  • the cleaning bath 9 contains a cleaning liquid 10.
  • the belt 7 is conveyed through the etching bath and through the cleaning bath 9.
  • the belt 7 is cleaned by the cleaning liquid in the cleaning bath.
  • the etching arrangement is further arranged in that along a second portion of the predetermined path through the etching solution the upper surface of the wafer does not come into contact with the belt.
  • the second portion may be shorter than the at least first portion of the predetermined path in the etching solution.
  • the second portion where the upper surface of the wafer does not contact the belt is located at an entry side of the etching bath.
  • the second portion where the upper surface of the wafer does not contact the belt is located at an exit side of the etching bath.
  • the invention relates to an etching arrangement for etching a silicon wafer with an upper surface and a lower surface, comprising: an etching bath containing an etching solution, at least when in use, in which the etching arrangement comprises an acid etchant resistant continuous belt, which is conveyed by a conveyance means along a predetermined path through the etching solution and which is arranged for masking the upper surface of the wafer before the wafer comes into contact with the etching solution, in such a manner that the upper surface of the wafer comes into direct contact with the belt and, as a result, does not come into contact with the etching solution as it follows the predetermined path through the etching solution.
  • the etching arrangement comprises an acid etchant resistant continuous belt, which is conveyed by a conveyance means along a predetermined path through the etching solution and which is arranged for masking the upper surface of the wafer before the wafer comes into contact with the etching solution, in such a manner that the upper surface of the

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The present invention relates to an etching arrangement (1) for etching a silicon wafer (6) having an upper surface and a lower surface. The etching arrangement (1) comprises: an etching bath (2) containing an etching solution (3), at least when in use, and an acid etchantresistant continuous belt (7), which is guided along a predetermined path through the etching solution (3) by a conveyance means and which is adapted for masking the upper surface of the wafer (6) along at least a first portion of the predetermined path through the etching solution (3), in such a manner that the upper surface of the wafer (6) comes into direct contact with the belt' (7) and, as a result thereof, when the wafer (6) in this state passes along the predetermined path through the etching solution (3), the upper surface thereof does not come into contact with the etching solution (3). This invention can be used for etching silicon wafers (3) for the production of solar energy cells.

Description

Arrangement and method for etching silicon wafer
The present invention relates to an etching arrangement for etching a silicon wafer with an upper surface and a lower side according to the preamble of claim 1. Silicon wafers (thin slices) are used for the production of solar energy cells. After cutting the wafer from an 'ingot', this is first treated with an etching agent during a so- called structure etching process. This removes any damages to the surface caused by cutting. Subsequently, the side which is later used to form the back of the solar energy cell is polished with the use of another etchant. The other side, which will later form the front of the solar cell, is not polished, so that it remains rough and thus restricts reflection by incident light.
In a so-called inline etching process, a silicon wafer is conveyed through a chemical etching bath by means of upper and lower rollers. The wafer is full immersed so that both the upper surface and lower surface are etched. The upper surface of the wafer later forms the back of a solar cell and the lower surface of the wafer later forms the front side of the solar cell. With present techniques, both the upper surface and the lower surface of the wafers are etched simultaneously. This may lead to the reduction of approximately 150% of the silicon on the upper surface in relation to the reduction on the lower surface, which means that 50% or more of the etchant is used unnecessarily on the back of the solar cell; however, the back of the solar cell does not need structure etching in order to texture the surface.
During the structure etching process, in the case of multi-crystalline wafers, etching occurs quicker on grain boundaries than on the silicon grains. This means that a structure of deep grooves is formed on the upper surface of the wafer. In order to polish this surface completely smooth, this surface, which later forms the back of the solar cell, a lot of silicon needs to be removed by etching in order to remove these grooves. Structure etching on the upper surface is therefore not desirable. At the present time, there are machines available on the market used for etching one side only, all of which are based on the same principle. The wafer floats as it were on the surface of the etchant so that only the lower surface is etched. This may lead to the occurrence of chemicals contacting the front surface of the wafer, for example, as a result of flow, splashing or foam formation of/in the etchant.
Structure etching on one side may also be achieved by masking the slices with a special tape and by subsequently texturing the wafers in a machine for etching both sides. The disadvantage of this method is that it is very laborious, as a piece of tape must be attached to each wafer and then be removed again. It is an objective of the present invention to provide an etching arrangement for the single-sided etching of silicon wafers, wherein the above disadvantages of the prior art are eliminated.
This objective is achieved by an arrangement according to the preamble of claim 1, characterized in that whilst following at least along a first portion of a predetermined path through the etching solution the upper surface of the wafer does not come into contact with the etching solution .
In an embodiment the arrangement is arranged in that the upper surface of the wafer is masked before the wafer comes into contact with the etching solution. In an embodiment the acid etchant resistant belt is made from plastic, for example
Teflon. Teflon is a plastic which is flexible and can therefore be easily mounted under some degree of tension over the upper rollers. Moreover, Teflon is resistant to acid etchants such as, for example, hydrogen fluoride, hydrogen peroxide and nitric acid.
According to another aspect, the invention also relates to a method for etching a silicon wafer with an upper surface and a lower surface, comprising:
- conveying the wafer through an etching bath containing an etching solution by means of an acid etchant resistant continuous belt which follows a predetermined path along a conveyance means through the etching solution.
- masking the upper surface of the wafer in such a manner that the upper surface of the wafer comes into direct contact with the belt characterized in that at least along a first portion of a predetermined path through the etching solution the upper surface of the wafer does not come into contact with the etching solution.
Further advantages and features of the present invention will be clarified on the basis of the description of an embodiment wherein reference is made to the accompanying figures, in which:
Fig. 1 shows a schematic cross-section of a section of an etching arrangement according to an embodiment of the invention;
Fig. 2 shows a schematic cross-section of a section of an etching arrangement according to a further embodiment of the invention; Figure 1 shows a schematic cross-section of a section of an etching arrangement 1 according to an embodiment of the invention. The etching arrangement 1 comprises an etching bath 2 filled with an etching solution 3. The etching arrangement comprises a conveyance means for conveying one or more wafers through the etching bath. The conveyance means in the embodiment shown, comprises a number of upper rollers 4c-4o and lower rollers 5a-5r.
The upper rollers 4c-4o are rotatably arranged in a first row of rollers. A number of lower rollers are arranged to rotate beneath the row of upper rollers. These lie in a second row of rollers, as shown in Figure 1. The etching arrangement 1 also comprises drive means for driving the upper and lower rollers. The drive means (not shown) may comprise a number of gear wheels which are driven in turn by an electric motor, as known by those skilled in the art. The upper rollers 4c-4o and the lower rollers 5a-5r are arranged in the first and seconds rows in such a manner that when the rollers are appropriately driven, a wafer 6 is conveyed between the first and the second row along a specific path. This path runs through the etching solution 3 in the etching bath 2. The etching solution 3 contained in the etching bath 2 may comprise chemicals such as HF in a concentration of between 1 and 70%, HNO3 in a concentration of between 1 and 95% and possibly also additives such as water, sulphuric acid, phosphoric acid and/or surfactants. A typical temperature of the etching solution 3 is between 5 and 500C. By driving the upper and lower rollers, the wafer will be conveyed along the path between the upper and lower rollers through the etching bath 2. The lower surface (later front side of the solar cell) of wafer 6 is fully covered by the etching solution 3.
The etching arrangement 1 also comprises a flexible synthetic belt 7 which is mounted around a number of upper rollers 4d-4m. The flexible belt is manufactured from a synthetic material which is resistant to the etching solution(s) used in the etching bath. Furthermore, the structure of the synthetic material is such, that the upper surface of the wafer with which it comes into contact is sealed off from etching solutions during at least a first portion of its passage through the etching bath.
A suitable synthetic material is Teflon, for example.
At a first station 2, a wafer can be introduced into the path which runs through the etching solution 3. The wafer that has followed a path through the etching solution can be removed at a second station 21.
The upper surface of the wafer 6 will adhere to the belt 7 if it comes into contact with the belt 7 due to the pressure exerted on the wafer 6 and on the belt 7 by the upper and lower rollers. In this manner, the upper surface of the wafer 6 is shielded and the upper surface of the wafer 6 does not come into contact with the etching solution 3. This results in a single-sided etching process, wherein only the lower surface of the wafer 6 is etched.
Figure 2 shows a cross-section of an etching arrangement according to a second embodiment. Here, the etching arrangement 1 also comprises a cleaning bath 9 through which the belt 7 is conveyed via a further conveyance means which may, for example, comprise one or more rollers 12, 13, 14. The cleaning bath 9 contains a cleaning liquid 10.
In this embodiment, the belt 7 is conveyed through the etching bath and through the cleaning bath 9. The belt 7 is cleaned by the cleaning liquid in the cleaning bath. This results in an advantageous means of reducing the risk of the upper surface of a following wafer 6a to be etched coming into contact with a residue of the etching solution.
By etching only the lower surface of the wafer 6, at least a 50% saving on expenditure can be achieved by less use of the chemicals. In this manner, more wafers 6, 6a, 6b can be etched with the same quantity of chemicals, thus reducing the use of, for example, HF (a corrosive and toxic acid) on each wafer by at least 50%.
If surfactants are present in the etching solution, this will reduce the formation of foam because less silicon on each wafer is etched. Moreover, because no deeper grooves (etching in the grain boundaries) are formed on the upper surface of the wafer 6, the back of a solar cell can be manufactured just as well requiring less removal (polishing) of silicon. This double saving on expenditure with respect to the silicon (no etching of the upper surface in structure etch and less silicon etching during a polishing step) will result in the reduction of the total removal of the thickness of silicon of the wafer 6, which will benefit the efficiency of the solar energy cell. By using a circulating belt which shields one side of the wafer 6, no synthetic material is consumed for masking, as is the case in the prior art in which each wafer was individually masked by a piece of synthetic material that could not be recycled.
In an embodiment, the etching arrangement is further arranged in that along a second portion of the predetermined path through the etching solution the upper surface of the wafer does not come into contact with the belt.
The second portion may be shorter than the at least first portion of the predetermined path in the etching solution.
In this manner it is possible to etch the upper surface of the wafer during a shorter time than the etching time of the lower surface of the wafer, simultaneously with the lower surface of the wafer, for example to etch away damage on the upper surface of the wafer.
In an embodiment, the second portion where the upper surface of the wafer does not contact the belt, is located at an entry side of the etching bath.
In an alternative embodiment, the second portion where the upper surface of the wafer does not contact the belt, is located at an exit side of the etching bath.
In an embodiment, the invention relates to an etching arrangement for etching a silicon wafer with an upper surface and a lower surface, comprising: an etching bath containing an etching solution, at least when in use, in which the etching arrangement comprises an acid etchant resistant continuous belt, which is conveyed by a conveyance means along a predetermined path through the etching solution and which is arranged for masking the upper surface of the wafer before the wafer comes into contact with the etching solution, in such a manner that the upper surface of the wafer comes into direct contact with the belt and, as a result, does not come into contact with the etching solution as it follows the predetermined path through the etching solution.
It will be evident that those skilled in the art who read the foregoing description will be readily aware of alternative embodiments. The etching arrangement can be used, for example, for etching both rectangular and circular wafers. Such alternative embodiments are considered as being within the scope of the invention, as set forth in the accompanying claims.

Claims

Claims
1. Etching arrangement for etching a silicon wafer with an upper surface and a lower surface, comprising: - an etching bath containing an etching solution, at least when in use, the etching arrangement comprising an acid etchant resistant continuous belt, which is conveyed by a conveyance means along a predetermined path through the etching solution and which is arranged for masking the upper surface of the wafer in such a manner that the upper surface of the wafer comes into direct contact with the belt wherein along at least a first portion of the predetermined path through the etching solution the upper surface does not come into contact with the etching solution.
2. Etching arrangement for etching a silicon wafer, wherein the masking of the upper surface of the wafer is done before the wafer comes into contact with the etching solution.
3. Etching arrangement for etching a silicon wafer according to claim 1 or 2, comprising:
- a number of upper rollers arranged to rotate in a first row of rollers;
- a number of lower rollers arranged to rotate in a second row of rollers;
- drive means for driving the upper and lower rollers, wherein the upper and lower rollers are arranged in the first and the second row in such a manner that the wafer is conveyed by an appropriate driving means between the first and the second row along the predetermined path through the etching solution, wherein the acid etchant resistant continuous belt is mounted around a number of the upper rollers.
4. Etching arrangement according to any one of the preceding claims 1-3, wherein the acid etchant resistant belt is formed from a plastic.
5. Etching arrangement according to claim 4, wherein the plastic comprises Teflon.
6. Etching arrangement according to any one of the preceding claims, wherein said arrangement comprises a cleaning bath through which the belt is conveyed via a further conveyance means.
7. Etching arrangement according to any one of the preceding claims, wherein along a second portion of the predetermined path through the etching solution, the upper surface of the wafer is not in contact with the belt, the second portion being shorter than the at least first portion of the predetermined path in the etching solution where the upper surface of the wafer does not come into contact with the etching solution.
8. Etching arrangement according to claim 7, wherein the second portion where the upper surface of the wafer is not contact with the belt is located at an entry side of the etching bath.
9. Etching arrangement according to claim 7, wherein the second portion where the upper surface of the wafer is not contact with the belt is located at an exit side of the etching bath.
10. Method for etching a silicon wafer with an upper surface and a lower surface, comprising: - conveying the wafer through an etching bath containing an etching solution by means of an acid etchant resistant continuous belt which follows a predetermined path along a conveyance means through the etching solution.
- masking the upper surface of the wafer in such a manner that the upper surface of the wafer comes into direct contact with the belt wherein along at least a first portion of the predetermined path through the etching solution the upper surface does not come into contact with the etching solution.
PCT/NL2009/050162 2008-04-01 2009-03-31 Arrangement and method for etching silicon wafer WO2009123450A1 (en)

Applications Claiming Priority (2)

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NL2001421 2008-04-01
NL2001421 2008-04-01

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1129881A (en) * 1997-07-15 1999-02-02 Sharp Corp Etching treatment device of wafer
DE10320212A1 (en) * 2003-05-07 2004-12-02 Universität Konstanz Process for texturing surfaces of silicon wafers
JP2007335791A (en) * 2006-06-19 2007-12-27 Febacs:Kk Substrate treatment apparatus
US20080041526A1 (en) * 2006-08-16 2008-02-21 Pass Thomas P Single-sided etching
GB2449309A (en) * 2007-05-18 2008-11-19 Renewable Energy Corp Asa A method for exposing a solar cell wafer to a liquid

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1129881A (en) * 1997-07-15 1999-02-02 Sharp Corp Etching treatment device of wafer
DE10320212A1 (en) * 2003-05-07 2004-12-02 Universität Konstanz Process for texturing surfaces of silicon wafers
JP2007335791A (en) * 2006-06-19 2007-12-27 Febacs:Kk Substrate treatment apparatus
US20080041526A1 (en) * 2006-08-16 2008-02-21 Pass Thomas P Single-sided etching
GB2449309A (en) * 2007-05-18 2008-11-19 Renewable Energy Corp Asa A method for exposing a solar cell wafer to a liquid

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