WO2009116201A1 - アクティブマトリクス基板、及び表示装置 - Google Patents
アクティブマトリクス基板、及び表示装置 Download PDFInfo
- Publication number
- WO2009116201A1 WO2009116201A1 PCT/JP2008/070181 JP2008070181W WO2009116201A1 WO 2009116201 A1 WO2009116201 A1 WO 2009116201A1 JP 2008070181 W JP2008070181 W JP 2008070181W WO 2009116201 A1 WO2009116201 A1 WO 2009116201A1
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- WIPO (PCT)
- Prior art keywords
- scanning
- wiring
- gate
- active matrix
- matrix substrate
- Prior art date
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
Definitions
- the present invention relates to an active matrix substrate in which a plurality of data lines and a plurality of scanning lines are arranged in a matrix, and a display device using the same.
- liquid crystal display devices have been widely used in liquid crystal televisions, monitors, mobile phones and the like as flat panel displays having features such as thinness and light weight compared to conventional cathode ray tubes.
- a liquid crystal display device a plurality of data lines and a plurality of scanning lines are wired in a matrix, and a switching element such as a thin film transistor (TFT: Thin Film Transistor) is provided near the intersection of the data lines and the scanning lines.
- TFT Thin Film Transistor
- An active matrix substrate in which pixels having pixels arranged in a matrix is used for a liquid crystal panel as a display panel is known (see, for example, Japanese Patent Application Laid-Open No. 2003-58119).
- gate drivers are provided on both sides of the display unit (effective display area) of the liquid crystal panel to drive the scanning wiring. It has been proposed. That is, in this conventional active matrix substrate, the gate driver on one side of the display unit is connected to the scan line on the odd-numbered row, and the scan line on the even-numbered row is connected to the gate driver on the other side of the display unit. In the conventional active matrix substrate, the gate driver on one side and the other side sequentially performs scanning operation by sequentially outputting scanning signals.
- the circuit scale becomes large even when the gate drivers are provided on both sides of the display unit by connecting the gate drivers on one side and the other side through the scanning wiring.
- the liquid crystal display device can be reduced in size.
- the gate drivers and the scanning wirings on both sides are arranged.
- the connection wiring for connecting the electrodes finer or longer it is necessary to make the connection wiring for connecting the electrodes finer or longer, and the resistance value of the connection wiring may be significantly increased. That is, in the conventional active matrix substrate, when the panel size is increased, the scanning provided on one end side in the scanning direction is larger than the dimension in the scanning direction of the gate driver (for example, the row direction of the matrix). The distance between the wiring and the scanning wiring provided on the other end side is greatly increased. For this reason, in the conventional active matrix substrate, for example, the dimension of the connection wiring connecting the scanning wiring provided on one end side and the gate driver is increased, and the resistance value thereof is increased.
- the number of scanning wirings connected to the gate driver increases, it is required to reduce the interval (pitch) between two adjacent connection wirings, and a plurality of connection wirings connected to a plurality of scanning wirings, respectively. Therefore, it was required to reduce each width dimension (cross-sectional area). That is, in the conventional active matrix substrate, it is required to make the plurality of connection wirings as a whole finer as the number of pixels increases, and the resistance value of these connection wirings may be significantly increased. As a result, in the conventional active matrix substrate, the scanning signal may be remarkably small depending on the distance from the gate driver, and there is a possibility that an appropriate scanning operation cannot be performed.
- an object of the present invention is to provide an active matrix substrate capable of appropriately performing a scanning operation even when the panel size is increased, and a display device using the active matrix substrate.
- an active matrix substrate is provided in the vicinity of a plurality of data wirings and a plurality of scanning wirings arranged in a matrix and an intersection of the data wirings and the scanning wirings.
- An active matrix substrate comprising a plurality of pixels and used as a display panel substrate,
- a plurality of scanning wiring driving circuits that sequentially output scanning signals in a predetermined scanning direction are provided along the scanning direction for the plurality of scanning wirings,
- the plurality of scanning wiring drive circuits are all provided with empty terminals that are not connected to the scanning wiring.
- a plurality of scanning wiring driving circuits are provided along the scanning direction. In all of the plurality of scanning wiring driving circuits, empty terminals that are not connected to the scanning wiring are provided.
- an active matrix substrate capable of appropriately performing the scanning operation even when the panel size is increased can be easily configured.
- a terminal connected to the scanning wiring is on one end side in the scanning direction. And provided on one side of the other end side, and In the scanning wiring drive circuit provided on the other end side in the scanning direction, a terminal connected to the scanning wiring may be provided on one end side in the scanning direction and the other side on the other end side.
- a terminal connected to the scanning wiring and an empty space not connected to the scanning wiring Terminals are sequentially provided along the scanning direction in this order, and
- an empty terminal not connected to the scanning wiring and a terminal connected to the scanning wiring are sequentially provided in this order along the scanning direction.
- it is.
- the number of terminals connected to the scanning wiring is set to be the same, and the number of empty terminals not connected to the scanning wiring is the same. It is preferable that it is set.
- the load applied to all the scanning wiring drive circuits can be made uniform, and the scanning operation can be easily performed.
- the number of terminals connected to the scanning wiring and the number of empty terminals not connected to the scanning wiring are set to the same number in each of the plurality of scanning wiring driving circuits. Also good.
- the display device of the present invention is a display device including a display unit, Any one of the active matrix substrates described above is used for the display section.
- an active matrix substrate capable of appropriately performing a scanning operation even when the panel size is increased is used for the display unit. Even when refined, a display device having excellent display performance can be easily configured.
- an active matrix substrate capable of appropriately performing a scanning operation even when the panel size is increased, and a display device using the active matrix substrate.
- FIG. 4 is a block diagram showing a specific configuration of the gate driver shown in FIG. 3.
- 3 is a timing chart showing a scanning operation on the active matrix substrate.
- FIG. 7 is a block diagram showing a specific configuration of the gate driver shown in FIG. 6. 7 is a timing chart showing a specific example of a scanning operation on the active matrix substrate shown in FIG. 6.
- FIG. 9 is a timing chart showing an operation example of the gate driver shown in FIG. 7 in the scanning operation shown in FIG. 8.
- 7 is a timing chart showing another specific example of the scanning operation on the active matrix substrate shown in FIG. 6.
- 11 is a timing chart illustrating an operation example of the gate driver illustrated in FIG. 7 in the scanning operation illustrated in FIG. 10.
- FIG. 11 is a diagram for explaining a problem when the scanning operation shown in FIG. 10 is performed on the active matrix substrate shown in FIG. 3.
- FIG. 1 is a schematic cross-sectional view illustrating a liquid crystal display device according to a first embodiment of the present invention.
- the liquid crystal display device 1 according to the present embodiment includes a liquid crystal panel 2 as a display unit installed on the upper side of the figure as a viewing side (display side), and a non-display side of the liquid crystal panel 2 (lower side of the figure).
- an illuminating device 3 that generates illumination light that illuminates the liquid crystal panel 2.
- the liquid crystal panel 2 is provided on the liquid crystal layer 4, the active matrix substrate 5 and the color filter substrate 6 of the present invention sandwiching the liquid crystal layer 4, and the outer surfaces of the active matrix substrate 5 and the color filter substrate 6, respectively.
- Polarizing plates 7 and 8 are provided.
- the liquid crystal panel 2 is provided with a driver device 9 for driving the liquid crystal panel 2 and a drive circuit device 10 connected to the driver device 9 via the flexible printed circuit board 11.
- the liquid crystal layer 4 can be driven pixel by pixel.
- the polarization state of the illumination light incident through the polarizing plate 7 is modulated by the liquid crystal layer 4 and the amount of light passing through the polarizing plate 8 is controlled, so that a desired image is displayed. Is done.
- the liquid crystal mode and pixel structure of the liquid crystal panel 2 are arbitrary. Moreover, the drive mode of the liquid crystal panel 2 is also arbitrary. That is, as the liquid crystal panel 2, any liquid crystal panel that can display information can be used. Therefore, the detailed structure of the liquid crystal panel 2 is not shown in FIG.
- the illuminating device 3 is provided with a bottomed chassis 12 opened on the upper side (liquid crystal panel 2 side) in the figure, and a frame-like frame 13 installed on the liquid crystal panel 2 side of the chassis 12.
- the chassis 12 and the frame 13 are made of metal or synthetic resin and are sandwiched by a bezel 14 having an L-shaped cross section in a state where the liquid crystal panel 2 is installed above the frame 13.
- the illuminating device 3 is assembled to the liquid crystal panel 2 and integrated as a transmissive liquid crystal display device 1 in which illumination light from the illuminating device 3 enters the liquid crystal panel 2.
- the illumination device 3 is provided on the inner surface of the chassis 12, the diffusion plate 15 installed so as to cover the opening of the chassis 12, the optical sheet 17 installed on the liquid crystal panel 2 side above the diffusion plate 15.
- the reflection sheet 21 is provided.
- a plurality of, for example, six cold cathode fluorescent tubes 20 are provided inside the chassis 12 on the lower side of the liquid crystal panel 2 to constitute a direct-type lighting device 3.
- the light from each cold cathode fluorescent tube 20 is radiate
- the configuration using the direct illumination device 3 has been described.
- the present embodiment is not limited to this, and an edge light illumination device having a light guide plate may be used.
- the illuminating device which has other light sources, such as hot cathode fluorescent tubes other than a cold cathode fluorescent tube, and LED, can also be used.
- the diffusion plate 15 is made of, for example, a rectangular synthetic resin or glass material having a thickness of about 2 mm, and diffuses light from the cold cathode fluorescent tube 20 and emits the light to the optical sheet 17 side.
- the diffusion plate 15 is mounted on a frame-like surface provided on the upper side of the chassis 12 on the four sides, and the surface of the chassis 12 and the surface of the frame 13 are interposed with an elastically deformable pressing member 16 interposed therebetween. It is incorporated in the lighting device 3 in a state of being held between the inner surface and the inner surface. Further, the diffusion plate 15 is supported at its substantially central portion by a transparent support member (not shown) installed inside the chassis 12, and is prevented from bending inside the chassis 12.
- the diffusion plate 15 is movably held between the chassis 12 and the pressing member 16, and the diffusion plate is affected by heat such as heat generation of the cold cathode fluorescent tube 20 and temperature rise inside the chassis 12. 15, even when expansion (plastic) deformation occurs, the pressing member 16 is elastically deformed so that the plastic deformation is absorbed and the diffusibility of light from the cold cathode fluorescent tube 20 is not reduced as much as possible. Yes. Further, the use of the diffusion plate 15 made of a glass material that is more resistant to heat than the synthetic resin is preferable in that warpage, yellowing, thermal deformation, and the like due to the influence of the heat are less likely to occur.
- the optical sheet 17 includes a light collecting sheet made of, for example, a synthetic resin film having a thickness of about 0.5 mm, and is configured to increase the luminance of the illumination light to the liquid crystal panel 2.
- the optical sheet 17 may be appropriately laminated with known optical sheet materials such as a prism sheet, a diffusion sheet, and a polarizing sheet for improving display quality on the display surface of the liquid crystal panel 2 as necessary. It has become.
- the optical sheet 17 converts the light emitted from the diffusion plate 15 into planar light having a predetermined luminance (for example, 10000 cd / m 2 ) or more and uniform luminance, and is used as illumination light for the liquid crystal panel 2. It is comprised so that it may inject into the side.
- an optical member such as a diffusion sheet for adjusting the viewing angle of the liquid crystal panel 2 may be appropriately stacked above the liquid crystal panel 2 (display surface side).
- a protruding portion that protrudes to the left in FIG. 1 is formed at the central portion on the left end side in FIG. 1 that is on the upper side when the liquid crystal display device 1 is actually used.
- the protruding portion is sandwiched between the inner surface of the frame 13 and the pressing member 16 with the elastic material 18 interposed therebetween.
- the optical sheet 17 can be expanded and contracted inside the lighting device 3. Built in state. Thereby, in the optical sheet 17, even when expansion / contraction (plastic) deformation occurs due to the influence of the heat such as the heat generation of the cold cathode fluorescent tube 20, free expansion / contraction deformation based on the protruding portion becomes possible.
- the optical sheet 17 is configured to prevent wrinkles and deflections from occurring as much as possible. As a result, in the liquid crystal display device 1, it is possible to prevent the display quality of the liquid crystal panel 2 from being deteriorated as much as possible due to the bending of the optical sheet 17 or the like on the display surface of the liquid crystal panel 2.
- Each cold cathode fluorescent tube 20 is a straight tube, and electrode portions (not shown) provided at both ends thereof are supported outside the chassis 12.
- each cold cathode fluorescent tube 20 is a thin tube having a diameter of about 3.0 to 4.0 mm and excellent in luminous efficiency.
- Each cold cathode fluorescent tube 20 includes a light source holder (not shown).
- the distance between each of the diffusion plate 15 and the reflection sheet 21 is held in the chassis 12 in a state where the distance is maintained at a predetermined distance.
- the cold cathode fluorescent tube 20 is arranged so that its longitudinal direction is parallel to a direction orthogonal to the direction of gravity action. As a result, in the cold cathode fluorescent tube 20, mercury (vapor) enclosed therein is prevented from gathering on one end side in the longitudinal direction due to the action of gravity, and the lamp life is greatly improved. Yes.
- the reflection sheet 21 is made of a metal thin film having a high light reflectance such as aluminum or silver having a thickness of about 0.2 to 0.5 mm, for example, and reflects light from the cold cathode fluorescent tube 20 toward the diffusion plate 15. To function as a reflector. Thereby, in the illuminating device 3, the light emitted from the cold cathode fluorescent tube 20 can be efficiently reflected to the diffusion plate 15 side, and the use efficiency of the light and the luminance at the diffusion plate 15 can be increased.
- a reflective sheet material made of synthetic resin is used in place of the metal thin film, or the inner surface of the chassis 12 is reflected by applying a paint having a high light reflectance such as white. It can also function as a plate.
- FIG. 2 is a diagram for explaining a main configuration of the active matrix substrate and the liquid crystal display device according to the first embodiment
- FIG. 3 is a diagram for explaining a specific configuration of the active matrix substrate.
- the liquid crystal display device 1 includes a panel control unit 22 that performs drive control of the liquid crystal panel 2 (FIG. 1) as the display unit that displays information such as characters and images, A plurality of, for example, 10 source drivers 23-1, 23-2,..., 23-9, 23-10 (hereinafter referred to as “23”) that operate based on the instruction signal from the panel control unit 22. ) And a plurality of, for example, six gate drivers 24-1, 24-2,..., 24-5, 24-6 (hereinafter collectively referred to as “24”).
- the panel control unit 22 is provided in the drive circuit device 10 (FIG. 1), and receives a video signal from the outside of the liquid crystal display device 1.
- the panel control unit 22 performs predetermined image processing on the input video signal to generate instruction signals to the source driver 23 and the gate driver 24, and the input video signal.
- a frame buffer 22b capable of storing display data for one frame included.
- the panel control unit 22 performs drive control of the source driver 23 and the gate driver 24 in accordance with the input video signal, so that information corresponding to the video signal is displayed on the liquid crystal panel 2.
- the source driver 23 and the gate driver 24 are provided in the drive device 9 (FIG. 1), and are installed on the active matrix substrate 5 of the present embodiment that constitutes the array substrate. Specifically, the source drivers 23-1 to 23-10 are arranged along the lateral direction of the liquid crystal panel 2 on the surface of the active matrix substrate 5 in the outer area of the effective display area A of the liquid crystal panel 2 as a display panel. Are installed in a straight line. Further, the gate drivers 24-1 to 24-6 are linear on the surface of the active matrix substrate 5 so as to extend along the vertical direction (scanning direction described later) of the liquid crystal panel 2 in the outer region of the effective display region A. Is installed.
- the source driver 23 and the gate driver 24 are drive circuits that drive a plurality of pixels P provided in the liquid crystal panel 2 in units of pixels.
- the source driver 23 and the gate driver 24 include a plurality of source lines S1 to SM. (M is an integer of 10 or more, hereinafter collectively referred to as “S”) and a plurality of gate wirings G1 to GN (N is an integer of 6 or more and is hereinafter collectively referred to as “N”). It is connected. Further, the same number of source lines S are connected to the source drivers 23-1 to 23-10, and the same number of gate lines G are connected to the gate drivers 24-1 to 24-6.
- (M / 10) source lines S are connected to each of the source drivers 23-1 to 23-10, and a voltage signal corresponding to the video signal is input from the source driver 23 to the source line S. Function as data wiring.
- (N / 6) gate wirings G are connected to each of the gate drivers 24-1 to 24-6, and the scanning signals from the gate driver 24 as the scanning wiring driving circuit are sequentially supplied to the gate wiring G. By being input, it functions as a scanning wiring for performing a scanning operation.
- the number of terminals connected to the gate wiring G and the number of empty terminals not connected to the gate wiring G are set. Is 1 ⁇ 2 of the total number of terminals (details will be described later).
- the source lines S and the gate lines G are arranged in a matrix form at least in the effective display area A, and the areas of the plurality of pixels P are formed in the areas partitioned in the matrix form. ing. More specifically, as illustrated in FIG. 2, the source wiring S includes source wiring main body portions S1b, S2b, S3b,... Arranged in parallel to the vertical direction of the liquid crystal panel 2, and these source wiring main body portions. Connection wires S1a, S2a, S3a,... For connecting the source drivers 23-1 to 23-10 corresponding to S1b, S2b, S3b,. Similarly, the gate wiring G includes gate wiring main body portions G1b, G2b,...
- the connection wiring portions S1a, S2a, S3a,... Connect the source drivers 23-1 to 23-10 corresponding to the source wiring main body portions S1b, S2b, S3b,. Therefore, the resistance value in each of the connection wiring portions S1a, S2a, S3a,... Is not increased as much as possible.
- the connection wiring portions G1a, G2a,... Connect the gate drivers 24-1 to 24-6 corresponding to the gate wiring main body portions G1b, G2b,... So that the distance is not as long as possible.
- the resistance values at the connection wiring portions G1a, G2a,... Are not increased as much as possible.
- the plurality of pixels P include red, green, and blue pixels. Further, these red, green, and blue pixels are sequentially arranged in parallel with the gate wiring main body portions G1b, g2b,.
- the gate of the switching element 25 provided for each pixel P is connected to the gate wiring main body portions G1b, g2b,.
- the source of the switching element 25 is connected to the source wiring body portions S1b, S2b, S3b,.
- a pixel electrode 26 provided for each pixel P is connected to the drain of each switching element 25.
- the common electrode 27 is configured to face the pixel electrode 26 with the liquid crystal layer 4 (FIG. 1) provided on the liquid crystal panel 2 interposed therebetween.
- the gate driver 24 sequentially outputs a scanning signal for turning on the gate of the corresponding switching element 25 to the gate wirings G1 to GN based on the instruction signal from the image processing unit 22a.
- the source driver 23 outputs a voltage signal (gradation voltage) corresponding to the luminance (gradation) of the display image to the corresponding source lines S1 to SM based on the instruction signal from the image processing unit 22a.
- FIG. 4 is a block diagram showing a specific configuration of the gate driver shown in FIG.
- the gate driver 24 has a control logic 24a to which an instruction signal from the image processing unit 22a (FIG. 2) is input, and a bidirectional register 24b and a level shifter 24c connected to the control logic 24a. , OGx for outputting a scanning signal, for example, X (X is an integer of 2 or more), and an output circuit 24d connected to the level shifter 24c is provided.
- the vertical shift clock signal GCK and the output enable signal GOE are input to the control logic 24a from the image processing unit 22a.
- the control logic 24a is supplied with a high-level power supply voltage VCC and a low-level power supply voltage GND for the logic, and drives the bidirectional register 24b based on an instruction signal from the image processing section 22a. Necessary control signals are generated to operate the bidirectional register 24b.
- the bidirectional register 24b outputs a start signal for starting output of the scanning signal to the level shifter 24c via the control logic 24a in accordance with the control signal from the control logic 24a.
- the bidirectional register 24b sequentially outputs scanning signals to the level shifter 24c.
- the level shifter 24c is supplied with a high-level power supply voltage VGH and a low-level power supply voltage VGL for driving the liquid crystal. Further, when the start signal from the bidirectional register 24b is input to the level shifter 24c and the scanning signal is sequentially input, the level of the scanning signal is sequentially shifted between the high level and the low level, and the scanning signal Are sequentially output to the output circuit 24d. Thus, the level shifter 24c outputs a scanning signal in a predetermined scanning direction from the output circuit 24d.
- the output circuit 24d only X / 2 terminals among the X terminals OG1, OG2,... OGx are connected to the gate wiring G as shown in FIG. That is, in the output circuit 24d, only the terminals OG1 to OG (x / 2) provided on the upper side of FIG. 3 are connected to the gate wiring G, and the terminals OG (x / 2 + 1) to OG provided on the lower side of FIG. OGx is not connected to the gate line G and is a free terminal.
- the output circuit 24d sequentially outputs scanning signals in the order from the terminal OG1 to the terminal OGx (that is, the scanning direction from the upper side to the lower side in FIG. 3).
- the six gate drivers 24-1 to 24-6 are configured to sequentially output scanning signals in the order provided along the scanning direction from the upper side to the lower side in FIG. It is configured.
- FIG. 5 is a timing chart showing the scanning operation on the active matrix substrate.
- the gate driver 24-1 sequentially outputs a scanning signal from the terminal OG1 from the time point T1, and outputs a scanning signal from the terminal OG (x / 2) at the time point T2. Then, the scanning signal output operation from the terminals OG1 to OG (x / 2) connected to the gate wiring G is completed, and as shown in FIG. 5 (m), between the time point T1 and the time point T2, A scanning operation is performed in the display area including the gate line G connected to the gate driver 24-1.
- the scanning signal is output to the vacant terminals OG (x / 2 + 1) to OGx during the period from the time point T2 to the time point T3 (the period indicated by hatching in the drawing).
- these empty terminals OG (x / 2 + 1) to OGx are not connected to the gate wiring G, they do not contribute to the display operation on the liquid crystal panel 2 (the same applies to the gate drivers 24-2 to 24-6). .)
- the image processing unit 22a outputs an instruction signal GSP2 for instructing the start of the scanning operation to the second gate driver 24-2 from the upper side immediately before the time point T2.
- the scanning signal is sequentially output from the terminal OG1 from the time point T2, and the scanning signal is output from the terminal OG (x / 2) at the time point T3.
- the scanning signal output operation from the terminals OG1 to OG (x / 2) connected to the gate wiring G is completed, and as shown in FIG. 5 (m), between the time T2 and the time T3, A scanning operation is performed in the display area including the gate line G connected to the gate driver 24-2.
- the image processing unit 22a outputs an instruction signal GSP3 for instructing the start of the scanning operation to the third gate driver 24-3 from the top immediately before the time T3.
- the gate driver 24-3 sequentially outputs the scanning signal from the terminal OG1 from the time point T3, and outputs the scanning signal from the terminal OG (x / 2) at the time point T4.
- the scanning signal output operation from the terminals OG1 to OG (x / 2) connected to the gate wiring G is completed, and as shown in FIG. 5 (m), between the time T3 and the time T4, A scanning operation is performed in the display area including the gate line G connected to the gate driver 24-3.
- the image processing unit 22a outputs an instruction signal GSP4 for instructing the start of the scanning operation to the fourth gate driver 24-4 from the top immediately before the time point T4.
- the scanning signal is sequentially output from the terminal OG1 from the time point T4, and the scanning signal is output from the terminal OG (x / 2) at the time point T5.
- the scanning signal output operation from the terminals OG1 to OG (x / 2) connected to the gate wiring G is completed, and as shown in FIG. 5 (m), between time T4 and time T5, A scanning operation is performed in the display area including the gate line G connected to the gate driver 24-4.
- the image processing unit 22a outputs an instruction signal GSP5 for instructing the start of the scanning operation to the fifth gate driver 24-5 from the upper side immediately before the time T5.
- the scanning signal is sequentially output from the terminal OG1 from the time point T5, and the scanning signal is output from the terminal OG (x / 2) at the time point T6.
- the scanning signal output operation from the terminals OG1 to OG (x / 2) connected to the gate wiring G is completed, and as shown in FIG. 5 (m), between the time T5 and the time T6, A scanning operation is performed in the display area including the gate line G connected to the gate driver 24-5.
- gate drivers 24-1 to 24-6 are linearly provided along the scanning direction. These gate drivers 24-1 to 24-6 are provided with empty terminals that are not connected to the gate wirings (scanning wirings) G1 to GN.
- the scanning wiring driving circuit (gate driver 24) and the scanning wiring (gate wiring main body portions G1b, G2b,... ) Can be suppressed from increasing in resistance value of the connection wiring (connection wiring portions G1a, G2a,).
- the active matrix substrate 5 capable of appropriately performing the scanning operation even when the panel size is increased can be easily configured.
- each of the X terminals OG1, OG2,..., OGx is configured using six gate drivers in which only X / 2 terminals are connected to the gate wiring G.
- three gate drivers having all X terminals connected to the gate wiring are used.
- the length of the scanning wiring is a maximum of 1/3 of the vertical length of the active matrix substrate.
- the length of the scanning wiring is a maximum of 1/6 of the length in the vertical direction of the active matrix substrate.
- the active matrix substrate 5 that can appropriately perform the scanning operation even when the panel size is increased is used for the liquid crystal panel (display unit) 2. Even when the screen is enlarged and / or the definition is increased, the liquid crystal display device 1 having excellent display performance can be easily configured.
- FIG. 6 is a diagram illustrating a specific configuration of an active matrix substrate according to the second embodiment of the present invention.
- the main difference between this embodiment and the first embodiment is that, in the gate driver provided on one end side in the scanning direction, a terminal connected to the gate wiring and an empty terminal not connected to the gate wiring. Are sequentially provided along the scanning direction in this order, and in the gate driver provided on the other end side in the scanning direction, an empty terminal not connected to the gate wiring and a terminal connected to the gate wiring are scanned in this order. It is the point provided sequentially along the direction.
- symbol is attached
- gate drivers 34-1 to 34-6 are included in the active matrix substrate 5. On the surface, it is installed in a straight line along the vertical direction (scanning direction) of the liquid crystal panel 2 in the outer region of the effective display region A.
- the same number of gate wirings G are connected as in the first embodiment.
- the number of terminals connected to the gate wiring G and the number of empty terminals not connected to the gate wiring G are set. Is 1 ⁇ 2 of the total number of terminals.
- the active matrix substrate 5 of the present embodiment is provided on the upper side (one end side in the scanning direction) and the lower side (the other end side in the scanning direction) of FIG. 6 as illustrated in FIG.
- the gate drivers 34-1 and 34-6 are configured so that the terminals connected to the gate line G and the vacant terminals not connected to the gate line G are different from each other.
- the active matrix substrate 5 of the present embodiment is configured so that the scanning direction in the scanning operation by the gate driver 34 can be easily reversed (details will be described later).
- FIG. 7 is a block diagram showing a specific configuration of the gate driver shown in FIG.
- the gate driver 34 has a control logic 34a to which an instruction signal from the image processing unit 22a (FIG. 2) is input, and the control logic 34a, as in the first embodiment.
- a circuit 34d is provided.
- the gate driver 34-6 is provided in the order of the empty terminal not connected to the gate wiring G and the terminal connected to the gate wiring G. It has been. That is, in the gate drivers 34-1 to 34-5, as in the first embodiment, among the terminals OG1 to OGx provided in the output circuit 34d, the terminals OG1 to OG provided on the upper side in FIG. Only (x / 2) is connected to the gate line G, and terminals OG (x / 2 + 1) to OGx provided on the lower side of FIG. On the other hand, in the gate driver 34-6, the terminals OG1 to OG (x / 2) provided on the upper side of FIG. 6 are not connected to the gate wiring G but are vacant terminals, and the terminals provided on the lower side of FIG. Only OG (x / 2 + 1) to OGx are connected to the gate line G.
- the gate driver 34 is configured so that the scanning direction in the scanning operation can be reversed.
- a terminal for switching the scanning direction is provided in the control logic 34a. That is, in the control logic 34a, the scanning operation by the gate drivers 34-1 to 34-6 is the same as the scanning operation in the scanning direction from the upper side to the lower side in FIG. 6 (hereinafter referred to as “normal scan”).
- a switching signal LBR instructing switching of the scanning operation in the scanning direction from the lower side to the upper side (hereinafter referred to as “reverse scanning”) is input from the image processing unit 22a. More specifically, in the gate driver 34, when the switching signal LBR is at a low level and a high level, a normal scan and a reverse scan are performed, respectively.
- control logic 34a input / output terminals GSPOI and GSPIO for inputting / outputting a control signal for notifying start of scanning signal output are provided in the control logic 34a. That is, in the gate driver 34, when a normal scan is performed, a control signal for notifying the subsequent gate driver 34 in the scanning direction of the start of scanning signal output is output from the input / output terminal GSPIO. The signal is input to the input / output terminal GSPOI provided in the gate driver 34. When reverse scanning is performed, the functions of the input / output terminals GSPOI and GSPIO are reversed from those in the normal scanning, and control signals for notifying the start of scanning signal output are input / output.
- FIG. 8 is a timing chart showing a specific example of the scanning operation on the active matrix substrate shown in FIG. 6, and FIG. 9 shows an operation example of the gate driver shown in FIG. 7 in the scanning operation shown in FIG. It is a timing chart.
- FIG. 10 is a timing chart showing another specific example of the scanning operation on the active matrix substrate shown in FIG. 6, and FIG. 11 is an operation example of the gate driver shown in FIG. 7 in the scanning operation shown in FIG. It is a timing chart which shows.
- the gate driver 34-1 sequentially outputs the scanning signal from the terminal OG1 from the time point T8, and outputs the scanning signal from the terminal OG (x / 2) at the time point T9. Then, the scanning signal output operation from the terminals OG1 to OG (x / 2) connected to the gate wiring G is completed, and as shown in FIG. 8 (m), between the time T8 and the time T9, A scanning operation is performed in the display area including the gate line G connected to the gate driver 34-1.
- the scanning signal is output to the vacant terminals OG (x / 2 + 1) to OGx during a period from time T9 to time T10 (a period indicated by hatching in the drawing).
- these empty terminals OG (x / 2 + 1) to OGx are not connected to the gate wiring G, they do not contribute to the display operation on the liquid crystal panel 2 (the same applies to the gate drivers 34-2 to 34-5). .
- the image processing unit 22a outputs an instruction signal GSP2 for instructing the start of the scanning operation to the second gate driver 34-2 from the upper side immediately before time T9.
- the scanning signal is sequentially output from the terminal OG1 from the time point T9, and the scanning signal is output from the terminal OG (x / 2) at the time point T3.
- the scanning signal output operation from the terminals OG1 to OG (x / 2) connected to the gate wiring G is completed, and as shown in FIG. 8 (m), between time T9 and time T10, A scanning operation is performed in the display area including the gate line G connected to the gate driver 34-2.
- the gate driver 34-2 when the control signal from the gate driver 34-1 is input to the input / output terminal GSPOI, the terminals OG1 to OGx are changed to those shown in FIG. As shown in FIG. 9 (k), scanning signals are sequentially output in synchronization with the vertical shift clock signal GCK shown in FIG. 9 (a).
- the gate driver 34-2 outputs a control signal from the input / output terminal GSPIO to the gate driver 34-3 in synchronization with the scanning signal output operation at the terminal OGx. As a result, the gate driver 34-3 notifies the gate driver 34-2 of the start of scanning signal output.
- the image processing unit 22a instructs the third gate driver 34-3 from the upper side to start the scanning operation immediately before time T10.
- the gate driver 34-3 sequentially outputs the scanning signal from the terminal OG1 from the time point T10, and outputs the scanning signal from the terminal OG (x / 2) at the time point T11. Is done. Then, the scanning signal output operation from the terminals OG1 to OG (x / 2) connected to the gate wiring G is completed, and as shown in FIG. 8 (m), between time T10 and time T11, A scanning operation is performed in the display area including the gate line G connected to the gate driver 34-3.
- the image processing unit 22a outputs an instruction signal GSP4 for instructing the start of the scanning operation to the fourth gate driver 34-4 from the top immediately before time T11.
- the gate driver 34-4 sequentially outputs the scanning signal from the terminal OG1 from the time point T11, and outputs the scanning signal from the terminal OG (x / 2) at the time point T12.
- the scanning signal output operation from the terminals OG1 to OG (x / 2) connected to the gate wiring G is completed, and as shown in FIG. 8 (m), between the time T11 and the time T12, A scanning operation is performed in the display area including the gate line G connected to the gate driver 34-4.
- the image processing unit 22a outputs an instruction signal GSP5 for instructing the start of the scanning operation to the fifth gate driver 34-5 from the upper side immediately before time T12.
- the gate driver 34-5 sequentially outputs the scanning signal from the terminal OG1 from the time point T12, and outputs the scanning signal from the terminal OG (x / 2) at the time point T13.
- the scanning signal output operation from the terminals OG1 to OG (x / 2) connected to the gate wiring G is completed, and as shown in FIG. 8 (m), between the time T12 and the time T13, A scanning operation is performed in the display area including the gate line G connected to the gate driver 34-5.
- the image processing unit 22a outputs an instruction signal GSP6 instructing the start of the scanning operation to the gate driver 34-6 immediately before the time T12. That is, in this embodiment, the image processing unit 22a outputs the instruction signals GSP5 and GSP6 at the same timing.
- the scanning signal is output to the vacant terminals OG1 to OG (x / 2) in the period from the time T12 to the time T13 (the period indicated by hatching in the drawing).
- these vacant terminals OG1 to OG (x / 2) are not connected to the gate line G and thus do not contribute to the display operation on the liquid crystal panel 2.
- the gate driver 34-6 sequentially outputs the scanning signal from the terminal OG (x / 2 + 1) from the time point T6, and outputs the scanning signal from the terminal OGx at the time point T14. Then, the scanning signal output operation from the terminals OG (x / 2 + 1) to OGx connected to the gate wiring G is completed, and as shown in FIG. 8 (m), between the time T13 and the time T14, A scanning operation is performed in the display area including the gate line G connected to the gate driver 34-6. Thereby, one scanning operation on the entire surface of the liquid crystal panel 2 is completed.
- the scanning signal is sequentially output from the terminal OGx from the time point T15, and the scanning signal is output from the terminal OG (x / 2 + 1) at the time point T16. Then, the scanning signal output operation from the terminals OGx to OG (x / 2 + 1) connected to the gate wiring G is completed, and as shown in FIG. 10 (m), between time T15 and time T16, A scanning operation is performed in the display area including the gate line G connected to the gate driver 34-6.
- the scanning signal is output to the vacant terminals OG (x / 2) to OG1 in the period from the time T16 to the time T17 (the period indicated by hatching in the drawing).
- these empty terminals OG (x / 2) to OG1 are not connected to the gate wiring G, they do not contribute to the display operation on the liquid crystal panel 2.
- the image processing unit 22a outputs an instruction signal GSP5 for instructing the start of the scanning operation to the gate driver 34-5 immediately before time T15. That is, in this embodiment, the image processing unit 22a outputs the instruction signals GSP5 and GSP6 at the same timing.
- the scanning signal is output to the vacant terminals OG (x / 2 + 1) to OGx during the period from the time T15 to the time T16 (the period indicated by hatching in the drawing).
- these empty terminals OG (x / 2 + 1) to OGx are not connected to the gate wiring G, they do not contribute to the display operation on the liquid crystal panel 2 (the same applies to the gate drivers 34-2 to 34-5). .
- the gate driver 34-5 sequentially outputs the scanning signal from the terminal OG (x / 2) from the time point T16, and outputs the scanning signal from the terminal OG1 at the time point T17. Then, the scanning signal output operation from the terminals OG (x / 2) to OG1 connected to the gate wiring G is completed, and as shown in FIG. 10 (m), between the time T16 and the time T17, A scanning operation is performed in the display area including the gate line G connected to the gate driver 34-5.
- the gate driver 34-5 when the control signal from the gate driver 34-6 is inputted to the input / output terminal GSPIO, the terminals OGx to OG1 are changed to those shown in FIG. As shown in FIG. 11 (k), scanning signals are sequentially output in synchronization with the vertical shift clock signal GCK shown in FIG. 11 (a). Further, the gate driver 34-5 outputs a control signal from the input / output terminal GSPOI to the gate driver 34-4 in synchronization with the scanning signal output operation at the terminal OG1. As a result, the gate driver 34-4 is notified of the start of scanning signal output from the gate driver 34-5.
- the image processing unit 22a instructs the fourth gate driver 34-4 from the upper side to start the scanning operation immediately before time T16.
- the gate driver 34-4 sequentially outputs the scanning signal from the terminal OG (x / 2) from the time point T17, and outputs the scanning signal from the terminal OG1 at the time point T18. Is done. Then, the scanning signal output operation from the terminals OG (x / 2) to OG1 connected to the gate wiring G is completed, and as shown in FIG. 10 (m), between time T17 and time T18, A scanning operation is performed in the display area including the gate line G connected to the gate driver 34-4.
- the image processing unit 22a outputs an instruction signal GSP3 for instructing the start of the scanning operation to the third gate driver 34-3 from the upper side immediately before time T17.
- the gate driver 34-3 sequentially outputs the scanning signal from the terminal OG (x / 2) from the time point T18, and outputs the scanning signal from the terminal OG1 at the time point T19.
- the scanning signal output operation from the terminals OG (x / 2) to OG1 connected to the gate line G is completed, and as shown in FIG. 10 (m), between time T18 and time T19, A scanning operation is performed in the display area including the gate line G connected to the gate driver 34-3.
- the image processing unit 22a outputs the instruction signal GSP2 instructing the start of the scanning operation to the second gate driver 34-2 from the upper side immediately before the time T18.
- the gate driver 34-2 sequentially outputs the scanning signal from the terminal OG (x / 2) from the time point T19, and outputs the scanning signal from the terminal OG1 at the time point T20.
- the scanning signal output operation from the terminals OG (x / 2) to OG1 connected to the gate wiring G is completed, and as shown in FIG. 10 (m), between time T19 and time T20, A scanning operation is performed in the display area including the gate line G connected to the gate driver 34-2.
- the image processing unit 22a outputs an instruction signal GSP1 for instructing the start of the scanning operation to the first gate driver 34-1 from the top immediately before time T19.
- the gate driver 34-1 sequentially outputs the scanning signal from the terminal OG (x / 2) from the time point T20, and outputs the scanning signal from the terminal OG1 at the time point T21.
- the scanning signal output operation from the terminals OG (x / 2) to OG1 connected to the gate wiring G is completed, and as shown in FIG. 10 (m), between time T20 and time T21, A scanning operation is performed in the display area including the gate line G connected to the gate driver 34-1. Thereby, one scanning operation on the entire surface of the liquid crystal panel 2 is completed.
- the present embodiment can achieve the same operations and effects as the first embodiment. Further, in the active matrix substrate 5 of the present embodiment, as shown in FIGS. 8 and 10, the normal scan and the reverse scan can be appropriately performed, and the scanning direction can be easily reversed. As a result, the active matrix substrate 5 of the present embodiment can easily perform upside down driving. On the other hand, with the active matrix substrate 5 of the first embodiment, it is not easy to perform reverse scanning appropriately.
- the image processing unit 22a needs to output the instruction signal GSP6 to the gate driver 24-6 before the period from the time T23 to the time T24 when the scanning operation in the display area including the gate wiring G is performed.
- the display device of the present invention is anything as long as a display panel including an active matrix substrate is used for a display portion. It is not limited.
- the display device of the present invention includes an active matrix substrate having a plurality of data lines and a plurality of scanning lines arranged in a matrix, and a plurality of pixels provided in the vicinity of the intersection of the data lines and the scanning lines. Anything used may be used.
- the display device of the present invention uses a transflective or reflective liquid crystal panel or an active matrix substrate such as an organic EL (Electronic Luminescence) element, an inorganic EL element, or a field emission display. It can be applied to various display devices.
- a transflective or reflective liquid crystal panel or an active matrix substrate such as an organic EL (Electronic Luminescence) element, an inorganic EL element, or a field emission display. It can be applied to various display devices.
- the gate driver scanning wiring driving circuit
- a terminal connected to the gate wiring scanning wiring
- an empty space not connected to the gate wiring in this order, the terminals are sequentially provided along the scanning direction, and in the gate driver provided on the other end side in the scanning direction, the empty terminals not connected to the gate wiring and the terminals connected to the gate wiring are arranged in this order. The case where they are sequentially provided along the scanning direction has been described.
- the present invention is not limited to this, and in a plurality of scanning wiring driving circuits, in a scanning wiring driving circuit provided on one end side in the scanning direction, a terminal connected to the scanning wiring is one end in the scanning direction.
- the terminals connected to the scanning wiring are the one end side and the other end in the scanning direction. What is necessary is just to be provided in the other side of the part side. Thus, it is possible to easily perform upside down driving for inverting the scanning direction and displaying the image accurately upside down.
- a terminal connected to the scanning wiring may be provided on one end side.
- the configuration as in the second embodiment is preferable in that it is possible to more easily perform the upside down driving in which the scanning direction is reversed and the image is accurately displayed upside down. .
- the present invention is not limited to this, and the present invention is not limited to this, as long as an empty terminal not connected to the scanning wiring is provided in the scanning wiring driving circuit. It is not limited.
- the number of terminals connected to the scanning wiring is set to be the same, and the number of empty terminals not connected to the scanning wiring is the same.
- the setting is preferable in that the load applied to all the scanning wiring drive circuits can be made uniform and the scanning operation can be easily performed.
- the number of terminals connected to the scanning wiring is set to the same number as the number of empty terminals not connected to the scanning wiring.
- the connection operation between the scanning wiring drive circuit and the scanning wiring can be simplified and the scanning operation can be performed more easily.
- the present invention is useful for an active matrix substrate capable of appropriately performing a scanning operation even when the panel size is increased, and a high-performance display device using the active matrix substrate.
Abstract
Description
前記複数の走査配線に対して、所定の走査方向で走査信号を順次出力する複数の走査配線駆動回路を、当該走査方向に沿うように設けるとともに、
前記複数の走査配線駆動回路全てに、前記走査配線に接続されない空き端子を設けたことを特徴とするものである。
前記走査方向の他端部側に設けられた走査配線駆動回路では、前記走査配線に接続される端子が前記走査方向の一端部側及び他端部側の他方側に設けられてもよい。
前記走査方向の他端部側に設けられた走査配線駆動回路では、前記走査配線に接続されない空き端子と前記走査配線に接続される端子とがこの順番で前記走査方向に沿って順次設けられていることが好ましい。
前記表示部には、上記いずれかに記載のアクティブマトリクス基板が用いられている。
図1は、本発明の第1の実施形態にかかる液晶表示装置を説明する概略断面図である。図において、本実施形態の液晶表示装置1には、図の上側が視認側(表示面側)として設置される表示部としての液晶パネル2と、液晶パネル2の非表示面側(図の下側)に配置されて、当該液晶パネル2を照明する照明光を発生する照明装置3とが設けられている。
図6は、本発明の第2の実施形態にかかるアクティブマトリクス基板の具体的な構成を説明する図である。図において、本実施形態と上記第1の実施形態との主な相違点は、走査方向の一端部側に設けられたゲートドライバでは、ゲート配線に接続される端子とゲート配線に接続されない空き端子とをこの順番で走査方向に沿って順次設けるとともに、走査方向の他端部側に設けられたゲートドライバでは、ゲート配線に接続されない空き端子とゲート配線に接続される端子とをこの順番で走査方向に沿って順次設けた点である。なお、上記第1の実施形態と共通する要素については、同じ符号を付して、その重複した説明を省略する。
Claims (6)
- マトリクス状に配列された複数のデータ配線及び複数の走査配線と、前記データ配線と前記走査配線との交差部の近傍に設けられた複数の画素を備え、表示パネルの基板として用いられるアクティブマトリクス基板であって、
前記複数の走査配線に対して、所定の走査方向で走査信号を順次出力する複数の走査配線駆動回路を、当該走査方向に沿うように設けるとともに、
前記複数の走査配線駆動回路全てに、前記走査配線に接続されない空き端子を設けた、
ことを特徴とするアクティブマトリクス基板。 - 前記複数の走査配線駆動回路において、前記走査方向の一端部側に設けられた走査配線駆動回路では、前記走査配線に接続される端子が前記走査方向の一端部側及び他端部側の一方側に設けられ、かつ、
前記走査方向の他端部側に設けられた走査配線駆動回路では、前記走査配線に接続される端子が前記走査方向の一端部側及び他端部側の他方側に設けられている請求項1に記載のアクティブマトリクス基板。 - 前記複数の走査配線駆動回路において、前記走査方向の一端部側に設けられた走査配線駆動回路では、前記走査配線に接続される端子と前記走査配線に接続されない空き端子とがこの順番で前記走査方向に沿って順次設けられ、かつ、
前記走査方向の他端部側に設けられた走査配線駆動回路では、前記走査配線に接続されない空き端子と前記走査配線に接続される端子とがこの順番で前記走査方向に沿って順次設けられている請求項1または2に記載のアクティブマトリクス基板。 - 前記複数の走査配線駆動回路では、前記走査配線に接続される端子の設置数が同じに設定され、かつ、前記走査配線に接続されない空き端子の設置数が同じに設定されている請求項1~3のいずれか1項に記載のアクティブマトリクス基板。
- 前記複数の各走査配線駆動回路において、前記走査配線に接続される端子の設置数と、前記走査配線に接続されない空き端子の設置数とが同じ数に設定されている請求項1~4のいずれか1項に記載のアクティブマトリクス基板。
- 表示部を備えた表示装置であって、
前記表示部には、請求項1~5のいずれか1項に記載のアクティブマトリクス基板が用いられていることを特徴とする表示装置。
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US12/919,024 US8432384B2 (en) | 2008-03-21 | 2008-11-06 | Active matrix substrate and display device |
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- 2008-11-06 US US12/919,024 patent/US8432384B2/en active Active
- 2008-11-06 JP JP2010503740A patent/JP5049385B2/ja active Active
- 2008-11-06 CN CN2008801279857A patent/CN101971240A/zh active Pending
- 2008-11-06 EP EP08873490A patent/EP2246841A4/en not_active Withdrawn
- 2008-11-06 WO PCT/JP2008/070181 patent/WO2009116201A1/ja active Application Filing
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US10109231B2 (en) | 2016-07-26 | 2018-10-23 | Seiko Epson Corporation | Electrooptical device, method for controlling electrooptical device, and electronic apparatus |
Also Published As
Publication number | Publication date |
---|---|
CN101971240A (zh) | 2011-02-09 |
US20110032226A1 (en) | 2011-02-10 |
EP2246841A4 (en) | 2011-09-28 |
EP2246841A1 (en) | 2010-11-03 |
US8432384B2 (en) | 2013-04-30 |
JP5049385B2 (ja) | 2012-10-17 |
JPWO2009116201A1 (ja) | 2011-07-21 |
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