WO2009072605A1 - アレイプロセッサ向けアドレス生成装置と方法並びにアレイプロセッサ - Google Patents

アレイプロセッサ向けアドレス生成装置と方法並びにアレイプロセッサ Download PDF

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Publication number
WO2009072605A1
WO2009072605A1 PCT/JP2008/072155 JP2008072155W WO2009072605A1 WO 2009072605 A1 WO2009072605 A1 WO 2009072605A1 JP 2008072155 W JP2008072155 W JP 2008072155W WO 2009072605 A1 WO2009072605 A1 WO 2009072605A1
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WO
WIPO (PCT)
Prior art keywords
address generation
array processor
address
generation device
unit
Prior art date
Application number
PCT/JP2008/072155
Other languages
English (en)
French (fr)
Inventor
Tomoyoshi Kobori
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2009544737A priority Critical patent/JP5428862B2/ja
Priority to US12/746,468 priority patent/US8452943B2/en
Publication of WO2009072605A1 publication Critical patent/WO2009072605A1/ja

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8046—Systolic arrays

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

　シストリックアレイプロセッサ向けのアドレス生成装置において、より簡素なプロセッサとより少ない追加ハードウェアにより、効率的にメモリアクセスを行うことができ、かつ、クロックサイクル単位のタイミング制御を行うアドレス生成ユニットの提供。アドレス生成用プロセッサ（１０ａ、１０ｂ、・・・１０ｃ）では、ベースアドレス生成処理の他に、アドレス生成処理の開始と終了程度の制御を行い、クロックサイクル単位のアドレス変換の制御はタイミング制御ユニット（１６）で行い、アドレス生成用プロセッサ（１０ａ、１０ｂ、・・・１０ｃ）と、アドレス変換回路（１２）との処理速度の違いはバッファ（１５ａ、１５ｂ、・・・１５ｃ）により吸収する。
PCT/JP2008/072155 2007-12-06 2008-12-05 アレイプロセッサ向けアドレス生成装置と方法並びにアレイプロセッサ WO2009072605A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009544737A JP5428862B2 (ja) 2007-12-06 2008-12-05 アレイプロセッサ向けアドレス生成装置と方法並びにアレイプロセッサ
US12/746,468 US8452943B2 (en) 2007-12-06 2008-12-05 Apparatus and method for address generation for array processor and array processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007316099 2007-12-06
JP2007-316099 2007-12-06

Publications (1)

Publication Number Publication Date
WO2009072605A1 true WO2009072605A1 (ja) 2009-06-11

Family

ID=40717783

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/072155 WO2009072605A1 (ja) 2007-12-06 2008-12-05 アレイプロセッサ向けアドレス生成装置と方法並びにアレイプロセッサ

Country Status (3)

Country Link
US (1) US8452943B2 (ja)
JP (1) JP5428862B2 (ja)
WO (1) WO2009072605A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018005369A (ja) * 2016-06-29 2018-01-11 富士通株式会社 演算処理装置及び演算処理装置の制御方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI529579B (zh) * 2013-12-31 2016-04-11 Egalax Empia Technology Inc Touch panel of the integrated circuit device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0380343A (ja) * 1989-08-24 1991-04-05 Matsushita Electric Works Ltd 演算処理装置
JP2004102633A (ja) * 2002-09-09 2004-04-02 Sony Corp 演算システム

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0212432A (ja) * 1988-06-30 1990-01-17 Nec Corp データ処理装置
US5581778A (en) * 1992-08-05 1996-12-03 David Sarnoff Researach Center Advanced massively parallel computer using a field of the instruction to selectively enable the profiling counter to increase its value in response to the system clock
JP3391020B2 (ja) * 1994-03-14 2003-03-31 株式会社エフ・エフ・シー ダイナミックアドレス変換装置
JP3247018B2 (ja) * 1994-12-06 2002-01-15 富士通株式会社 アドレス生成装置
JPH0934784A (ja) * 1995-07-14 1997-02-07 Sony Corp データ書込み回路、データ読出し回路及びデータ伝送装置
US5854921A (en) * 1995-08-31 1998-12-29 Advanced Micro Devices, Inc. Stride-based data address prediction structure
US7844796B2 (en) * 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7805589B2 (en) * 2006-08-31 2010-09-28 Qualcomm Incorporated Relative address generation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0380343A (ja) * 1989-08-24 1991-04-05 Matsushita Electric Works Ltd 演算処理装置
JP2004102633A (ja) * 2002-09-09 2004-04-02 Sony Corp 演算システム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018005369A (ja) * 2016-06-29 2018-01-11 富士通株式会社 演算処理装置及び演算処理装置の制御方法

Also Published As

Publication number Publication date
US8452943B2 (en) 2013-05-28
US20100306496A1 (en) 2010-12-02
JP5428862B2 (ja) 2014-02-26
JPWO2009072605A1 (ja) 2011-04-28

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