WO2009066764A1 - 半導体集積回路装置及びそのテスト方法 - Google Patents

半導体集積回路装置及びそのテスト方法 Download PDF

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Publication number
WO2009066764A1
WO2009066764A1 PCT/JP2008/071230 JP2008071230W WO2009066764A1 WO 2009066764 A1 WO2009066764 A1 WO 2009066764A1 JP 2008071230 W JP2008071230 W JP 2008071230W WO 2009066764 A1 WO2009066764 A1 WO 2009066764A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor integrated
integrated circuit
circuit device
input signal
under test
Prior art date
Application number
PCT/JP2008/071230
Other languages
English (en)
French (fr)
Inventor
Koichi Nose
Masayuki Mizuno
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to US12/744,188 priority Critical patent/US8446162B2/en
Priority to JP2009542603A priority patent/JPWO2009066764A1/ja
Publication of WO2009066764A1 publication Critical patent/WO2009066764A1/ja

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

　半導体集積回路装置の入出力回路やテスタの動作周波数がテスト用の入力信号の周波数よりも低い場合において、半導体集積回路装置に備えた被測定回路の動作を停止させることなく、被測定回路の擾乱耐性量の測定を可能とする。半導体集積回路装置は、１又は２以上の入力信号から成る入力信号群の各入力信号に対する処理を順に被測定回路によって複数回にわたって繰り返した場合において、該入力信号群のうちの所定の入力信号に対して該被測定回路により正常な出力信号が出力された回数をカウントする正常出力信号カウンタを備える。
PCT/JP2008/071230 2007-11-21 2008-11-21 半導体集積回路装置及びそのテスト方法 WO2009066764A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/744,188 US8446162B2 (en) 2007-11-21 2008-11-21 Semiconductor integrated circuit device with test circuit and test method therefor
JP2009542603A JPWO2009066764A1 (ja) 2007-11-21 2008-11-21 半導体集積回路装置及びそのテスト方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-301127 2007-11-21
JP2007301127 2007-11-21

Publications (1)

Publication Number Publication Date
WO2009066764A1 true WO2009066764A1 (ja) 2009-05-28

Family

ID=40667586

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/071230 WO2009066764A1 (ja) 2007-11-21 2008-11-21 半導体集積回路装置及びそのテスト方法

Country Status (3)

Country Link
US (1) US8446162B2 (ja)
JP (1) JPWO2009066764A1 (ja)
WO (1) WO2009066764A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MX2018010985A (es) * 2016-03-17 2019-05-06 Jcu Corp Dispositivo generador de plasma.

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5246871A (en) * 1975-10-13 1977-04-14 Hitachi Ltd Device for measurement of automatic phase discriminating allowance
JP2001229699A (ja) * 2000-02-14 2001-08-24 Nec Corp テスト装置、及び、テスト方法
JP2002214300A (ja) * 2001-01-22 2002-07-31 Seiko Epson Corp 半導体装置
JP2006073081A (ja) * 2004-09-01 2006-03-16 Fujitsu Ltd Ｒａｍマクロ及びそれを使用した集積回路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3233559B2 (ja) * 1995-08-14 2001-11-26 シャープ株式会社 半導体集積回路のテスト方法および装置
US6535986B1 (en) 2000-03-14 2003-03-18 International Business Machines Corporation Optimizing performance of a clocked system by adjusting clock control settings and clock frequency
US20080232538A1 (en) * 2007-03-20 2008-09-25 Advantest Corporation Test apparatus and electronic device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5246871A (en) * 1975-10-13 1977-04-14 Hitachi Ltd Device for measurement of automatic phase discriminating allowance
JP2001229699A (ja) * 2000-02-14 2001-08-24 Nec Corp テスト装置、及び、テスト方法
JP2002214300A (ja) * 2001-01-22 2002-07-31 Seiko Epson Corp 半導体装置
JP2006073081A (ja) * 2004-09-01 2006-03-16 Fujitsu Ltd Ｒａｍマクロ及びそれを使用した集積回路

Also Published As

Publication number Publication date
US20100259292A1 (en) 2010-10-14
US8446162B2 (en) 2013-05-21
JPWO2009066764A1 (ja) 2011-04-07

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