WO2009066479A1 - 薄膜トランジスタ及びその製造方法 - Google Patents

薄膜トランジスタ及びその製造方法 Download PDF

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Publication number
WO2009066479A1
WO2009066479A1 PCT/JP2008/059258 JP2008059258W WO2009066479A1 WO 2009066479 A1 WO2009066479 A1 WO 2009066479A1 JP 2008059258 W JP2008059258 W JP 2008059258W WO 2009066479 A1 WO2009066479 A1 WO 2009066479A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin
film transistor
microcrystalline silicon
gate insulating
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/059258
Other languages
English (en)
French (fr)
Inventor
Masaharu Nishiura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Holdings Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Holdings Ltd filed Critical Fuji Electric Holdings Ltd
Priority to TW097133444A priority Critical patent/TW200935521A/zh
Publication of WO2009066479A1 publication Critical patent/WO2009066479A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739Conductor-insulator-semiconductor electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732Bottom-gate only TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743Silicon
    • H10D30/6746Amorphous silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6757Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40Crystalline structures

Landscapes

  • Thin Film Transistor (AREA)

Abstract

微結晶シリコンにより構成されたチャネル層を備える薄膜トランジスタを安価に製造する方法を提供することを目的とする。薄膜トランジスタ(400)の備えるイントリンシック微結晶シリコン層(404)は、次のように形成することができる。ゲート絶縁層(103)の形成後に、ゲート絶縁層(103)の表面を、予め定めた時間にわたり水素を流してプラズマ処理する。ついで、プラズマ処理を継続している間に、原料ガスを導入してイントリンシック微結晶シリコンにより構成されたイントリンシック微結晶シリコン層(404)をゲート絶縁層(103)上に形成する。微結晶シリコンは、いわば水素の海の中でシリコンが活性化されて凝集することにより形成されるということから、この方法は、ゲート絶縁層(103)の表面を水素で満たして活性化し、その状態でシリコンを導入するものである。
PCT/JP2008/059258 2007-11-22 2008-05-20 薄膜トランジスタ及びその製造方法 Ceased WO2009066479A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW097133444A TW200935521A (en) 2007-11-22 2008-09-01 Thin-film transistor and process for producing the thin-film transistor

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007-303665 2007-11-22
JP2007303665 2007-11-22
JP2008019658 2008-01-30
JP2008-019658 2008-01-30

Publications (1)

Publication Number Publication Date
WO2009066479A1 true WO2009066479A1 (ja) 2009-05-28

Family

ID=40667311

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/059258 Ceased WO2009066479A1 (ja) 2007-11-22 2008-05-20 薄膜トランジスタ及びその製造方法

Country Status (3)

Country Link
KR (1) KR20100086934A (ja)
TW (1) TW200935521A (ja)
WO (1) WO2009066479A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011133873A (ja) * 2009-11-24 2011-07-07 Semiconductor Energy Lab Co Ltd 表示装置
CN115132819A (zh) * 2022-07-28 2022-09-30 惠科股份有限公司 薄膜晶体管及其制备方法、显示面板

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI445181B (zh) 2012-02-08 2014-07-11 E Ink Holdings Inc 薄膜電晶體

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794749A (ja) * 1993-09-22 1995-04-07 Toshiba Corp 薄膜トランジスタの製造方法
JPH0897427A (ja) * 1994-07-27 1996-04-12 Sharp Corp 薄膜半導体素子および薄膜トランジスタ並びにその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794749A (ja) * 1993-09-22 1995-04-07 Toshiba Corp 薄膜トランジスタの製造方法
JPH0897427A (ja) * 1994-07-27 1996-04-12 Sharp Corp 薄膜半導体素子および薄膜トランジスタ並びにその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011133873A (ja) * 2009-11-24 2011-07-07 Semiconductor Energy Lab Co Ltd 表示装置
CN115132819A (zh) * 2022-07-28 2022-09-30 惠科股份有限公司 薄膜晶体管及其制备方法、显示面板
CN115132819B (zh) * 2022-07-28 2026-03-20 惠科股份有限公司 薄膜晶体管及其制备方法、显示面板

Also Published As

Publication number Publication date
TW200935521A (en) 2009-08-16
KR20100086934A (ko) 2010-08-02

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