WO2009066379A1 - ビア設計装置、ビア設計プログラム、ビア設計方法 - Google Patents

ビア設計装置、ビア設計プログラム、ビア設計方法 Download PDF

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Publication number
WO2009066379A1
WO2009066379A1 PCT/JP2007/072546 JP2007072546W WO2009066379A1 WO 2009066379 A1 WO2009066379 A1 WO 2009066379A1 JP 2007072546 W JP2007072546 W JP 2007072546W WO 2009066379 A1 WO2009066379 A1 WO 2009066379A1
Authority
WO
WIPO (PCT)
Prior art keywords
designing
via designing
shape
program
layers
Prior art date
Application number
PCT/JP2007/072546
Other languages
English (en)
French (fr)
Inventor
Hirofumi Mori
Jun Yamada
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/072546 priority Critical patent/WO2009066379A1/ja
Priority to JP2009542438A priority patent/JP5018893B2/ja
Publication of WO2009066379A1 publication Critical patent/WO2009066379A1/ja
Priority to US12/781,009 priority patent/US8429594B2/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09645—Patterning on via walls; Plural lands around one hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

　多層基板において複数の層の間を接続するビアの設計を行うビア設計装置であって、複数の層を貫く孔の一部に少なくとも１つの導電部を配置したビアについて、該ビアの形状を示す形状パラメータを設定する形状設定部と、形状設定部により設定された形状パラメータに基づいてビアのインピーダンスを算出するインピーダンス算出部とを備えた。
PCT/JP2007/072546 2007-11-21 2007-11-21 ビア設計装置、ビア設計プログラム、ビア設計方法 WO2009066379A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/072546 WO2009066379A1 (ja) 2007-11-21 2007-11-21 ビア設計装置、ビア設計プログラム、ビア設計方法
JP2009542438A JP5018893B2 (ja) 2007-11-21 2007-11-21 ビア設計装置、ビア設計プログラム、ビア設計方法
US12/781,009 US8429594B2 (en) 2007-11-21 2010-05-17 Via design apparatus and via design method based on impedance calculations

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/072546 WO2009066379A1 (ja) 2007-11-21 2007-11-21 ビア設計装置、ビア設計プログラム、ビア設計方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/781,009 Continuation US8429594B2 (en) 2007-11-21 2010-05-17 Via design apparatus and via design method based on impedance calculations

Publications (1)

Publication Number Publication Date
WO2009066379A1 true WO2009066379A1 (ja) 2009-05-28

Family

ID=40667217

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/072546 WO2009066379A1 (ja) 2007-11-21 2007-11-21 ビア設計装置、ビア設計プログラム、ビア設計方法

Country Status (3)

Country Link
US (1) US8429594B2 (ja)
JP (1) JP5018893B2 (ja)
WO (1) WO2009066379A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012085234A (ja) * 2010-10-14 2012-04-26 Ngk Spark Plug Co Ltd 伝送システム及び伝送装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107580409A (zh) * 2017-11-10 2018-01-12 郑州云海信息技术有限公司 一种新型过孔结构
CN111642085B (zh) * 2020-06-19 2021-08-31 苏州浪潮智能科技有限公司 一种印刷电路板制作方法、系统、设备及计算机存储介质

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09325983A (ja) * 1996-06-06 1997-12-16 Nippon Telegr & Teleph Corp <Ntt> 最適解計算方法
JP2002334956A (ja) * 2001-05-09 2002-11-22 Fujitsu Ltd 半導体装置の支持体及びその製造方法
JP2004158754A (ja) * 2002-11-08 2004-06-03 Mitsubishi Electric Corp 半導体装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0669660A (ja) 1992-03-26 1994-03-11 Nec Corp プリント配線板およびその製造方法
JP2776269B2 (ja) 1994-10-25 1998-07-16 日本電気株式会社 印刷配線板設計装置
US6025947A (en) * 1996-05-02 2000-02-15 Fujitsu Limited Controller which controls a variable optical attenuator to control the power level of a wavelength-multiplexed optical signal when the number of channels are varied
JP3306713B2 (ja) 1996-05-02 2002-07-24 富士通株式会社 光増幅装置
JP3532759B2 (ja) 1998-03-11 2004-05-31 富士通株式会社 Ｗｄｍ通信システムにおける中継装置及び同装置の送信レベル制御方法
JP2000101241A (ja) 1998-09-21 2000-04-07 Toshiba Corp 信号パターンの層間接続用ビア、プリント基板および信号パターンの層間接続方法
JP2000216513A (ja) 1999-01-22 2000-08-04 Hitachi Ltd 配線基板及びそれを用いた製造方法
JP2000224102A (ja) * 1999-01-29 2000-08-11 Nec Corp 下り回線送信電力制御システム
JP2002313687A (ja) * 2001-04-16 2002-10-25 Mitsubishi Electric Corp 半導体プロセスパラメータ決定方法、半導体プロセスパラメータ決定システム、及び半導体プロセスパラメータ決定プログラム
US6759257B2 (en) * 2001-11-13 2004-07-06 Fujitsu Limited Structure and method for embedding capacitors in z-connected multi-chip modules
JP4101573B2 (ja) * 2002-07-17 2008-06-18 富士通株式会社 光伝送装置
CN1695408A (zh) * 2003-01-31 2005-11-09 富士通株式会社 多层印刷电路板、电子设备、安装方法
US6976233B1 (en) * 2003-02-13 2005-12-13 Hewlett-Packard Development Company, L.P. Signal via impedance verification tool
US7346869B2 (en) * 2004-10-29 2008-03-18 Synopsys, Inc. Power network analyzer for an integrated circuit design
CN1916915A (zh) * 2005-08-19 2007-02-21 鸿富锦精密工业（深圳）有限公司 改良过孔阻抗的方法
JP2007286691A (ja) * 2006-04-12 2007-11-01 Toshiba Corp 集積回路設計装置
US7519929B2 (en) * 2006-06-23 2009-04-14 Sun Microsystems, Inc. Method and computer program product for interlayer connection of arbitrarily complex shapes under asymmetric via enclosure rules
JP2008009776A (ja) * 2006-06-29 2008-01-17 Matsushita Electric Ind Co Ltd 半導体集積回路の設計方法、設計装置、半導体集積回路システム、半導体集積回路実装基板、パッケージ、半導体集積回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09325983A (ja) * 1996-06-06 1997-12-16 Nippon Telegr & Teleph Corp <Ntt> 最適解計算方法
JP2002334956A (ja) * 2001-05-09 2002-11-22 Fujitsu Ltd 半導体装置の支持体及びその製造方法
JP2004158754A (ja) * 2002-11-08 2004-06-03 Mitsubishi Electric Corp 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012085234A (ja) * 2010-10-14 2012-04-26 Ngk Spark Plug Co Ltd 伝送システム及び伝送装置

Also Published As

Publication number Publication date
US20100251200A1 (en) 2010-09-30
US8429594B2 (en) 2013-04-23
JPWO2009066379A1 (ja) 2011-03-31
JP5018893B2 (ja) 2012-09-05

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