WO2009054201A1 - 高周波基板および、これを用いた高周波モジュール - Google Patents

高周波基板および、これを用いた高周波モジュール Download PDF

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Publication number
WO2009054201A1
WO2009054201A1 PCT/JP2008/066347 JP2008066347W WO2009054201A1 WO 2009054201 A1 WO2009054201 A1 WO 2009054201A1 JP 2008066347 W JP2008066347 W JP 2008066347W WO 2009054201 A1 WO2009054201 A1 WO 2009054201A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
high frequency
wiring layer
ground pattern
signal line
Prior art date
Application number
PCT/JP2008/066347
Other languages
English (en)
French (fr)
Inventor
Risato Ohhira
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to US12/739,847 priority Critical patent/US20100254094A1/en
Priority to JP2009538003A priority patent/JP5397225B2/ja
Publication of WO2009054201A1 publication Critical patent/WO2009054201A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00—Auxiliary devices
    • H01P1/04—Fixed joints
    • H01P1/047—Strip line joints
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Waveguide Connection Structure (AREA)
  • Waveguides (AREA)

Abstract

　本発明の高周波基板は、第１のコプレーナ線路と、該第１のコプレーナ線路とは異なる層に形成された第２のコプレーナ線路とを有し、第１のコプレーナ線路と第２のコプレーナ線路とが各々の線路端にて接続された基板である。第１のコプレーナ線路は、第１の信号線路10と、該第１の信号線路と同じ配線層に形成された第１の面状グランドパタン30ａを備える。さらに、第２のコプレーナ線路は、第１の信号線路とは異なる配線層に形成された第２の信号線路11、該第２の信号線路と同じ配線層に形成された第２の面状グランドパタン32、および第１のコプレーナ線路と同じ配線層に形成された第１のグランドパタン30bを備える。そして、第１の面状グランドパタン30aの端部と第１のグランドパタン30bの端部が接続され一体化している。このような高周波基板において、第１の信号線路と第２の信号線路の端部どうしの接続部付近から第２のコプレーナ線路の延在方向にかけて、第２の面状グランドパタン32が、第１の面状グランドパタン30ａの端部での接続部から分離されている。
PCT/JP2008/066347 2007-10-25 2008-09-10 高周波基板および、これを用いた高周波モジュール WO2009054201A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/739,847 US20100254094A1 (en) 2007-10-25 2008-09-10 High-Frequency Wiring Board and High-Frequency Module That Uses the High-Frequency Wiring Board
JP2009538003A JP5397225B2 (ja) 2007-10-25 2008-09-10 高周波基板および、これを用いた高周波モジュール

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-277686 2007-10-25
JP2007277686 2007-10-25

Publications (1)

Publication Number Publication Date
WO2009054201A1 true WO2009054201A1 (ja) 2009-04-30

Family

ID=40579308

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/066347 WO2009054201A1 (ja) 2007-10-25 2008-09-10 高周波基板および、これを用いた高周波モジュール

Country Status (3)

Country Link
US (1) US20100254094A1 (ja)
JP (1) JP5397225B2 (ja)
WO (1) WO2009054201A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014130974A (ja) * 2012-12-29 2014-07-10 Kyocer Slc Technologies Corp 配線基板
JP2016184768A (ja) * 2016-07-25 2016-10-20 京セラ株式会社 配線基板の製造方法
EP2441118A4 (en) * 2009-06-11 2017-07-26 Honeywell International Inc. Method for achieving intrinsic safety compliance in wireless devices using isolated overlapping grounds and related apparatus
JP2020088255A (ja) * 2018-11-29 2020-06-04 京セラ株式会社 配線基板
JP2021502769A (ja) * 2017-11-10 2021-01-28 レイセオン カンパニー ミリメータ波伝送線アーキテクチャ

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019094600A1 (en) 2017-11-10 2019-05-16 Raytheon Company Additive manufacturing technology (amt) faraday boundaries in radio frequency circuits
US20190150296A1 (en) * 2017-11-10 2019-05-16 Raytheon Company Additive manufacturing technology microwave vertical launch
KR102545915B1 (ko) 2017-11-10 2023-06-22 레이던 컴퍼니 적층 제조 기술(amt) 저 프로파일 라디에이터
US11289814B2 (en) 2017-11-10 2022-03-29 Raytheon Company Spiral antenna and related fabrication techniques
IL308118A (en) 2018-02-28 2023-12-01 Raytheon Co Radio frequency push connections
WO2019168996A1 (en) 2018-02-28 2019-09-06 Raytheon Company Additive manufacturing technology (amt) low profile signal divider
WO2023133750A1 (en) * 2022-01-13 2023-07-20 Commscope Technologies Llc Ultra wideband board-to-board transitions for stripline rf transmisison lines

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000100993A (ja) * 1998-09-24 2000-04-07 Sumitomo Metal Ind Ltd 高周波回路基板
JP2001298306A (ja) * 2000-04-14 2001-10-26 Sumitomo Metal Electronics Devices Inc 高周波伝送線路基板、及び高周波パッケージ
JP2002185201A (ja) * 2000-12-08 2002-06-28 Kyocera Corp 高周波用配線基板
JP2002325004A (ja) * 2001-04-26 2002-11-08 Kyocera Corp 高周波用配線基板

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5057798A (en) * 1990-06-22 1991-10-15 Hughes Aircraft Company Space-saving two-sided microwave circuitry for hybrid circuits
SE9502326D0 (sv) * 1995-06-27 1995-06-27 Sivers Ima Ab Mikrovågskrets, sådan krets av kapslat utförande, samt användning av mikrovågskretsen i ett kretsarrangemang
JP2004064174A (ja) * 2002-07-25 2004-02-26 Kyocera Corp 高周波用配線基板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000100993A (ja) * 1998-09-24 2000-04-07 Sumitomo Metal Ind Ltd 高周波回路基板
JP2001298306A (ja) * 2000-04-14 2001-10-26 Sumitomo Metal Electronics Devices Inc 高周波伝送線路基板、及び高周波パッケージ
JP2002185201A (ja) * 2000-12-08 2002-06-28 Kyocera Corp 高周波用配線基板
JP2002325004A (ja) * 2001-04-26 2002-11-08 Kyocera Corp 高周波用配線基板

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2441118A4 (en) * 2009-06-11 2017-07-26 Honeywell International Inc. Method for achieving intrinsic safety compliance in wireless devices using isolated overlapping grounds and related apparatus
JP2014130974A (ja) * 2012-12-29 2014-07-10 Kyocer Slc Technologies Corp 配線基板
JP2016184768A (ja) * 2016-07-25 2016-10-20 京セラ株式会社 配線基板の製造方法
JP2021502769A (ja) * 2017-11-10 2021-01-28 レイセオン カンパニー ミリメータ波伝送線アーキテクチャ
JP7013579B2 (ja) 2017-11-10 2022-02-15 レイセオン カンパニー ミリメータ波伝送線アーキテクチャ
JP2020088255A (ja) * 2018-11-29 2020-06-04 京セラ株式会社 配線基板

Also Published As

Publication number Publication date
JP5397225B2 (ja) 2014-01-22
JPWO2009054201A1 (ja) 2011-03-03
US20100254094A1 (en) 2010-10-07

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