WO2009037762A1 - カレントミラー回路 - Google Patents

カレントミラー回路 Download PDF

Info

Publication number
WO2009037762A1
WO2009037762A1 PCT/JP2007/068236 JP2007068236W WO2009037762A1 WO 2009037762 A1 WO2009037762 A1 WO 2009037762A1 JP 2007068236 W JP2007068236 W JP 2007068236W WO 2009037762 A1 WO2009037762 A1 WO 2009037762A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
gate
current mirror
mirror circuit
cascode
Prior art date
Application number
PCT/JP2007/068236
Other languages
English (en)
French (fr)
Inventor
Masahiro Kudo
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2009532995A priority Critical patent/JP5035350B2/ja
Priority to PCT/JP2007/068236 priority patent/WO2009037762A1/ja
Publication of WO2009037762A1 publication Critical patent/WO2009037762A1/ja
Priority to US12/691,836 priority patent/US7932712B2/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—DC amplifiers in which all stages are DC-coupled
    • H03F3/343—DC amplifiers in which all stages are DC-coupled with semiconductor devices only
    • H03F3/345—DC amplifiers in which all stages are DC-coupled with semiconductor devices only with field-effect devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/453—Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/91—Indexing scheme relating to amplifiers the amplifier has a current mode topology

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

　１つの電流源による基準電流を複製して出力する。 　トランジスタ（Ｍ１４）は、ゲートがトランジスタ（Ｍ１１）のゲートと接続されている。トランジスタ（Ｍ１３）は、トランジスタ（Ｍ１１）にカスコード接続されている。トランジスタ（Ｍ１５）は、ゲートがトランジスタ（Ｍ１３）のゲートと接続され、トランジスタ（Ｍ１４）にカスコード接続されている。トランジス（Ｍ１２）は、トランジスタ（Ｍ１３）と並列に接続され、ゲートが電流源（Ｉ１１）、トランジスタ（Ｍ１３）のドレイン、およびトランジスタ（Ｍ１１）のゲートに接続されている。バイアス電圧生成回路（１１）は、トランジスタ（Ｍ１１）とトランジスタ（Ｍ１２）のゲート電圧に基づいて、トランジスタ（Ｍ１３）とトランジスタ（Ｍ１５）とのバイアス電圧を生成する。
PCT/JP2007/068236 2007-09-20 2007-09-20 カレントミラー回路 WO2009037762A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009532995A JP5035350B2 (ja) 2007-09-20 2007-09-20 カレントミラー回路
PCT/JP2007/068236 WO2009037762A1 (ja) 2007-09-20 2007-09-20 カレントミラー回路
US12/691,836 US7932712B2 (en) 2007-09-20 2010-01-22 Current-mirror circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/068236 WO2009037762A1 (ja) 2007-09-20 2007-09-20 カレントミラー回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/691,836 Continuation US7932712B2 (en) 2007-09-20 2010-01-22 Current-mirror circuit

Publications (1)

Publication Number Publication Date
WO2009037762A1 true WO2009037762A1 (ja) 2009-03-26

Family

ID=40467593

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/068236 WO2009037762A1 (ja) 2007-09-20 2007-09-20 カレントミラー回路

Country Status (3)

Country Link
US (1) US7932712B2 (ja)
JP (1) JP5035350B2 (ja)
WO (1) WO2009037762A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012004627A (ja) * 2010-06-14 2012-01-05 Toshiba Corp カレントミラー回路
JP2013070283A (ja) * 2011-09-22 2013-04-18 Fujitsu Ltd デジタル−アナログ変換器及び半導体集積回路
US8471631B2 (en) 2010-04-27 2013-06-25 Murata Manufacturing Co., Ltd. Bias circuit, power amplifier, and current mirror circuit
CN106383546A (zh) * 2016-08-31 2017-02-08 厦门优迅高速芯片有限公司 一种用于dac输出端的高线性度电流镜电路

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9715245B2 (en) * 2015-01-20 2017-07-25 Taiwan Semiconductor Manufacturing Company Limited Circuit for generating an output voltage and method for setting an output voltage of a low dropout regulator
JP7284593B2 (ja) * 2018-03-22 2023-05-31 株式会社東芝 電流駆動回路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0888521A (ja) * 1993-09-10 1996-04-02 Motorola Inc 自己バイアスされたカスコード電流ミラー回路
JPH09139638A (ja) * 1995-09-12 1997-05-27 Toshiba Corp カレントミラー回路
JP2007142698A (ja) * 2005-11-17 2007-06-07 Toshiba Corp スタートアップ回路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4550284A (en) * 1984-05-16 1985-10-29 At&T Bell Laboratories MOS Cascode current mirror
KR100241202B1 (ko) * 1995-09-12 2000-02-01 니시무로 타이죠 전류미러회로
US5966005A (en) * 1997-12-18 1999-10-12 Asahi Corporation Low voltage self cascode current mirror
JP3510100B2 (ja) * 1998-02-18 2004-03-22 富士通株式会社 カレントミラー回路および該カレントミラー回路を有する半導体集積回路
JP4118562B2 (ja) * 1999-07-23 2008-07-16 富士通株式会社 低電圧カレントミラー回路
US6211659B1 (en) * 2000-03-14 2001-04-03 Intel Corporation Cascode circuits in dual-Vt, BICMOS and DTMOS technologies
US6680605B2 (en) * 2002-05-06 2004-01-20 Exar Corporation Single-seed wide-swing current mirror

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0888521A (ja) * 1993-09-10 1996-04-02 Motorola Inc 自己バイアスされたカスコード電流ミラー回路
JPH09139638A (ja) * 1995-09-12 1997-05-27 Toshiba Corp カレントミラー回路
JP2007142698A (ja) * 2005-11-17 2007-06-07 Toshiba Corp スタートアップ回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium", vol. 2, 7 August 2002, article MINCH, B.A.: "A low-voltage MOS cascode current mirror for all current levels", pages: II-53 - II-56, XP003027165 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8471631B2 (en) 2010-04-27 2013-06-25 Murata Manufacturing Co., Ltd. Bias circuit, power amplifier, and current mirror circuit
JP2012004627A (ja) * 2010-06-14 2012-01-05 Toshiba Corp カレントミラー回路
JP2013070283A (ja) * 2011-09-22 2013-04-18 Fujitsu Ltd デジタル−アナログ変換器及び半導体集積回路
CN106383546A (zh) * 2016-08-31 2017-02-08 厦门优迅高速芯片有限公司 一种用于dac输出端的高线性度电流镜电路

Also Published As

Publication number Publication date
US7932712B2 (en) 2011-04-26
JP5035350B2 (ja) 2012-09-26
US20100117619A1 (en) 2010-05-13
JPWO2009037762A1 (ja) 2011-01-06

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