WO2009033342A1 - Procédé et système de synchronisation d'horloge pour l'architecture de calcul de télécommunication avancée - Google Patents

Procédé et système de synchronisation d'horloge pour l'architecture de calcul de télécommunication avancée Download PDF

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Publication number
WO2009033342A1
WO2009033342A1 PCT/CN2007/003767 CN2007003767W WO2009033342A1 WO 2009033342 A1 WO2009033342 A1 WO 2009033342A1 CN 2007003767 W CN2007003767 W CN 2007003767W WO 2009033342 A1 WO2009033342 A1 WO 2009033342A1
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WIPO (PCT)
Prior art keywords
clock
module
node
board
node board
Prior art date
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PCT/CN2007/003767
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English (en)
French (fr)
Inventor
Guohua Sun
Yun Wang
Jun Tian
Original Assignee
Zte Corporation
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Publication date
Application filed by Zte Corporation filed Critical Zte Corporation
Priority to BRPI0722011A priority Critical patent/BRPI0722011B1/pt
Publication of WO2009033342A1 publication Critical patent/WO2009033342A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

Definitions

  • the present invention relates to the field of ATCA (Advanced Telecommunications Computer System) platforms, and more particularly to a clock synchronization system and method for the system.
  • ATCA Advanced Telecommunications Computer System
  • the synchronous clock interface uses a bus structure of MLVDS (Multi-Node Low Voltage Differential Signaling) to ensure reliable transmission of the clock.
  • ATCA supports three pairs of clock buses: CLK1A/B, CLK2A/B, CLK3A/B, the specifications define CLK1A/B, CLK2A/B are 8K, 19.44M, CLK3A/B is a custom clock bus, each clock There is a set of backup clocks, a total of six pairs of differential lines, all located on the Zone2 socket. The main/standby two sets of clock sources each drive one bus.
  • the ATCA specification stipulates that for the receiving board, the distributed processing mode is adopted, and the receiving board monitors the validity of the clock bus A and B by itself. And decide which bus to take. If the currently selected clock fails or the indicator becomes worse, another clock will be selected according to the switching strategy. The primary and backup clocks are not strictly distinguished.
  • the ATCA specification does not specify fixed slots for the driver and receiver. It is completely negotiated by each node board through the IPMC (Intelligent Platform Management Controller) and the chassis management module to determine which node board drives which set of clocks to prevent the same clock. The point driver creates a conflict.
  • Solution 1 The clock function of the ATCA system is integrated into the switch board, and the AMC (Advanced Sandwich Subcard) subcard mode is adopted, or a non-standard sub-card is adopted.
  • the card realizes the synchronous clock function, and the switch board acts as its carrier motherboard and becomes the driving source of the ATCA clock bus.
  • the switch board loses Out to the backplane clock bus A, another switch board outputs to the backplane clock bus B, and the two switch boards have a cascaded clock cable.
  • the clock board does not have an i-book relationship, and forms a double-star plane topology as the switch board.
  • the system synchronous clock can also output multiple clock signals on the card panel of Zone3 for clock test or synchronous cascade chassis.
  • the two buses A and B of each clock on the ATCA backplane correspond to the output of one clock board, and the switching of the clock reference on the node board is judged by each node board.
  • the AMC daughter card with the line interface can be inserted on the node board to extract the 8K line synchronization clock, which is divided into two channels and output on the rear card of the Zone 3 zone of the node board. Connect to the Zone3 clock rear card of the two switch boards.
  • the Zone3 rear card of the switchboard supports two clock line inputs, such as 2Mbps, 2Mbits, and 5MHz.
  • a certain frame is set as the root node in the system.
  • the switch board on which the frame is located configures the clock daughter card, accepts the line extraction clock or clock reference input such as 2Mbps and 2Mbits, and outputs the system synchronous clock through the line.
  • the cable is distributed to the rear card input end of the switch board of the other frame, and then distributed by the switch board to each node board in the frame through the clock bus, and the switch board of the remaining frame can be inserted without the clock daughter card.
  • Solution 2 Set up the clock node board and the clock post-insertion module separately to complete all the clock functions described in the first scheme. As shown in Figure 2, one clock node board simultaneously outputs the clock to the backplane clock bus A and B, and the two clock node boards have a cascaded clock cable. The two clock node boards are located in adjacent slots and use the UPDATE channel defined by ATCA for primary and backup.
  • scheme 2 can use the UPDATE channel of the ATCA to implement the active and standby clock node boards, which can prevent a single point of failure of the clock node board, but must use two adjacent slots, which is obviously a waste of valuable Slot resources reduce the processing power of the system.
  • the cascaded clock outputted by the rear plug-in module of the two clock node boards it is difficult to achieve a cable output, and it is difficult to achieve clock synchronization of the cascaded chassis.
  • the disadvantages of the first solution are also obvious. See Figure 1.
  • the cascaded clock cable has two paths.
  • the switch board uses the same clock reference and affects the number of external C3s that the switch board outputs to the rear-plug module. For both scenarios, the same type of external clock reference must provide at least two paths to evenly distribute to two clock node boards, wasting the operator's valuable reference clock resources. Summary of the invention
  • the technical problem to be solved by the present invention is to provide a clock synchronization system and method for an advanced telecommunication computer system, so that only one way is required for external clock reference access, and a single ATCA chassis cascade cable is provided on the clock rear card module. Or fiber optic outlets.
  • a clock synchronization system of an advanced telecommunication computer system the system is located in a chassis, the chassis includes a node board and a backboard, and the system includes: a clock rear insertion module, a middle layer small backplane module, and a clock daughter card;
  • the clock post-plug module is configured to access an external clock reference and transmit the same to the clock daughter card through the middle layer small backplane module;
  • the clock subcard is located on the node board, and is configured to receive and process an external clock reference, select a reference clock, process the clock required by the system, and send the clock to the clock bus on the backplane.
  • the middle layer small backplane module is located in the Zone 3 area of the node board, and is used to interconnect the clock reference access interfaces of the clock daughter cards on each slot node board.
  • the clock daughter card is further configured to output a cascade synchronization clock, and send the clock post-plug module through the small layer backplane module of the intermediate layer;
  • the clock post-insertion module is further configured to receive a cascaded synchronous clock signal from the clock daughter card for processing, and provide a cascaded clock output interface and a cascaded clock access interface;
  • the middle layer small backplane module is further configured to interconnect the cascade clock output interfaces of the clock daughter cards on each slot node board.
  • the front and back sides of the middle layer small backplane module have two rows of sockets: one row is a first Zone3 socket, and is connected to a clock reference access interface of the clock daughter card and the clock rear insertion module.
  • the clock reference output interface the other row is a second Zone3 socket for connecting the cascaded clock output interface of the clock daughter card and the cascade clock access interface of the clock post-plug module.
  • all of the first Zone3 sockets on the intermediate layer small backplane module are interconnected, and all of the second Zone3 sockets are interconnected.
  • the clock synchronization system further includes a chassis management module, configured to configure an external clock reference, provide the clock daughter card, and report the current reference selection situation and the clock synchronization status to the network management system.
  • the clock synchronization system further includes an intelligent platform management controller sub-card module, the module is located on the node board, and is used to implement a board management function, where the board management function includes measuring and monitoring the status of the node board. Log the exception event log and report alarm or status information to the chassis management module when an exception occurs.
  • the clock daughter card is independently located on the node board in an advanced sandwich subcard manner, and the clock rear insertion module is later located in the rear of the chassis.
  • the clock synchronization method of the advanced telecommunication computer system comprises the following steps: a: inserting two clock daughter cards into two node boards respectively, and connecting the clock rear card to each node board through the middle layer small backplane module ;
  • the chassis is powered on, the chassis management module is started, and the physical slot number of the clock bus driver is obtained, and the clock bus driver end is a node board with a clock daughter card inserted therein;
  • the chassis management module sets the two node boards to use the same clock reference
  • the clock post-plug module sends the external clock reference to the two node boards through the middle layer small backplane module, one of the node boards processes the external clock reference, selects one reference clock, and processes the clock to the frequency required by the system. , send it to the clock bus on the backplane.
  • the method for obtaining the physical slot number of the clock bus driver is: the chassis management module communicates with the intelligent platform management controller daughter card module on each node board to obtain the clock daughter card on the node board.
  • the physical slot number of the clock bus driver is obtained according to the hardware address of the node board.
  • the node board with the best health condition of the two node boards processes the external clock reference, and selects one reference clock according to the priority.
  • the method further includes:
  • the chassis management module monitors the health status of the two node boards in real time, and selects the node board that outputs the clock signal according to the health status or the mandatory selection command of the network management, which is controlled by the hardware of the node board.
  • the clock output switching of the two node boards and the time point of switching.
  • the method further includes:
  • the node board obtains a cascade clock signal and sends it to the clock post-plug module; g: the cascade chassis selects an appropriate cascade according to the monitoring of the cascade input clock by the node board of the access cascade clock Come over the clock.
  • step d further includes: the other node board of the two node boards only processes the input reference, and does not allow output to the back board clock bus and the post-plug module.
  • the slot of each node board is any slot.
  • the cascaded synchronous clock output has only one cable, which does not require interaction information between the various chassis, which reduces the complexity of the management software to select the clock reference strategy and improves the reliability of the system.
  • FIG. 2 is a schematic diagram of a method of the prior art scheme 2
  • FIG. 3 is a schematic view showing the overall structure of a clock synchronization system of the present invention.
  • FIG. 4 is a schematic diagram of functions of a chassis management module according to the present invention.
  • FIG. 5 is a hardware schematic diagram of a chassis management module of the present invention.
  • FIG. 6 is a schematic structural diagram of an IPMC daughter card
  • FIG. 7 is a schematic diagram of the clock daughter card
  • Figure 8 is a schematic diagram of a clock post-plug module
  • Figure 9 is a schematic view of the intermediate layer small back plate of the present invention. Preferred embodiment of the invention
  • the clock synchronization system of the present invention comprises a chassis management module and an IPMC (Intelligent Platform Management Controller) daughter card module; and further includes: a clock daughter card, a clock rear insertion module, and an intermediate layer small backplane module.
  • IPMC Intelligent Platform Management Controller
  • each module separately, in which the IPMC daughter card is independently located on the node board of each ATCA, implements the board management function specified in the PICMG3.0 specification, measures and monitors the status of the node board, records the abnormal event log, and is abnormal. Alarm or status information is reported to the chassis management module via the IPMB (Intelligent Platform Management Bus) interface.
  • the NMS can query the external clock reference through the chassis management module, and the chassis management module reports the current reference selection status to the NMS, and whether the clock is synchronized.
  • the clock daughter card is independently located on the node board of each ATCA in the AMC mode or in the form of a non-standard daughter card. It is used to meet the requirements of the clock synchronization network, and receives and processes the external synchronous clock signal, including the clock reference extraction and receiving circuit. Frequency circuit, digital phase detection circuit, clock regeneration circuit, clock quality cycle monitoring circuit.
  • the clock post-plug module is located in the rear of the ATCA chassis in the form of an RTM (rear card module). Unlike other dual-star planes, only one post-card module is used to complete external clock reference access, impedance matching, and cascaded clocks. Level shifting, driving, distributing, monitoring, and cascading clocks are output in cable or fiber optics.
  • the middle layer small backplane device is located in the Zone 3 area of the board and can be connected to the Zone3 area of all slots. According to the specific conditions of the product, it can also be simplified as a Zone3 area that connects two adjacent slots separately, achieving a single external input clock reference.
  • the interconnections are distributed among multiple ATCA node boards, the line extraction clocks, and the output of the cascaded clocks of the respective slots are interconnected.
  • the implementation method of the above clock synchronization system includes the following steps:
  • Step 1 Insert two clock daughter cards into the node boards of two random slots, and connect a clock rear insertion module to a slot through the middle layer small backplane module.
  • Step 2 After the chassis is powered on, after the chassis management module starts normally, the IPMB interface communicates with the IPMC daughter card on each node board to obtain the clock subcard in the node board.
  • the hardware address is obtained by the physical slot number of the clock bus driver, and is sent to the network management system in a graphical manner, and the synchronous clock slot and state are displayed in real time in a graphical manner;
  • Step 3 According to the physical slot number of the bus driver obtained in the second step, the chassis management module queries the health of the two node boards, and sets the two node boards to use the same one through the IPMB (Intelligent Platform Management Bus) interface.
  • the clock reference, the clock post-plug module sends the external clock reference to the two node boards through the middle layer small backplane module, and then the chassis management module communicates with the healthier node board to output the processed clock to the ATCA.
  • the output cascades the synchronous clock to the clock to insert the module, and the other node board only processes the input reference clock, and does not allow output to the backplane clock bus and the post-plug module;
  • Step 4 The chassis management module monitors the health of the two node boards in real time. According to the health situation, or the forced selection command of the network management tube, the node board that outputs the clock signal is selected, and the clock output of the two node boards is controlled by the hardware of the node board. Switching and switching time points;
  • Step 5 Since the output of the cascaded clock switching point is properly selected, it does not affect the clock synchronization of the cascaded chassis.
  • the cascaded chassis does not require additional processing. It only needs to monitor the cascaded input clock according to the node board that accesses the cascaded clock. In the case, independently select the appropriate cascading clock.
  • FIG. 3 is a schematic diagram of an overall structure of a clock synchronization system according to the present invention, wherein the hardware module part includes:
  • A chassis management module
  • IPMC Intelligent Platform Management Controller
  • the two modules are the standard modules defined by the PICMG 3.0 specification, including the IPMI protocol for the communication between the two modules, and the boards that implement the management, monitoring, and network management commands of the node board. Management function.
  • the three modules are the core of the invention.
  • the clock synchronization implementation method is as follows: First, the external clock reference from the operator, or the system node board extracts the external interface line clock, and accesses the clock through the cable.
  • the rear card is connected to the small backplane of the middle layer by the rear card, and all the Zone3 area sockets 1 (the first Zone3 socket) are interconnected on the small backplane of the middle layer, and the socket 2 (the second Zone3 socket) provides the cascaded clock output mutual
  • the clock reference can be input to the node board, and the cascaded clock is output to the rear card.
  • the Zone3 plug and the socket of the gusset board and the rear card are connected through the small backplane of the middle layer, the plug 1 is connected to the socket 1, and the plug 2 is connected to the socket 2.
  • the clock reference is connected to the clock daughter card of the node board through the plug 1, and the reference shield is monitored.
  • a reference clock is selected for frequency division and phase discrimination, and the clock of the OCXO output on the clock daughter card is matched with the frequency and phase of the reference clock.
  • the clock is controlled and distributed to the backboard clock bus A/B, and other frequency clocks required by the system are generated by frequency conversion, converted to an appropriate level, and output to The card is inserted after the clock to ensure that the entire system has only one clock driver at any time.
  • FIGS. 4 and Figure 5 are the functional diagrams and hardware schematic diagrams of the chassis management module.
  • the hardware core is the logic device to implement the I 2 C interface.
  • the module software implements various network management interfaces and communicates with the IPMC for monitoring and controlling the chassis. Node boards and other functional modules that report system anomalies and perform basic recovery operations.
  • the electronic switch controls the opening/closing of the connection port between the node board and the back board;
  • the IPMC daughter card software and hardware mainly implement the following functions:
  • Non-volatile storage function with sensor data record and other key data. It is stored on the daughter card by measuring the voltage uploaded by the sensor provided by the carrier board of the daughter card according to the sensor data record (SDR) format required by the ATCA specification. FLASH or NV-SRAM;
  • the indicator light and the wrench switch signal are connected to the input and output ports of the EPLD chip.
  • the internal registers are 8-bit registers and corresponding register numbers.
  • the single-chip W83910F is directly connected to the data bus. EPLD writes and reads offline status indicator, hot plug indicator, alarm light status, front panel wrench switch status;
  • the structure principle of the clock daughter card is shown in Figure 7.
  • the clock daughter card is used to convert, divide, and monitor the external reference.
  • the microcontroller selects a clock according to the priority and quality of the clock reference, and the OCXO on the daughter card.
  • the (output crystal oscillator) output clock is phase-compared, and the phase difference is converted to an analog voltage by a D/A (digital/analog conversion) device, and the phase of the control OCXO clock is made coincident with the reference clock.
  • the clock output from the OCXO is divided again to generate a synchronous clock of various frequencies required by the system.
  • the clock daughter card can be a standard AMC daughter card or a custom daughter card.
  • the structure of the clock rear insertion module is shown in Figure 7; the structure of the small layer backplane module is shown in Figure 8.
  • the middle layer small backplane module has two rows of sockets on the front and back sides: one row is the Zone3 socket 1, the clock reference access interface for connecting the clock daughter card and the clock reference output interface of the other clock rear insertion module; the other row is Zone 3 socket 2, which is used to connect the cascaded clock output interface of the clock daughter card and the cascade clock access interface of another clock post-plug module; all Zone3 sockets 1 are interconnected, and all Zone 3 sockets 2 are interconnected.
  • the clock rear-plug module is used in conjunction with the small-layer backplane of the middle layer to complete the external reference clock access to each node board that may be inserted into the clock daughter card.
  • the output of the node board is used for the cascade chassis.
  • the synchronized clock is level-converted, outputted to the socket on the rear card panel, or converted to an optical signal by the optical module, so that the cascaded chassis can be connected by cable or fiber, or the cable and fiber can be connected to the cascaded chassis at the same time.

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Description

一种先进电信计算机体系的时钟同歩系统及方法
技 领域
本发明涉及 ATCA (先进电信计算机体系）平台领域， 尤其涉及该体系 的时钟同步系统及方法。
背景技术
现代通讯领域，信息的传输和交换是通过时分复用完成的， 为了获得准 确的频率和定时信号， 都需要依赖时钟同步技术才能正确解复用出有用信 息，使得输出数据码率与输入的数据码率一致， 从而避免数据在传输和交换 过程中因不同步而产生数据的滑动损伤，导致数据误码率增大，通信效率和 质量下降甚至通信中断。 当 ATCA平台应用在电路域时， 同样需要保证整 个机箱， 以及级联机箱的时钟处于同步状态。 PICMG ( PCI工业计算机厂商 组织）制定的 3.0规范规定了同步时钟的电气特性、 分发方式及智能管理方 式。 同步时钟接口釆用 MLVDS (多节点低电压差分信号） 的总线结构， 确 保时钟的可靠传输。 ATCA 支持三对时钟总线： CLK1A/B、 CLK2A/B , CLK3A/B, 规范分别定义 CLK1A/B、 CLK2A/B为 8K、 19.44M, CLK3A/B 为自定义的时钟总线， 每一种时钟都有一组备份时钟， 共六对差分线， 全部 位于 Zone2插座上。 主 /备两套时钟源各驱动一套总线， 对于两套时钟的选 择， ATCA规范规定， 对于接收单板而言， 采用分布式处理方式， 接收单板 自己监控时钟总线 A、 B的有效性， 并自己决定取哪套总线， 如果当前选择 的时钟故障或指标变差，会根据切换策略选择另外一路时钟， 主备时钟没有 严格区分。 另外 ATCA规范并未规定驱动端和接收端固定槽位， 完全由各 个节点板通过 IPMC (智能平台管理控制器）和机箱管理模块协商， 确定哪 个节点板驱动哪套时钟， 以防止同一个时钟多点驱动产生沖突。
为了实现 ATCA系统的时钟同步， 现有技术中有以下两个方案： 方案一： 将 ATCA系统的时钟功能合入交换板， 采用 AMC (先进夹层子 卡)子卡方式， 或者采用非标准的子卡来实现同步时钟功能， 交换板作为其 承载母板， 成为 ATCA时钟总线的驱动源， 如附图 1所示， 一块交换板输 出到背板时钟总线 A, 另外一块交换板输出到背板时钟总线 B， 两个交换板 后插卡各出一个级联时钟电缆。 与传统产品不同的是， 该时钟板不存在 i备 关系， 与交换板一样组成一个双星平面的拓朴结构。 系统同步时钟除输出到 背板总线八、 B外， 还可以在 Zone3后插卡面板输出多路时钟信号， 供时钟 测试用或者同步级联机箱。 ATCA背板上每种时钟的两条总线 A和 B，分别 对应一块时钟板的输出， 节点板上时钟基准的切换由各节点板自己判断。 当 ATCA平台使用在电路域场合时，节点板上可以插带线路接口的 AMC子卡 , 来提取 8K线路同步时钟， 分为两路在节点板 Zone 3区的后插卡上输出，通 过线缆分别接到两块交换单板的 Zone3时钟后插卡上。交换板的 Zone3后插 卡除支持 2路线路时钟输入外， 还支持 2Mbps、 2Mbits、 5MHz等常规时钟 基准输入。 当 ATCA平台需要多框级联时， 系统内设定某框为根节点， 此 框所在交换板配置时钟子卡，接受线路提取时钟或 2Mbps、 2Mbits等时钟基 准输入，输出的系统同步时钟通过线缆分发到其他框的交换板的后插卡输入 端，.再由交换板通过时钟总线分发到框内各节点板， 其余框的交换板可以不 插时钟子卡。
方案二：单独设立时钟节点板及时钟后插模块来完成方案一所述的所有 时钟方面的功能。如附图 2所示， 一块时钟节点板同时输出时钟到背板时钟 总线 A、 B， 两个时钟节点板后插卡各出一个级联时钟电缆。 两个时钟节点 板位于相邻槽位， 使用 ATCA定义的 UPDATE通道来主备用。
结合 ATCA架构特点，可以看出，方案二可以利用 ATCA的 UPDATE通 道实现主备时钟节点板， 可以防止出现时钟节点板的单点故障，但是必须使 用相邻两个槽位， 显然浪费了宝贵的槽位资源， 降低了系统的处理能力。 而 且对于两个时钟节点板的后插模块输出的級联时钟， 难以做到一个电缆输 出， 不易实现级联机箱的时钟同步。 方案一的缺点也艮明显， 见附图 1， 级 联的时钟电缆有两路， 必须与对端 ATCA机箱交换板的后插卡点对点连接， 增加了板上倒换策略复杂性， 难以保证两块交换板使用同一路的时钟基准， 而且影响了交换板输出到后插模块的对外接 C3数量。对于这两种方案， 同一 种类的外部时钟基准必须至少提供两路来平均分配到两块时钟节点板，浪费 运营商宝贵的基准时钟资源。 发明内容
本发明所要解决的技术问题是提供一种先进电信计算机体系的时钟同 步系统及方法，使得外部时钟基准接入时只需一路， 同时在时钟后插卡模块 上提供唯一的 ATCA机箱级联的电缆或光纤出口。
为解决上述技术问题， 本发明是通过以下技术方案实现的：
一种先进电信计算机体系的时钟同步系统， 该系统位于机箱内， 所述机 箱包括节点板和背板， 所述系统包括： 时钟后插模块、 中间层小背板模块和 时钟子卡；
所述时钟后插模块用于接入外部时钟基准，将其通过所述中间层小背板 模块传送给所述时钟子卡；
所述时钟子卡位于所述节点板上， 用于接收、 处理外部时钟基准， 选择 一路基准时钟， 处理成系统需要的时钟后，将其发送到所述背板上的时钟总 线；
所述中间层小背板模块位于所述节点板的 Zone3区，用于将各槽位节点 板上时钟子卡的时钟基准接入接口互连。
进一步地， 所述时钟子卡还用于输出级联同步时钟，通过中间层小背板 模块发送给时钟后插模块；
所述时钟后插模块还用于接收来自时钟子卡的级联同步时钟信号进行 处理， 并提供级联时钟输出接口和级联时钟接入接口；
所述中间层小背板模块还用于将各槽位节点板上时钟子卡的级联时钟 输出接口互连。
进一步地， 所述中间层小背板模块的正反面均有两排插座： 一排为第一 Zone3插座， 用于连接所述时钟子卡的时钟基准接入接口和所述时钟后插模 块的时钟基准输出接口； 另一排为第二 Zone3插座， 用于连接所述时钟子卡 的级联时钟输出接口和所述时钟后插模块的级联时钟接入接口。 进一步地, 所述中间层小背板模块上的所有第一 Zone3插座互连， 所有 第二 Zone3插座互连。 进一步地， 所述时钟同步系统还包括机箱管理模块， 该模块用于配置外 部时钟基准，提供给时钟子卡， 并向网管报告当前基准选择情况以及时钟同 步情况。
进一步地， 所述时钟同步系统还包括智能平台管理控制器子卡模块， 该 模块位于所述节点板上， 用于实现单板管理功能， 所述单板管理功能包括测 量、监控节点板状态， 记录异常事件日志， 并在异常时向所述机箱管理模块 上报告警或者状态信息。
进一步地， 所述时钟子卡以先进夹层子卡方式独立位于节点板上， 所述 时钟后插模块以后插卡模块形式位于机箱的后部。
本发明提供的先进电信计算机体系的时钟同步方法， 包括以下步骤： a: 将两个时钟子卡分别插入两个节点板， 并将时钟后插卡通过中间层 小背板模块与各节点板相连；
b: 机箱上电， 机箱管理模块启动， 获取时钟总线驱动端的物理槽位号， 该时钟总线驱动端为插有时钟子卡的节点板；
c: 根据所述物理槽位号， 机箱管理模块设置所述两个节点板使用同一 个时钟基准；
d: 时钟后插模块将外部时钟基准通过中间层小背板模块发送给上述两 个节点板， 其中一个节点板处理所述外部时钟基准， 选择一路基准时钟， 处 理成系统需要的频率的时钟后， 将其发送到所述背板上的时钟总线。
进一步地，所述步骤 b中，获取时钟总线驱动端的物理槽位号的方法为： 机箱管理模块与各'节点板上的智能平台管理控制器子卡模块通讯，获取节点 板上的时钟子卡在位情况，根据节点板的硬件地址获取时钟总线驱动端的物 理槽位号。
进一步地， 所述步骤 d中， 所述两个节点板中健康情况最好的节点板处 理所述外部时钟基准， 并按照优先级选择一路基准时钟。
进一步地， 所述步骤 d之后还包括：
e: 机箱管理模块实时监控所述两个节点板的健康状况， 根据健康状况 或网管的强制选择命令，选择输出时钟信号的节点板， 由节点板的硬件控制 两个节点板的时钟输出切换以及切换的时间点。
进一步地， 所述步骤 d后还包括：
fl 所述节点板获得级联时钟信号， 将其发送给所述时钟后插模块； g: 级联机箱根据接入级联时钟的节点板对级联输入时钟的监控情况， 选择合适的级联过来的时钟。
进一步地， 所述步骤 d还包括： 所述两个节点板的另一节点板只对输入 基准进行处理， 不允许输出到背板时钟总线和后插模块。
进一步地， 所述方法中各节点板的槽位为任意槽位。
本发明具有以下有益效果：
( 1 )最低要求只需要运营商提供一路时钟基准即可， 节省运营商的时 钟资源， 降低了成本。
( 2 ) 时钟后插卡只需要一块， 可以位于任意槽位， 比如插在不需要功 能后插卡的槽位，节省下来的后插槽位可以用于其他需要外接或者外出端口 的节点板。
( 3 )级联的同步时钟输出只有一个线缆， 不需要各个机箱之间交互信 息， 降低了管理软件选择时钟基准策略的复杂性， 提高了系统的可靠性。 附图概述
图 1为现有技术方案一的方法示意图；
图 2为现有技术方案二的方法示意图；
图 3为本发明的时钟同步系统整体结构示意图；
图 4为本发明的机箱管理模块功能示意图；
图 5为本发明的机箱管理模块的硬件原理图；
图 6为 IPMC子卡结构示意图；
图 7为时钟子卡原理图；
图 8为时钟后插模块示意图； 图 9为本发明的中间层小背板示意图。 本发明的较佳实施方式
本发明所述时钟同步系统包括机箱管理模块、 IPMC (智能平台管理控 制器）子卡模块； 还包括： 时钟子卡、 时钟后插模块、 中间层小背板模块。
下面对各个模块分别介绍，其中 IPMC子卡是独立位于各个 ATCA的节 点板上的， 实现 PICMG3.0规范规定的单板管理功能， 测量、 监控节点板状 态， 记录异常事件日志， 并在异常时通过 IPMB (智能平台管理总线）接口 向机箱管理模块上报告警或者状态信息。 网管可以通过机箱管理模块， 配置 查询外部时钟基准， 以及机箱管理模块向网管上报当前基准选择情况， 时钟 是否同步等。
时钟子卡以 AMC方式， 或者以非标准的子卡形式独立位于各个 ATCA 的节点板上， 用来满足时钟同步网的要求， 接收、 处理外部同步时钟信号， 包括时钟基准提取和接收电路， 分频电路， 数字鉴相电路， 时钟再生电路， 时钟质量循环监测电路。
时钟后插模块以 RTM (后插卡模块）形式位于 ATCA机箱的后部， 不 同于其他双星平面情况，仅仅使用一块后插卡模块来完成外部时钟基准的接 入、 阻抗匹配， 级联时钟的电平转换、 驱动、 分配、 监测， 以及级联时钟以 电缆或者光纤输出。
中间层小背板装置位于单板的 Zone3 区， 可以连接所有槽位的 Zone3 区， 根据产品具体情况， 也可以简化为单独连接两个相邻槽位的 Zone3区， 实现单路外部输入时钟基准在多个 ATCA节点板的互连分配， 线路提取时 钟、 各个槽位级联时钟的输出互连。
上述时钟同步系统的实现方法包括以下步骤：
第一步： 将两个时钟子卡分别插入两个随机槽位的节点板，通过中间层 小背板模块， 将一个时钟后插模块随机连接到某个槽位；
第二步： 机箱上电， 机箱管理模块正常启动后， 通过 IPMB接口与各个 节点板上的 IPMC子卡通讯， 获取节点板上时钟子卡在位情况， 根据节点板 的硬件地址得到时钟总线驱动端的物理槽位号， 并上 4艮给网管， 图形方式实 时显示同步时钟槽位和状态；
第三步： 根据第二步获取的总线驱动端的物理槽位号，机箱管理模块查 询这两块节点板的健康情况， 通过 IPMB (智能平台管理总线）接口， 设置 这两块节点板使用同一个时钟基准，时钟后插模块将外部时钟基准通过中间 层小背板模块发送给这两块节点板，然后机箱管理模块与健康情况最好的节 点板通信， 令其将处理过的时钟输出到 ATCA背板的时钟总线上， 输出级 联同步时钟到时钟后插模块， 而另外一块节点板只对输入基准时钟进行处 理， 不允许输出到背板时钟总线和后插模块；
第四步： 机箱管理模块实时监控这两块节点板的健康情况，根据健康情 况， 或者 居网管强制选择命令， 选择输出时钟信号的节点板， 由节点板的 硬件控制两个节点板的时钟输出切换以及切换的时间点；
第五步： 由于输出的级联时钟切换点选择合适， 不影响级联机箱的时钟 同步情况， 级联机箱不需要额外处理， 只要根据接入级联时钟的节点板对级 联输入时钟的监测情况， 独立选择合适的级联过来的时钟即可。
下面结合附图及实施例对本发明作进一步详细的描述：
如图 3所示， 图 3为本发明所述时钟同步系统的整体结构示意图， 其中 硬件模块部分包括：
A、 机箱管理模块；
B、 IPMC (智能平台管理控制器）子卡模块；
这两个模块是 PICMG3.0规范定义的标准模块， 包括实现这两个模块之 间通信的 IPMI协议，主要完成节点板与机箱之间关于节点板信息上报管理、 监控、 网管命令实现等单板管理功能。
C, 时钟子卡;
D 时钟后插模块；
E、 中间层小背板装置；
此三个模块为发明核心， 其时钟同步实施方式是： 首先来自运营商的外 部时钟基准， 或者本系统节点板提取外部接口线路时钟， 通过线缆接入时钟 后插卡， 由后插卡传入中间层小背板， 中间层小背板上所有 Zone3区插座 1 (第一 Zone3插座）互连， 插座 2 (第二 Zone3插座）提供级联时钟输出互 连， 保证一块时钟后插模块随机插入任意槽位都能够输入时钟基准到节点 板， 输出级联时钟到后插卡。 节点板和后插卡的 Zone3插头、 插座通过中间 层小背板连接， 插头 1连接插座 1， 插头 2连接插座 2。 时钟基准通过插头 1接入节点板的时钟子卡，进行基准盾量监测，选择一路基准时钟进行分频、 鉴相， 控制时钟子卡上的 OCXO输出与基准时钟的频率、 相位一致的时钟， 然后根据本板的 IPMC和机箱管理模块协商结果， 控制时钟驱动、 分发到背 板时钟总线 A/B 上， 通过频率变换， 生成系统所需要的其他频率时钟， 转 换为合适的电平，输出到时钟后插卡，保证任意时刻整个系统只有一个时钟 驱动端。
图 4和图 5分别为机箱管理模块功能示意图和硬件原理图，硬件核心为 逻辑器件实现 I2C接口，由模块软件实现各种网管接口，与 IPMC进行通信， 用于监测、控制机箱中的节点板板和其它功能模块，报告系统异常并进行基 本的恢复操作。
1 )热插拔管理；
2 ) 电源功率分配管理；
3 )机箱散热管理；
4 ) 电子开关控制节点板与背板连接端口的打开 /关闭；
5 ) 背板 IPMB总线故障检测、 管理与恢复。
如图 6所示， IPMC子卡软件、 硬件主要实现如下功能：
1 )提供 ATCA规范定义的智能平台管理总线接口， 物理上为图 6中的 I2C接口， 根据已有的 IPMI协议与机箱管理模块交互通信， 实现可控制的 单板上下电， 热插拔緩沖及隔离控制功能；
2 )具备传感器数据记录和其他关键数据的非易失性存储功能， 通过测 量子卡所在载板提供的传感器上传的电压， 按照 ATCA规范要求的传感器 数据记录（SDR )格式， 保存在子卡上 FLASH或者 NV-SRAM里；
3 )提供对 ATCA单板的电源管理接口， 在子卡和 ATCA单板之间有直 接的硬件连线， 可以直接控制单板电源开关， 控制、 获取单板 CPU状态， 控制单板有效载荷电源；
4 )提供 ATCA单板前面板指示灯的控制接口， 指示灯和扳手开关信号 连接到 EPLD芯片的输入、输出端口， 在内部集中为 8位寄存器和相应的寄 存器号， 单片机 W83910F通过数据总线直接向 EPLD写入和读出离线状态 指示灯、 热插拔指示灯、 告警灯状态、 前面板扳手开关状态；
5 )提供一个硬件监视接口， 以现成的监测芯片实现对单板电压、 温度 的监视， 风扇转速测量及转速控制。
时钟子卡的结构原理如图 7所示， 时钟子卡用于对外部基准进行转换、 分频、 质量监测， 由单片机根据时钟基准的优先级和质量情况， 选择一路时 钟， 与子卡上 OCXO (恒温晶体振荡器）输出的时钟进行相位比较， 相位差 值通过 D/A (数字 /模拟转换)器件转换为模拟电压， 控制 OCXO时钟的相位 与基准时钟一致。 此时对 OCXO输出的时钟再次分频， 生成系统需要的各 种频率的同步时钟。 时钟子卡可以采用标准的 AMC子卡， 也可以采用自定 义的子卡。
时钟后插模块的结构如图 7所示；中间层小背板模块的结构如图 8所示。 中间层小背板模块正反面均有两排插座： 一排为 Zone3插座 1 , 用于连接时 钟子卡的时钟基准接入接口和另一时钟后插模块的时钟基准输出接口；另一 排为 Zone3插座 2， 用于连接时钟子卡的级联时钟输出接口和另一时钟后插 模块的级联时钟接入接口；所有 Zone3插座 1互连，所有 Zone3插座 2互连。 时钟后插模块与中间层小背板配套使用，完成外部基准时钟接入到各个有可 能插时钟子卡的节点板，根据级联机箱距离和使用环境，对节点板输出的用 于级联机箱同步的时钟进行电平转换，输出到后插卡面板上的插座上， 或者 通过光模块转换为光信号， 以便通过电缆或光纤连接级联机箱，也可以同时 采用电缆和光纤连接级联机箱。
以上所述仅为本发明的较佳实施例而已， 并不用以限制本发明， 凡在本 发明的精神和原则之内所作的任何修改、等同替换和改进等， 均应包含在本 发明的保护范围之内。

Claims

权 利 要 求 书
1、 一种先进电信计算机体系的时钟同步系统， 该系统位于机箱内， 所述机箱包括节点板和背板， 其特征在于， 所述系统包括： 时钟后插模块、 中间层小背板模块和时钟子卡；
所述时钟后插模块用于接入外部时钟基准，将其通过所述中间层小背板 模块传送给所述时钟子卡；
所述时钟子卡位于所述节点板上， 用于接收、 处理外部时钟基准， 选择 一路基准时钟， 处理成系统需要的时钟后，将其发送到所述背板上的时钟总 线；
所述中间层小背板模块位于所述节点 的 Zone3区，用于将各槽位节点 板上时钟子卡的时钟基准接入接口互连。
2、 如权利要求 1所述的先进电信计算机体系的时钟同步系统， 其特 征在于，
所述时钟子卡还用于输 级联同步时钟，通过中间层小背板模块发送给 时钟后插模块；
所述时钟后插模块还用于接收来自时钟子卡的级联同步时钟信号进行 处理， 并提供级联时钟输出接口和级联时钟接入接口；
所述中间层小背板模块还用于将各槽位节点板上时钟子卡的级联时钟 输出接口互连。
3、 如权利要求 2所述的先进电信计算机体系的时钟同步系统， 其特 征在于， 所述中间层小背板模块的正反面均有两排插座： 一排为第一 Zone3 插座，用于连接所述时钟子卡的时钟基准接入接口和所述时钟后插模块的时 钟基准输出接口； 另一排为第二 Zone3插座， 用于连接所述时钟子卡的级联 时钟输出接口和所述时钟后插模块的级联时钟接入接口。
4、 如权利要求 3所述的先进电信计算机体系的时钟同步系统， 其特 征在于， 所述中间层小背板模块上的所有第一 Zone3 插座互连， 所有第二 Zone3插座互连。
5、 如权利要求 1所述的先进电信计算机体系的时钟同步系统， 其特 征在于， 所述时钟同步系统还包括机箱管理模块， 该模块用于配置外部时钟 基准，提供给时钟子卡，并向网管报告当前基准选择情况以及时^ 7同步情况。
6、 如权利要求 5所述的先进电信计算机体系的时钟同步系统， 其特 征在于， 所述时钟同步系统还包括智能平台管理控制器子卡模块， 该模块位 于所述节点板上， 用于实现单板管瑄功能， 所述单板管理功能包括测量、监 控节点板状态，记录异常事件日志， 并在异常时向所述机箱管理模块上 4艮告 警或者状态信息。
7、 如权利要求 1所述的先进电信计算机体系的时钟同步系统， 其特 征在于， 所述时钟子卡以先进夹层子卡方式独立位于节点板上， 所述时钟后 插模块以后插卡模块形式位于机箱的后部。
8、 一种先进电信计算机体系的时钟同步方法， 其特征在于， 包括以 下步骤：
a: 将两个时钟子卡分别插入两个节点板， 并将时钟后插卡通过中间层 小背板模块与各节点板相连；
b: 机箱上电， 机箱管理模块启动， 获取时钟总线驱动端的物理槽位号， 该时钟总线驱动端为插有时钟子卡的节点板；
c: 根据所述物理槽位号， 机箱管理模块设置所述两个节点板使用同一 个时钟基准； d: 时钟后插模块将外部时钟基准通过中间层小背板模块发送给上述两 个节点板， 其中一个节点板处理所述外部时钟基准， 选择一路基准时钟， 处 理成系统需要的频率的时钟后， 将其发送到所述背板上的时钟总线。
9、 如权利要求 8所述的先进电信计算机体系的时钟同步方法， 其特 征在于， 所述步骤 b中， 获取时钟总线驱动端的物理槽位号的方法为： 机箱 管理模块与各节点板上的智能平台管理控制器子卡模块通讯，获取节点板上 的时钟子卡在位情况，根据节点板的硬件地址获取时钟总线驱动端的物理槽 位号。
10、 如权利要求 8所述的先进电信计算机体系的时钟同步方法， 其特 征在于， 所述步骤 d中， 所述两个节点板中健康情况最好的节点板处理所述 外部时钟基准， 并按照优先级选择一路基准时钟。
11、 如权利要求 10所述的先进电信计算机体系的时钟同步方法，其特 征在于， 所述步骤 d之后还包括：
e: 机箱管理模块实时益控所述两个节点板的健康状况， 根据健康状况 或网管的强制选择命令，选择输出时钟信号的节点板， 由节点板的硬件控制 两个节点板的时钟输出切换以及切换的时间点。
12、 如权利要求 8或 11所述的先进电信计算机体系的时钟同步方法， 其特征在于， 所述步骤 d后还包括：
f: 所述节点板获得级联时钟信号， 将其发送给所述时钟后插模块； g: 级联机箱根据接入级联时钟的节点板对级联输入时钟的监控情况， 选择合适的级联过来的时钟。
13、 如权利要求 8所述的先进电信计算机体系的时钟同步方法， 其特 征在于， 所述步骤 d还包括： 所述两个节点板的另一节点板只对输入基准进 行处理， 不允许输出到背板时钟总线和后插模块。
14、 如权利要求 8所述的先进电信计算机体系的时钟同步方法， 其特 征在于， 所述方法中各节点板的槽位为任意槽位。
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