WO2009028051A1 - メモリの試験方法及びメモリ試験装置 - Google Patents

メモリの試験方法及びメモリ試験装置 Download PDF

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Publication number
WO2009028051A1
WO2009028051A1 PCT/JP2007/066679 JP2007066679W WO2009028051A1 WO 2009028051 A1 WO2009028051 A1 WO 2009028051A1 JP 2007066679 W JP2007066679 W JP 2007066679W WO 2009028051 A1 WO2009028051 A1 WO 2009028051A1
Authority
WO
WIPO (PCT)
Prior art keywords
random number
memory
test method
regenerated
tester
Prior art date
Application number
PCT/JP2007/066679
Other languages
English (en)
French (fr)
Inventor
Takeshi Yanase
Shuichi Kameyama
Kouji Uesaka
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/066679 priority Critical patent/WO2009028051A1/ja
Publication of WO2009028051A1 publication Critical patent/WO2009028051A1/ja

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56004—Pattern generation

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

　第１の乱数を生成し、第１の乱数により被試験メモリのアドレスを指定し、第２の乱数を生成し、第２の乱数をデータとして、指定されるアドレスに対して書き込み、第１の乱数と同一の値をとる乱数を再度生成し、再度生成した乱数により被試験メモリのアドレスを指定し、書き込まれたデータを読み出し、第２の乱数と同一の値をとる乱数を再度生成し、再度生成した乱数と、読み出されたデータとを比較するメモリ試験方法を提供する。
PCT/JP2007/066679 2007-08-28 2007-08-28 メモリの試験方法及びメモリ試験装置 WO2009028051A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/066679 WO2009028051A1 (ja) 2007-08-28 2007-08-28 メモリの試験方法及びメモリ試験装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/066679 WO2009028051A1 (ja) 2007-08-28 2007-08-28 メモリの試験方法及びメモリ試験装置

Publications (1)

Publication Number Publication Date
WO2009028051A1 true WO2009028051A1 (ja) 2009-03-05

Family

ID=40386795

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/066679 WO2009028051A1 (ja) 2007-08-28 2007-08-28 メモリの試験方法及びメモリ試験装置

Country Status (1)

Country Link
WO (1) WO2009028051A1 (ja)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0357979A (ja) * 1989-07-27 1991-03-13 Nec Corp メモリ検査装置
JPH03296676A (ja) * 1990-04-16 1991-12-27 Nec Corp オンチップメモリテスト回路およびテスト方法
JPH05250900A (ja) * 1992-03-09 1993-09-28 Mitsubishi Electric Corp テスト機能付き半導体集積回路
JPH06102327A (ja) * 1992-09-18 1994-04-15 Sony Corp メモリ内蔵型半導体集積回路およびその論理設計方法
JPH07320499A (ja) * 1994-05-27 1995-12-08 Canon Inc メモリの試験装置およびメモリの試験方法
JPH0963298A (ja) * 1995-08-25 1997-03-07 Oki Electric Ind Co Ltd Ｒａｍのテスト回路
JP2004326893A (ja) * 2003-04-23 2004-11-18 Renesas Technology Corp 試験回路装置
JP3791757B2 (ja) * 2000-11-15 2006-06-28 松下電器産業株式会社 診断機能を備えた半導体集積回路
JP2006318115A (ja) * 2005-05-11 2006-11-24 Sony Corp 半導体記憶装置及び半導体記憶装置機能検査方法並びに半導体記憶装置を有する電子機器

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0357979A (ja) * 1989-07-27 1991-03-13 Nec Corp メモリ検査装置
JPH03296676A (ja) * 1990-04-16 1991-12-27 Nec Corp オンチップメモリテスト回路およびテスト方法
JPH05250900A (ja) * 1992-03-09 1993-09-28 Mitsubishi Electric Corp テスト機能付き半導体集積回路
JPH06102327A (ja) * 1992-09-18 1994-04-15 Sony Corp メモリ内蔵型半導体集積回路およびその論理設計方法
JPH07320499A (ja) * 1994-05-27 1995-12-08 Canon Inc メモリの試験装置およびメモリの試験方法
JPH0963298A (ja) * 1995-08-25 1997-03-07 Oki Electric Ind Co Ltd Ｒａｍのテスト回路
JP3791757B2 (ja) * 2000-11-15 2006-06-28 松下電器産業株式会社 診断機能を備えた半導体集積回路
JP2004326893A (ja) * 2003-04-23 2004-11-18 Renesas Technology Corp 試験回路装置
JP2006318115A (ja) * 2005-05-11 2006-11-24 Sony Corp 半導体記憶装置及び半導体記憶装置機能検査方法並びに半導体記憶装置を有する電子機器

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