WO2009022252A2 - Bond pad arrangement of an integrated circuit - Google Patents

Bond pad arrangement of an integrated circuit Download PDF

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Publication number
WO2009022252A2
WO2009022252A2 PCT/IB2008/053093 IB2008053093W WO2009022252A2 WO 2009022252 A2 WO2009022252 A2 WO 2009022252A2 IB 2008053093 W IB2008053093 W IB 2008053093W WO 2009022252 A2 WO2009022252 A2 WO 2009022252A2
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WO
WIPO (PCT)
Prior art keywords
die attach
metal die
planar
chip
integrated circuit
Prior art date
Application number
PCT/IB2008/053093
Other languages
French (fr)
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WO2009022252A3 (en
Inventor
Jörg SYRE
Original Assignee
Nxp B.V.
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Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2009022252A2 publication Critical patent/WO2009022252A2/en
Publication of WO2009022252A3 publication Critical patent/WO2009022252A3/en

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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Definitions

  • the present invention is related to die bonding technology, in particular to a small- size layout for the surface areas of the planar final metal die attach pads in a novel CSP-type semiconductor integrated circuit chip device assembly, wherein each final metal die attach pad contained in this assembly layout has a surface area that is smaller in size than those of conventional semiconductor integrated circuit chips that are to be mounted on a printed circuit board's substrate in chip-scale package technology.
  • a lead frame typically includes tie bars which support an array of die attach pads and contacts which are associated with each die attach pad. Thereby, a die is mounted onto each die attach pad and electrically connected to the associated contacts. The contacts provide the physical connection between the input and output terminals of the die and those of the printed circuit board.
  • a molding material is then applied to encapsulate the die and the non-contact surfaces of the contacts. The molding material serves to protect the integrated circuit and makes it easier to handle. After having applied the molding compound, each packaged die is cut from the molded lead frame and is then ready to be mounted onto a printed circuit board.
  • a common approach uses non-conductive or conductive epoxy for die-to- substrate attachment.
  • the die is glued to the substrate, and the epoxy is cured to achieve a good die attach.
  • a second method which involves an eutectic die attach, is used in most military applications and in cases where heat conduction is important.
  • a gold-tin solder preform on the substrate is brought in contact with the semiconductor, and - with the aid of a temperature of about 360 0 C - the eutectic point is reached such that attachment occurs.
  • These techniques require gold or aluminum wires to be bonded on the output pads of the device. Owing to the complexity of today's inte- grated semiconductor circuits, there are many output pads which require a plurality of wires to be bonded. Furthermore, there is also a demand to attach more than one circuit on a single substrate for the sake of space economy.
  • tape automated bonding Another technique which is widely used is tape automated bonding. Thereby, a special frame having the configuration of the output pads on the chip is placed over the chip. A heated bonding tool is then lowered to apply pressure and temperature for thermocompression bonding. Another method of implementing this same idea is to use solder for frame attachment to a die. Tape-automated bonding packaging fits very well with automation where a spool with the frame is moved over dies which are placed on a chuck. AIl of the aforementioned packaging techniques do not fit well with multi-chip hybrid or chip-on-board packaging.
  • flip chip technology is has emerged as a viable packaging approach for GaAs devices which are operating at microwave and millimeter wave frequencies. Flip chip bonding leads to high packaging densities, faster circuits, and eliminates wire bonding.
  • Various methods to obtain reliable processes are being investigated by many corporations. In general, a metal bump is grown on the chip, on the substrate or on both. The chip is flipped over, aligned to the substrate and then bonded. The "bumped" chip is elevated from the surface of the substrate by the height of the bumps, and electrical connection occurs on the top layer. There are basically four different methods being investigated.
  • the most common method is the use of solder balls "grown" on the out- put pads of the die and the substrate. As mentioned before, the die is flipped over, aligned to the substrate, and bonded by heating the solder to the reflow point. Die alignment with the substrate is through the mechanism of the surface tension of the solder.
  • gold bump to gold or aluminum pads may be used in conjunction with thermocompression bonding. Thereby, heat and pressure are used to achieve a reliable contact between the die and the substrate.
  • a variation on this theme can be the use of ultrasonic bonding of gold to gold after the alignment and contact.
  • Indium which is mainly used where cryogenic temperatures are required for the operation of the device, may also be used for flip chip bonding.
  • One of the main applications is for focal plane arrays and special detectors. Thereby, an indium layer is deposited on the die and substrate by plating, or evaporation and lift-off technique to obtain the bumps.
  • Conductive epoxy is also utilizable for flip chip bonding.
  • the epoxy can be screened on the substrate, and the operation is similar to the process explained before.
  • Some chip-scale packages (e.g. Amkor's Ultra CSPTM package licensed from FlipChip International as its standard wafer level package offering, that has been widely adopted as the industrial standard for cost-effective, high performance wafer level CSP applications) uses conventional CSP solder bumps on top of the semiconductor chips which are to be bumped. These bumps require a solderable area on top of the chip for adhesion. This area is made of metal, e.g. copper (Cu), silver (Ag) or nickel (Ni). This so-called under-bump metal (UBM) is deposited on top of the passivation of the semiconductor chip. It is connected to the interconnection metal layer of the semiconductor chip via one or several openings in the die passivation layer.
  • UBM under-bump metal
  • a semiconductor die metal layout for flip chip packaging which provides flat under-bump metal layers.
  • adjacent surface-mounted metal die pads are arranged narrower to each other than adjacent UBM layers so as to accommodate decreased die pitch. This is achieved by depositing a metal region adjacent to and closely spaced from the metal die pad which - together with this die pad - is capable of providing a substrate with a substantially flat passivation layer surface on which the aforementioned UBM layers are subse- quently deposited.
  • the adjacent closely spaced metal region may be provided by bringing metal traces closer to metal die pads whose surface areas are reduced in size, which means into the die surface areas underlying the UBM layers, and/or by depositing dummy metal similarly near to the die pad.
  • the dummy metal may also be deposited over the whole chip surface area that is not occupied by other electrical components.
  • planar final metal die attach pad layers of a semiconductor integrated circuit to be bonded onto a printed circuit board by means of solder bumps have a larger diameter than the corresponding under-bump metallization layers associated with these metal die attach pads.
  • the critical mechanical part is the outer edge of a planar metal die attach pad, which is because this is the point where die crack initiation is very likely to begin.
  • the UBM diameter is defined as minimal 280 ⁇ m, such that the surface area of the final metal die attach pad has to have a diameter of almost 300 ⁇ m.
  • this die attach pad will have a parasitic capacitance to the silicon substrate of about 3 to 5 pF.
  • the above-mentioned parasitic metal-silicon capacitance is det- rimental.
  • the planar metal die attach pad area surfaces are larger in size than their under-bump metallization (UBM) area. Reducing the parasitic metal-silicon capacitance, which can easily be achieved by using metal die attach pads with smaller surface areas, is very lifetime-critical in cases where metal bonding wires are required, which results in that the semiconductor chip device might possibly fail during mechanical stress.
  • a significant problem concerning the robustness of the assembly are the edges of the under-bump metallization area, which is due to the fact that there are high stress forces along these edges during the lifetime of a chip-scale packaged semiconductor chip device assembly.
  • a die crack typically starts at the position of the UBM edge and the final metal die attach pad, which may cause a fail of the entire semiconductor chip device. Stepped structures under these edges could also possibly decrease the lifetime of the CSP product. It may thus be an object of the present invention to reduce the occurring parasitic metal-silicon capacitance of conventional semiconductor chip device assemblies that are fabricated in chip-scale package (CSP) technology.
  • CSP chip-scale package
  • the present invention is therefore directed to a chip-scale package type semiconductor integrated circuit chip device assembly bonded onto an array of planar metal die attach pad layers on a printed circuit board's substrate.
  • said planar metal die attach pad layers are respectively placed beneath a corresponding one from an array of subsequently arranged, spaced under-bump metallization layers associated with said planar metal die attach pad layers, wherein said semiconductor chip device assembly are attached to the printed circuit board's substrate by means of an array of solder bumps associated to said planar metal die attach pad layers.
  • said planar metal die attach pad layers are placed beneath the under-bump metallization layers associated with these die attach pads.
  • said chip-scale package type semiconductor integrated circuit chip device assembly is fabricated in such a way that the aforementioned die attach pad layers do not protrude over the outer edges of their associated UBM layers.
  • the die attach pads of said chip device assembly may have a reduced or equal surface area size compared with the planar final metal die attach pad surface area sizes of conventional die-bonded chip-scale packaged semiconductor integrated circuit chips.
  • the invention proposes to use a very thin and hard metal layer for wiring.
  • this metal bonding layer can be used as a surface-mounted ohmic resistor.
  • Fig. 1 shows a rear-side view of a bonded die on a substrate of an integrated circuit's chip-scale package (CSP) type semiconductor chip device assembly for illustrating the beginning of a die crack at the edge position of a solder bump's under-bump metallization layer and a planar metal die attach pad forming the final metal surface layer of the semiconductor chip,
  • CSP chip-scale package
  • Fig. 2 shows a top view and a longitudinal cross-sectional side view of a conventional chip-scale packaged semiconductor chip mounting assembly comprising an under-bump metallization layer, a die passivation layer and planar final metal die attach pads, the latter being interconnected by an electrically conductive metal lead segment constituting an ohmic resistor,
  • Fig. 3 shows a top view and a longitudinal cross-sectional side view of a new
  • Fig. 4 exemplarily illustrates a simplified CSP layout of the Philips Semiconductors 74LV573 integrated circuit (product No.: IP 4040) in a top view as an example for a CSP-type semiconductor chip device assembly.
  • Fig. 1 shows a rear-side view of a bonded die on a substrate of an integrated circuit's CSP type semiconductor chip device assembly, from which it becomes apparent that a die crack (which means a crack of the bond wire 1 interconnecting a die attach pad of said semiconductor chip with another contact on the substrate) typically begins at the edge position 2 of a solder bump's (3) UBM layer 5 and the planar metal die attach pad 4 constituting the final metal surface layer of the bonded semiconductor chip.
  • a die crack which means a crack of the bond wire 1 interconnecting a die attach pad of said semiconductor chip with another contact on the substrate
  • a top view and a longitudinal cross-sectional side view of a conventional chip-scale packaged semiconductor chip mounting assembly is shown.
  • the depicted CSP layout comprises an under-bump metallization layer 5, electrically conductive metal lead segments 6a constituting and being used as ohmic resistors, which may be divided into two separate parts located at both sides of the solder bumps 3 and spaced by a passivation opening d, thereby protruding over the outer edges of the under-bump metallization layers 5.
  • said layout comprises final metal die attach pads 9 with planar surface areas mounted onto a silicon substrate 8 as well as a metal resistor layer 6b, that may e.g.
  • TiWN titanium tungsten nitride
  • Ta tantalum
  • TaN tantalumnitride
  • Fig. 3 shows a top view and a longitudinal cross- sectional side view of a new CSP-type semiconductor chip mounting assembly with a novel small-size layout for the planar final metal die attach pads 9 according to an exemplary embodiment of the present invention.
  • the planar surface areas of the final metal die attach pads 9 under the under-bump metallization layers 5 differ from those depicted in Fig. 2 in being smaller in size than the surface areas of their respectively associated UBM layers 5 without protruding over the outer edges of these under-bump metallization layers 5.
  • the conductive metal lead segment 6a constituting said ohmic resistor which may also be divided into two separate parts located at both sides of the solder bumps 3 and spaced by a passivation opening d, goes beneath the under-bump metallization layers 5 and, in the surface area range of the planar final metal die attach pads 9 associated with the respective UBM layers 5, is limited in size by the outer edges of said UBM layers 5.
  • dummy metal fills 7 adjacent to and closely spaced from said final metal die attach pads 9 may subsequently be deposited on the substrate so as to reduce parasitic silicon-metal capacitance.
  • said dummy metal fills 7, which may e.g. be made of aluminium (In, interconnection layer)) or any other suitable fill-in metal layer, may also be hermetically covered by said passivation layer 6a.
  • the most important difference in comparison with the semiconductor chip assembly depicted in Fig. 2 consists in that the metal resistor layer lies beneath the under-bump metallization layer such that said metal resistor layer does not protrude over the outer edge of the under-bump metallization layer.
  • the critical outer edge of the final metal die attach pad is far away from the outer edge of the UBM layer, where - under thermal or mechanical stress - the biggest mechanical forces arise.
  • a simplified CSP layout of an octal D-type transparent latch featuring separate D-type inputs for each latch as well as tri-state outputs for bus- oriented applications as implemented by the 74LV573 - a low-voltage Si-gate CMOS device developed by Philips Semiconductors (product No.: IP 4040) - is shown in a top view as an example for a chip-scale packaged semiconductor integrated circuit.
  • the simplified CSP layout exemplarily comprises an array of 25 interconnected die attach pads which are arranged in a square as well as contacts that are associated with these die attach pads. Moreover, only three different layers are shown, the planar metal die attach pad, the metal resistors as well as the under-bump metallization layer.
  • the present invention can be applied in the field of die bonding technol- ogy, in particular for fabricating chip-scale package type semiconductor chip device assemblies where a small-size layout for the surface area of the planar final metal die attach pad is required, such as e.g. for attaching the Philips Semiconductors 74LV573 integrated circuit or any other semiconductor dies with low parasitic metal-silicon capacitance requirements on a silicon or silicon dioxide substrate.
  • a computer program may be stored/distributed on a suitable medium, such as e.g. an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as e.g. via the Internet or other wired or wireless telecommunication systems. Any reference signs in the claims should not be construed as limiting the scope of the invention.

Abstract

The present invention is related to die bonding technology, in particular to a small- size layout for the surface areas of the planar final metal die attach pads (9) in a novel CSP-type semiconductor integrated circuit chip device assembly, wherein each planar final metal die attach pad (9) contained in this assembly layout has a surface area that is smaller in size than those of conventional semiconductor integrated circuit chips that are to be mounted on a printed circuit board's substrate in chip-scale package technology. For applications with a restricted upper tolerable limit for the total capacitance of the integrated circuit, parasitic metal-silicon capacitance, which occurs between each planar final metal die attach pad (9) and the substrate (8), is detrimental. For mechanical robust CSP products, on the other hand, it is a necessary requirement that the planar metal die attach pad area surfaces are larger in size than their associated under-bump metallization (UBM) areas (5). Reducing said parasitic metal-silicon capacitance, which can easily be achieved by using metal die attach pads (9) with smaller surface areas, is very lifetime-critical in cases where metal bonding wires (1) are required and results in that the semiconductor chip device might possibly fail during mechanical stress. A significant problem concerning the robustness of the assembly are the edges of the under-bump metallization areas (5), which is because there are usually high stress forces along these edges during the lifetime of said chip-scale packaged semiconductor chip device assembly. The present invention therefore proposes a chip-scale packaged semiconductor chip device assembly bonded onto planar final metal die attach pad layers (9) on a printed circuit board (8) by means of solder bumps, wherein the surface areas of the planar final metal die attach pad layers (9) are smaller in size than their associated under-bump metallization layers (5). For die-to-die bond wiring, very thin and hard electrically conductive materials are proposed which - according to a refinement of the present invention - may be used as surface-mounted ohmic resistors. In this case, the mechanical stability of the bump-chip connection is still given, and, at the same time, parasitic metal-silicon capacitances of the die attach pads to the substrate are reduced.

Description

Small-Size Layout for the Planar Final Metal Die Attach Pads of an Integrated Circuit's CSP-Type Semiconductor Chip Device Assembly
FIELD OF INVENTION
The present invention is related to die bonding technology, in particular to a small- size layout for the surface areas of the planar final metal die attach pads in a novel CSP-type semiconductor integrated circuit chip device assembly, wherein each final metal die attach pad contained in this assembly layout has a surface area that is smaller in size than those of conventional semiconductor integrated circuit chips that are to be mounted on a printed circuit board's substrate in chip-scale package technology.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuit chips are typically fabricated in wafer form. After fabrication, individual dies are cut from the wafer and then packaged. Generally, many dies are packaged simultaneously on a metal lead frame. A lead frame typically includes tie bars which support an array of die attach pads and contacts which are associated with each die attach pad. Thereby, a die is mounted onto each die attach pad and electrically connected to the associated contacts. The contacts provide the physical connection between the input and output terminals of the die and those of the printed circuit board. A molding material is then applied to encapsulate the die and the non-contact surfaces of the contacts. The molding material serves to protect the integrated circuit and makes it easier to handle. After having applied the molding compound, each packaged die is cut from the molded lead frame and is then ready to be mounted onto a printed circuit board.
With increasing packaging density and device operation speed (digital) or operating frequency (analog), new challenges have been imposed in the field of electronic packaging. New packaging techniques such as tape-automated bonding are quickly replacing wire bonding in many areas. The conventional packaging approach is a two step process. First, the semiconductor chip is attached (face-up fashion) to the substrate or metallic carrier using a conductive epoxy adhesive or eutectic solder bond. Second, the interconnect operation, wherein electrical continuity between the chip and the rest of the circuitry is established, is completed by wire bonds. Even with automated assembly procedures, this approach is both time-consuming and defect prone. Flip chip bonding is a viable substitute for and utilizable in addition to tape-automated bonding.
There are several ways to attach a die to the substrate of a printed circuit board. A common approach uses non-conductive or conductive epoxy for die-to- substrate attachment. In this technique, the die is glued to the substrate, and the epoxy is cured to achieve a good die attach. A second method, which involves an eutectic die attach, is used in most military applications and in cases where heat conduction is important. A gold-tin solder preform on the substrate is brought in contact with the semiconductor, and - with the aid of a temperature of about 360 0C - the eutectic point is reached such that attachment occurs. These techniques require gold or aluminum wires to be bonded on the output pads of the device. Owing to the complexity of today's inte- grated semiconductor circuits, there are many output pads which require a plurality of wires to be bonded. Furthermore, there is also a demand to attach more than one circuit on a single substrate for the sake of space economy.
Early attempts to get away from wire bonding were successfully imple- mented with the beam lead technology in which thin gold leads protrude from the outer edge of the device via a special metallization process. The device is flipped over and a special wobbling tool attaches all the beams to substrate in one motion.
Another technique which is widely used is tape automated bonding. Thereby, a special frame having the configuration of the output pads on the chip is placed over the chip. A heated bonding tool is then lowered to apply pressure and temperature for thermocompression bonding. Another method of implementing this same idea is to use solder for frame attachment to a die. Tape-automated bonding packaging fits very well with automation where a spool with the frame is moved over dies which are placed on a chuck. AIl of the aforementioned packaging techniques do not fit well with multi-chip hybrid or chip-on-board packaging. Nowadays, there is a growing tendency to mount semiconductor chips on one substrate for increased density and increased operating speed of the device. Renewed interest has surfaced in the technique of flip chip bonding.
Another well-known approach for packaging semiconductor devices on a silicon or silicon dioxide substrate is flip chip technology. As described in the technical literature, flip chip technology is has emerged as a viable packaging approach for GaAs devices which are operating at microwave and millimeter wave frequencies. Flip chip bonding leads to high packaging densities, faster circuits, and eliminates wire bonding. Various methods to obtain reliable processes are being investigated by many corporations. In general, a metal bump is grown on the chip, on the substrate or on both. The chip is flipped over, aligned to the substrate and then bonded. The "bumped" chip is elevated from the surface of the substrate by the height of the bumps, and electrical connection occurs on the top layer. There are basically four different methods being investigated.
The most common method is the use of solder balls "grown" on the out- put pads of the die and the substrate. As mentioned before, the die is flipped over, aligned to the substrate, and bonded by heating the solder to the reflow point. Die alignment with the substrate is through the mechanism of the surface tension of the solder.
Aside therefrom, gold bump to gold or aluminum pads may be used in conjunction with thermocompression bonding. Thereby, heat and pressure are used to achieve a reliable contact between the die and the substrate. A variation on this theme can be the use of ultrasonic bonding of gold to gold after the alignment and contact.
Indium, which is mainly used where cryogenic temperatures are required for the operation of the device, may also be used for flip chip bonding. One of the main applications is for focal plane arrays and special detectors. Thereby, an indium layer is deposited on the die and substrate by plating, or evaporation and lift-off technique to obtain the bumps.
Conductive epoxy is also utilizable for flip chip bonding. The epoxy can be screened on the substrate, and the operation is similar to the process explained before.
Some chip-scale packages (e.g. Amkor's Ultra CSP™ package licensed from FlipChip International as its standard wafer level package offering, that has been widely adopted as the industrial standard for cost-effective, high performance wafer level CSP applications) uses conventional CSP solder bumps on top of the semiconductor chips which are to be bumped. These bumps require a solderable area on top of the chip for adhesion. This area is made of metal, e.g. copper (Cu), silver (Ag) or nickel (Ni). This so-called under-bump metal (UBM) is deposited on top of the passivation of the semiconductor chip. It is connected to the interconnection metal layer of the semiconductor chip via one or several openings in the die passivation layer.
In US 6,118,180, a semiconductor die metal layout for flip chip packaging is disclosed which provides flat under-bump metal layers. In the herein described layout, adjacent surface-mounted metal die pads are arranged narrower to each other than adjacent UBM layers so as to accommodate decreased die pitch. This is achieved by depositing a metal region adjacent to and closely spaced from the metal die pad which - together with this die pad - is capable of providing a substrate with a substantially flat passivation layer surface on which the aforementioned UBM layers are subse- quently deposited. The adjacent closely spaced metal region may be provided by bringing metal traces closer to metal die pads whose surface areas are reduced in size, which means into the die surface areas underlying the UBM layers, and/or by depositing dummy metal similarly near to the die pad. The dummy metal may also be deposited over the whole chip surface area that is not occupied by other electrical components.
SUMMARY OF THE INVENTION In order to achieve reasonable mechanical stability (e.g. against thermal cycling), it is advisable that the planar final metal die attach pad layers of a semiconductor integrated circuit to be bonded onto a printed circuit board by means of solder bumps have a larger diameter than the corresponding under-bump metallization layers associated with these metal die attach pads. In general, the critical mechanical part is the outer edge of a planar metal die attach pad, which is because this is the point where die crack initiation is very likely to begin.
Unfortunately, this measure increases the area of the planar final metal die attach pad, and - as a consequence - large parasitic capacitances result from using these die attach pads. For instance, when regarding a CSP-type semiconductor integrated circuit chip assembly layout with 500 μm bump-to-bump distance, the UBM diameter is defined as minimal 280 μm, such that the surface area of the final metal die attach pad has to have a diameter of almost 300 μm. In a single metal layer process with reasonable dielectric layer thicknesses, this die attach pad will have a parasitic capacitance to the silicon substrate of about 3 to 5 pF.
For applications with a restricted upper tolerable limit for the total capacitance of the circuit, the above-mentioned parasitic metal-silicon capacitance is det- rimental. For mechanical robust CSP products, on the other hand, it is a necessary requirement that the planar metal die attach pad area surfaces are larger in size than their under-bump metallization (UBM) area. Reducing the parasitic metal-silicon capacitance, which can easily be achieved by using metal die attach pads with smaller surface areas, is very lifetime-critical in cases where metal bonding wires are required, which results in that the semiconductor chip device might possibly fail during mechanical stress. A significant problem concerning the robustness of the assembly are the edges of the under-bump metallization area, which is due to the fact that there are high stress forces along these edges during the lifetime of a chip-scale packaged semiconductor chip device assembly. A die crack typically starts at the position of the UBM edge and the final metal die attach pad, which may cause a fail of the entire semiconductor chip device. Stepped structures under these edges could also possibly decrease the lifetime of the CSP product. It may thus be an object of the present invention to reduce the occurring parasitic metal-silicon capacitance of conventional semiconductor chip device assemblies that are fabricated in chip-scale package (CSP) technology.
The present invention is therefore directed to a chip-scale package type semiconductor integrated circuit chip device assembly bonded onto an array of planar metal die attach pad layers on a printed circuit board's substrate. Thereby, said planar metal die attach pad layers are respectively placed beneath a corresponding one from an array of subsequently arranged, spaced under-bump metallization layers associated with said planar metal die attach pad layers, wherein said semiconductor chip device assembly are attached to the printed circuit board's substrate by means of an array of solder bumps associated to said planar metal die attach pad layers. In this assembly layout, said planar metal die attach pad layers are placed beneath the under-bump metallization layers associated with these die attach pads. In this context, the present invention provides that said chip-scale package type semiconductor integrated circuit chip device assembly is fabricated in such a way that the aforementioned die attach pad layers do not protrude over the outer edges of their associated UBM layers.
To achieve this, the die attach pads of said chip device assembly may have a reduced or equal surface area size compared with the planar final metal die attach pad surface area sizes of conventional die-bonded chip-scale packaged semiconductor integrated circuit chips. Aside from using smaller final metal die attach pads, the invention proposes to use a very thin and hard metal layer for wiring. According to an exemplary embodiment of the invention, this metal bonding layer can be used as a surface-mounted ohmic resistor. Thus, mechanical stability of the bump-chip connection is still given, and, simultaneously, the aforementioned parasitic metal-silicon capacitance, whose value is directly proportional to the surface area size of the planar metal die attach pad, is reduced.
BRIEF DESCRIPTION OF THE DRAWINGS Advantageous features, aspects, and advantages of the invention will become evident from the following description, the appended claims and the accompanying drawings. Thereby,
Fig. 1 shows a rear-side view of a bonded die on a substrate of an integrated circuit's chip-scale package (CSP) type semiconductor chip device assembly for illustrating the beginning of a die crack at the edge position of a solder bump's under-bump metallization layer and a planar metal die attach pad forming the final metal surface layer of the semiconductor chip,
Fig. 2 shows a top view and a longitudinal cross-sectional side view of a conventional chip-scale packaged semiconductor chip mounting assembly comprising an under-bump metallization layer, a die passivation layer and planar final metal die attach pads, the latter being interconnected by an electrically conductive metal lead segment constituting an ohmic resistor,
Fig. 3 shows a top view and a longitudinal cross-sectional side view of a new
CSP-type semiconductor chip mounting assembly with a novel small- size layout for the final metal die attach pads according to an exemplary embodiment of the present invention, and
Fig. 4 exemplarily illustrates a simplified CSP layout of the Philips Semiconductors 74LV573 integrated circuit (product No.: IP 4040) in a top view as an example for a CSP-type semiconductor chip device assembly.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
In the following, the proposed CSP-type semiconductor chip device assembly according to an exemplary embodiment of the present invention will be ex- plained in more detail with respect to special refinements and referring to the accompanying drawings. First, however, it shall briefly be illustrated at which spot die cracks typically emerge. Therefore, Fig. 1 shows a rear-side view of a bonded die on a substrate of an integrated circuit's CSP type semiconductor chip device assembly, from which it becomes apparent that a die crack (which means a crack of the bond wire 1 interconnecting a die attach pad of said semiconductor chip with another contact on the substrate) typically begins at the edge position 2 of a solder bump's (3) UBM layer 5 and the planar metal die attach pad 4 constituting the final metal surface layer of the bonded semiconductor chip.
In Fig. 2, a top view and a longitudinal cross-sectional side view of a conventional chip-scale packaged semiconductor chip mounting assembly is shown. As illustrated in this figure, the depicted CSP layout comprises an under-bump metallization layer 5, electrically conductive metal lead segments 6a constituting and being used as ohmic resistors, which may be divided into two separate parts located at both sides of the solder bumps 3 and spaced by a passivation opening d, thereby protruding over the outer edges of the under-bump metallization layers 5. Moreover, said layout comprises final metal die attach pads 9 with planar surface areas mounted onto a silicon substrate 8 as well as a metal resistor layer 6b, that may e.g. be made of a thin layer of titanium tungsten nitride TiWN, tantalum (Ta) or tantalumnitride (TaN) evaporated or sputtered onto the silicon substrate 8, thereby serving as an anti-oxidation protection that hermetically covers the metal bonding wires 1 , the metal die attach pads 9 and the silicon substrate 8.
In contrast thereto, Fig. 3 shows a top view and a longitudinal cross- sectional side view of a new CSP-type semiconductor chip mounting assembly with a novel small-size layout for the planar final metal die attach pads 9 according to an exemplary embodiment of the present invention. As can easily be taken from Fig. 3, the planar surface areas of the final metal die attach pads 9 under the under-bump metallization layers 5 differ from those depicted in Fig. 2 in being smaller in size than the surface areas of their respectively associated UBM layers 5 without protruding over the outer edges of these under-bump metallization layers 5. In addition to that, the conductive metal lead segment 6a constituting said ohmic resistor, which may also be divided into two separate parts located at both sides of the solder bumps 3 and spaced by a passivation opening d, goes beneath the under-bump metallization layers 5 and, in the surface area range of the planar final metal die attach pads 9 associated with the respective UBM layers 5, is limited in size by the outer edges of said UBM layers 5. Furthermore, dummy metal fills 7 adjacent to and closely spaced from said final metal die attach pads 9 may subsequently be deposited on the substrate so as to reduce parasitic silicon-metal capacitance. Thereby, said dummy metal fills 7, which may e.g. be made of aluminium (In, interconnection layer)) or any other suitable fill-in metal layer, may also be hermetically covered by said passivation layer 6a.
The most important difference in comparison with the semiconductor chip assembly depicted in Fig. 2 consists in that the metal resistor layer lies beneath the under-bump metallization layer such that said metal resistor layer does not protrude over the outer edge of the under-bump metallization layer. In this case, the critical outer edge of the final metal die attach pad is far away from the outer edge of the UBM layer, where - under thermal or mechanical stress - the biggest mechanical forces arise.
In Fig. 4, a simplified CSP layout of an octal D-type transparent latch featuring separate D-type inputs for each latch as well as tri-state outputs for bus- oriented applications as implemented by the 74LV573 - a low-voltage Si-gate CMOS device developed by Philips Semiconductors (product No.: IP 4040) - is shown in a top view as an example for a chip-scale packaged semiconductor integrated circuit. The simplified CSP layout exemplarily comprises an array of 25 interconnected die attach pads which are arranged in a square as well as contacts that are associated with these die attach pads. Moreover, only three different layers are shown, the planar metal die attach pad, the metal resistors as well as the under-bump metallization layer.
APPLICATIONS OF THE PRESENT INVENTION
The present invention can be applied in the field of die bonding technol- ogy, in particular for fabricating chip-scale package type semiconductor chip device assemblies where a small-size layout for the surface area of the planar final metal die attach pad is required, such as e.g. for attaching the Philips Semiconductors 74LV573 integrated circuit or any other semiconductor dies with low parasitic metal-silicon capacitance requirements on a silicon or silicon dioxide substrate.
While the present invention has been illustrated and described in detail in the drawings and in the foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive, which means that the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the disclosure including the accompanying drawings and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures can not be used to advan- tage. A computer program may be stored/distributed on a suitable medium, such as e.g. an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as e.g. via the Internet or other wired or wireless telecommunication systems. Any reference signs in the claims should not be construed as limiting the scope of the invention.

Claims

1. A chip-scale package type semiconductor integrated circuit chip device assembly bonded onto an array of planar metal die attach pad layers (9) on a printed circuit board's substrate (8), wherein said planar metal die attach pad layers (9) are respectively placed beneath a corresponding one from an array of subsequently arranged, spaced under-bump metallization layers (5) associated with said planar metal die attach pad layers (9), said semiconductor chip device assembly being attached to the printed circuit board's substrate (8) by means of an array of solder bumps (3) associated to said planar metal die attach pad layers (9), wherein said planar metal die attach pad layers (9) are placed beneath the under- bump metallization layers (5) associated with these planar metal die attach pad layers (9) in such a way that the die attach pad layers (9) do not protrude over the outer edges of their associated under-bump metallization layers (5).
2. The chip-scale package type semiconductor integrated circuit chip device assembly according to claim 1 , wherein the surface areas of the planar final metal die attach pad layers (9) are smaller in size than those of the corresponding under-bump metallization layers (5) associated with these final metal die attach pads (9).
3. The chip-scale package type semiconductor integrated circuit chip device assembly according to claim 1 , wherein the surface areas of the planar final metal die attach pad layers (9) and those of the corresponding under-bump metallization layers (5) associated with these final metal die attach pads (9) are equal in size.
4. The chip-scale package type semiconductor integrated circuit chip device assembly according to anyone of the preceding claims, wherein the planar metal die attach pad layers (9) of adjacent solder bumps are interconnected by a relatively thin and hard electrically conductive metal lead segment (6b) constituting and being used as a surface-mounted ohmic resistor.
5. The chip-scale package type semiconductor integrated circuit chip device assembly according to anyone of the preceding claims, wherein the electrically conductive metal lead segment (6b) constituting said oh- mic resistor is divided into two separate parts located at both sides of the solder bumps (3) and spaced by a passivation opening (</).
6. The chip-scale package type semiconductor integrated circuit chip device assembly according to anyone of the preceding claims, wherein the electrically conductive metal lead segment (6b) constituting said ohmic resistor goes beneath the under-bump metallization layers (5) and, in the surface area range of the planar final metal die attach pads (9) associated with the respective under-bump metallization layers (5), is limited in size by the outer edges of said under- bump metallization layers (5).
7. The chip-scale package type semiconductor integrated circuit chip device assembly according to anyone of the preceding claims, wherein dummy metal fills (7) adjacent to and closely spaced from said final metal die attach pads (9) are subsequently deposited on the substrate (8).
8. The chip-scale package type semiconductor integrated circuit chip device assembly according to claim 7, wherein said dummy metal fills (7) as well as said die attach pads (9) are hermetically covered by a passivation layer (6a) serving as an anti-oxidation protection.
PCT/IB2008/053093 2007-08-13 2008-08-01 Bond pad arrangement of an integrated circuit WO2009022252A2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111952296A (en) * 2019-05-15 2020-11-17 联发科技股份有限公司 Semiconductor package

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