WO2009022252A3 - Bond pad arrangement of an integrated circuit - Google Patents
Bond pad arrangement of an integrated circuit Download PDFInfo
- Publication number
- WO2009022252A3 WO2009022252A3 PCT/IB2008/053093 IB2008053093W WO2009022252A3 WO 2009022252 A3 WO2009022252 A3 WO 2009022252A3 IB 2008053093 W IB2008053093 W IB 2008053093W WO 2009022252 A3 WO2009022252 A3 WO 2009022252A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- die attach
- metal die
- integrated circuit
- planar
- attach pad
- Prior art date
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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Abstract
The present invention is related to die bonding technology, in particular to a small- size layout for the surface areas of the planar final metal die attach pads (9) in a novel CSP-type semiconductor integrated circuit chip device assembly, wherein each planar final metal die attach pad (9) contained in this assembly layout has a surface area that is smaller in size than those of conventional semiconductor integrated circuit chips that are to be mounted on a printed circuit board's substrate in chip-scale package technology. For applications with a restricted upper tolerable limit for the total capacitance of the integrated circuit, parasitic metal-silicon capacitance, which occurs between each planar final metal die attach pad (9) and the substrate (8), is detrimental. For mechanical robust CSP products, on the other hand, it is a necessary requirement that the planar metal die attach pad area surfaces are larger in size than their associated under-bump metallization (UBM) areas (5). Reducing said parasitic metal-silicon capacitance, which can easily be achieved by using metal die attach pads (9) with smaller surface areas, is very lifetime-critical in cases where metal bonding wires (1) are required and results in that the semiconductor chip device might possibly fail during mechanical stress. A significant problem concerning the robustness of the assembly are the edges of the under-bump metallization areas (5), which is because there are usually high stress forces along these edges during the lifetime of said chip-scale packaged semiconductor chip device assembly. The present invention therefore proposes a chip-scale packaged semiconductor chip device assembly bonded onto planar final metal die attach pad layers (9) on a printed circuit board (8) by means of solder bumps, wherein the surface areas of the planar final metal die attach pad layers (9) are smaller in size than their associated under-bump metallization layers (5). For die-to-die bond wiring, very thin and hard electrically conductive materials are proposed which - according to a refinement of the present invention - may be used as surface-mounted ohmic resistors. In this case, the mechanical stability of the bump-chip connection is still given, and, at the same time, parasitic metal-silicon capacitances of the die attach pads to the substrate are reduced.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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EP07114221 | 2007-08-13 | ||
EP07114221.0 | 2007-08-13 |
Publications (2)
Publication Number | Publication Date |
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WO2009022252A2 WO2009022252A2 (en) | 2009-02-19 |
WO2009022252A3 true WO2009022252A3 (en) | 2009-04-09 |
Family
ID=40193803
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/IB2008/053093 WO2009022252A2 (en) | 2007-08-13 | 2008-08-01 | Bond pad arrangement of an integrated circuit |
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WO (1) | WO2009022252A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US11508707B2 (en) * | 2019-05-15 | 2022-11-22 | Mediatek Inc. | Semiconductor package with dummy MIM capacitor die |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6118180A (en) * | 1997-11-03 | 2000-09-12 | Lsi Logic Corporation | Semiconductor die metal layout for flip chip packaging |
US20020131254A1 (en) * | 1998-10-22 | 2002-09-19 | Schaper Leonard W. | Surface applied passives |
US20040007778A1 (en) * | 2000-12-18 | 2004-01-15 | Masao Shinozaki | Semiconductor integrated circuit device |
US20060205200A1 (en) * | 2005-03-08 | 2006-09-14 | Dominick Richiuso | Low capacitance solder bump interface structure |
US20060291174A1 (en) * | 2005-06-28 | 2006-12-28 | Myat Myitzu S | Embedding thin film resistors in substrates in power delivery networks |
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2008
- 2008-08-01 WO PCT/IB2008/053093 patent/WO2009022252A2/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6118180A (en) * | 1997-11-03 | 2000-09-12 | Lsi Logic Corporation | Semiconductor die metal layout for flip chip packaging |
US20020131254A1 (en) * | 1998-10-22 | 2002-09-19 | Schaper Leonard W. | Surface applied passives |
US20040007778A1 (en) * | 2000-12-18 | 2004-01-15 | Masao Shinozaki | Semiconductor integrated circuit device |
US20060205200A1 (en) * | 2005-03-08 | 2006-09-14 | Dominick Richiuso | Low capacitance solder bump interface structure |
US20060291174A1 (en) * | 2005-06-28 | 2006-12-28 | Myat Myitzu S | Embedding thin film resistors in substrates in power delivery networks |
Also Published As
Publication number | Publication date |
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WO2009022252A2 (en) | 2009-02-19 |
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