WO2009022252A3 - Bond pad arrangement of an integrated circuit - Google Patents

Bond pad arrangement of an integrated circuit Download PDF

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Publication number
WO2009022252A3
WO2009022252A3 PCT/IB2008/053093 IB2008053093W WO2009022252A3 WO 2009022252 A3 WO2009022252 A3 WO 2009022252A3 IB 2008053093 W IB2008053093 W IB 2008053093W WO 2009022252 A3 WO2009022252 A3 WO 2009022252A3
Authority
WO
WIPO (PCT)
Prior art keywords
die attach
metal
integrated circuit
metal die
size
Prior art date
Application number
PCT/IB2008/053093
Other languages
French (fr)
Other versions
WO2009022252A2 (en
Inventor
Joerg Syre
Original Assignee
Nxp Bv
Joerg Syre
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to EP07114221 priority Critical
Priority to EP07114221.0 priority
Application filed by Nxp Bv, Joerg Syre filed Critical Nxp Bv
Publication of WO2009022252A2 publication Critical patent/WO2009022252A2/en
Publication of WO2009022252A3 publication Critical patent/WO2009022252A3/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
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    • H01BASIC ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
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    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L2924/30105Capacitance

Abstract

The present invention is related to die bonding technology, in particular to a small- size layout for the surface areas of the planar final metal die attach pads (9) in a novel CSP-type semiconductor integrated circuit chip device assembly, wherein each planar final metal die attach pad (9) contained in this assembly layout has a surface area that is smaller in size than those of conventional semiconductor integrated circuit chips that are to be mounted on a printed circuit board's substrate in chip-scale package technology. For applications with a restricted upper tolerable limit for the total capacitance of the integrated circuit, parasitic metal-silicon capacitance, which occurs between each planar final metal die attach pad (9) and the substrate (8), is detrimental. For mechanical robust CSP products, on the other hand, it is a necessary requirement that the planar metal die attach pad area surfaces are larger in size than their associated under-bump metallization (UBM) areas (5). Reducing said parasitic metal-silicon capacitance, which can easily be achieved by using metal die attach pads (9) with smaller surface areas, is very lifetime-critical in cases where metal bonding wires (1) are required and results in that the semiconductor chip device might possibly fail during mechanical stress. A significant problem concerning the robustness of the assembly are the edges of the under-bump metallization areas (5), which is because there are usually high stress forces along these edges during the lifetime of said chip-scale packaged semiconductor chip device assembly. The present invention therefore proposes a chip-scale packaged semiconductor chip device assembly bonded onto planar final metal die attach pad layers (9) on a printed circuit board (8) by means of solder bumps, wherein the surface areas of the planar final metal die attach pad layers (9) are smaller in size than their associated under-bump metallization layers (5). For die-to-die bond wiring, very thin and hard electrically conductive materials are proposed which - according to a refinement of the present invention - may be used as surface-mounted ohmic resistors. In this case, the mechanical stability of the bump-chip connection is still given, and, at the same time, parasitic metal-silicon capacitances of the die attach pads to the substrate are reduced.
PCT/IB2008/053093 2007-08-13 2008-08-01 Bond pad arrangement of an integrated circuit WO2009022252A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP07114221 2007-08-13
EP07114221.0 2007-08-13

Publications (2)

Publication Number Publication Date
WO2009022252A2 WO2009022252A2 (en) 2009-02-19
WO2009022252A3 true WO2009022252A3 (en) 2009-04-09

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PCT/IB2008/053093 WO2009022252A2 (en) 2007-08-13 2008-08-01 Bond pad arrangement of an integrated circuit

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118180A (en) * 1997-11-03 2000-09-12 Lsi Logic Corporation Semiconductor die metal layout for flip chip packaging
US20020131254A1 (en) * 1998-10-22 2002-09-19 Schaper Leonard W. Surface applied passives
US20040007778A1 (en) * 2000-12-18 2004-01-15 Masao Shinozaki Semiconductor integrated circuit device
US20060205200A1 (en) * 2005-03-08 2006-09-14 Dominick Richiuso Low capacitance solder bump interface structure
US20060291174A1 (en) * 2005-06-28 2006-12-28 Myat Myitzu S Embedding thin film resistors in substrates in power delivery networks

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118180A (en) * 1997-11-03 2000-09-12 Lsi Logic Corporation Semiconductor die metal layout for flip chip packaging
US20020131254A1 (en) * 1998-10-22 2002-09-19 Schaper Leonard W. Surface applied passives
US20040007778A1 (en) * 2000-12-18 2004-01-15 Masao Shinozaki Semiconductor integrated circuit device
US20060205200A1 (en) * 2005-03-08 2006-09-14 Dominick Richiuso Low capacitance solder bump interface structure
US20060291174A1 (en) * 2005-06-28 2006-12-28 Myat Myitzu S Embedding thin film resistors in substrates in power delivery networks

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