WO2009014144A1 - 半導体基板の製造方法 - Google Patents

半導体基板の製造方法 Download PDF

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Publication number
WO2009014144A1
WO2009014144A1 PCT/JP2008/063198 JP2008063198W WO2009014144A1 WO 2009014144 A1 WO2009014144 A1 WO 2009014144A1 JP 2008063198 W JP2008063198 W JP 2008063198W WO 2009014144 A1 WO2009014144 A1 WO 2009014144A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor substrate
cleaning
treatment
drying
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/063198
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English (en)
French (fr)
Inventor
Hiroyuki Maruyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to JP2009524497A priority Critical patent/JP4947393B2/ja
Publication of WO2009014144A1 publication Critical patent/WO2009014144A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00Cleaning of wafers, substrates or parts of devices
    • H10P70/10Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H10P70/15Cleaning before device manufacture, i.e. Begin-Of-Line process by wet cleaning only

Landscapes

  • Cleaning Or Drying Semiconductors (AREA)

Abstract

 Fe、Ni、Cr、Cu等の重金属やパーティクルの付着を防止し、かつ液汚れの発生を防止することを可能とした半導体基板の製造方法を提供する。  半導体基板の全面に酸化膜を形成する工程と、前記半導体基板の裏面および側面の酸化膜をレジスト膜でコートする工程と、前記半導体基板を洗浄する洗浄工程と、前記洗浄工程を経た半導体基板の表面に気相成長法によりエピタキシャル層を成長させる工程と、を含む半導体基板の製造方法であって、前記洗浄工程が、界面活性剤を添加したバッファードフッ酸により前記半導体基板表面酸化膜を除去する処理と、前記半導体基板を乾燥させることなく硫酸過酸化水素洗浄により該半導体基板裏面レジスト膜を除去する処理と、前記半導体基板を乾燥させずに該半導体基板に対してSC-1洗浄を行う処理と、前記半導体基板を乾燥する処理と、を有するようにした。
PCT/JP2008/063198 2007-07-24 2008-07-23 半導体基板の製造方法 Ceased WO2009014144A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009524497A JP4947393B2 (ja) 2007-07-24 2008-07-23 半導体基板の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-192235 2007-07-24
JP2007192235 2007-07-24

Publications (1)

Publication Number Publication Date
WO2009014144A1 true WO2009014144A1 (ja) 2009-01-29

Family

ID=40281393

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/063198 Ceased WO2009014144A1 (ja) 2007-07-24 2008-07-23 半導体基板の製造方法

Country Status (2)

Country Link
JP (1) JP4947393B2 (ja)
WO (1) WO2009014144A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9831088B2 (en) 2010-10-06 2017-11-28 Entegris, Inc. Composition and process for selectively etching metal nitrides

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5895819A (ja) * 1981-12-02 1983-06-07 Toshiba Corp 半導体ウエ−ハ
JPH0737796A (ja) * 1993-07-17 1995-02-07 Shin Etsu Handotai Co Ltd 半導体基板の製造方法及びその装置
JPH08264500A (ja) * 1995-03-27 1996-10-11 Sony Corp 基板の洗浄方法
JPH1187281A (ja) * 1997-09-08 1999-03-30 Shin Etsu Handotai Co Ltd シリコンウエーハの洗浄方法
WO2005095567A1 (en) * 2004-03-03 2005-10-13 3M Innovative Properties Company Fluorinated sulfonamide surfactants for aqueous cleaning solutions

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5895819A (ja) * 1981-12-02 1983-06-07 Toshiba Corp 半導体ウエ−ハ
JPH0737796A (ja) * 1993-07-17 1995-02-07 Shin Etsu Handotai Co Ltd 半導体基板の製造方法及びその装置
JPH08264500A (ja) * 1995-03-27 1996-10-11 Sony Corp 基板の洗浄方法
JPH1187281A (ja) * 1997-09-08 1999-03-30 Shin Etsu Handotai Co Ltd シリコンウエーハの洗浄方法
WO2005095567A1 (en) * 2004-03-03 2005-10-13 3M Innovative Properties Company Fluorinated sulfonamide surfactants for aqueous cleaning solutions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9831088B2 (en) 2010-10-06 2017-11-28 Entegris, Inc. Composition and process for selectively etching metal nitrides

Also Published As

Publication number Publication date
JPWO2009014144A1 (ja) 2010-10-07
JP4947393B2 (ja) 2012-06-06

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