WO2009010457A2 - Fentes d'extension destinées à réduire les contraintes thermomécaniques d'une connexion électrique - Google Patents

Fentes d'extension destinées à réduire les contraintes thermomécaniques d'une connexion électrique Download PDF

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Publication number
WO2009010457A2
WO2009010457A2 PCT/EP2008/059058 EP2008059058W WO2009010457A2 WO 2009010457 A2 WO2009010457 A2 WO 2009010457A2 EP 2008059058 W EP2008059058 W EP 2008059058W WO 2009010457 A2 WO2009010457 A2 WO 2009010457A2
Authority
WO
WIPO (PCT)
Prior art keywords
contact surface
substrate
insulating layer
conductor track
insulating
Prior art date
Application number
PCT/EP2008/059058
Other languages
German (de)
English (en)
Other versions
WO2009010457A3 (fr
Inventor
Herbert Schwarzbauer
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO2009010457A2 publication Critical patent/WO2009010457A2/fr
Publication of WO2009010457A3 publication Critical patent/WO2009010457A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Definitions

  • the invention relates to an arrangement and a method for contacting at least one electrical contact surface.
  • a method for contacting electrical contact surfaces on the surface of a substrate in which an insulating film of electrically insulating plastic material is laminated to the surface of the substrate, the contact surfaces on the surface of the substrate by opening windows in the Isolati - Onsfolie be exposed, and thus exposed contact surfaces are contacted with a flat conductor track.
  • a circuit for high electrical power including its components and electrical connections in operation a
  • the object on which the invention is based is to specify a method and an arrangement for making contact with at least one electrical contact surface, in which the thermo-mechanical stress of a conductor track and of a conductor under the conductor terbahn lying insulation layer and the associated risk of failure of the insulation layer is reduced.
  • the arrangement according to the invention for contacting at least one electrical contact surface on a surface of a substrate has an insulation layer which is applied to the surface of the substrate.
  • the insulation layer leaves the contact surface free.
  • the contact surface is contacted with a flat conductor track.
  • the conductor track has at least one expansion slot.
  • an insulating layer is applied to the surface of the substrate such that the contact surface to be contacted remains free.
  • the contact surface is then contacted with a flat conductor track.
  • the planar conductor has at least one Dehnschlitz.
  • the Dehnschlitz is a recess in the conductor track.
  • the expansion slot is ensured that the underlying insulating layer compensates for thermal expansion by a lower mechanical displacement and / or mechanical deformation in the direction of Dehnschlitzes. This reduces the thermomechanical load both in the insulation layer and in the overlying conductor track. As a result, cracking and delamination are advantageously avoided.
  • the substrate is, for example, a ceramic substrate.
  • the contact surface can be a partial surface of the substrate itself, for example a part of the conductive surface layer or a contact surface of a component facing away from the substrate, which is applied to the substrate, for example a power-electronic component.
  • the track is a layer of conductive material. For example, it may be copper, but other metals, alloys or non-metals are also possible.
  • At least one insulating film of an insulating plastic material laminated to the substrate is used as the insulating layer.
  • the Dehnschlitz is provided in the immediate vicinity of the contact surface or the window.
  • the thermo-mechanical load which is the highest for windows or vias, is reduced exactly there.
  • the Dehnschlitz is formed parallel to the direction of the current flow.
  • the deviation of the direction of the Dehnschlitzes from that of the current flow is less than 30 ° or in a particular embodiment less than 5 °. This ensures that the line cross-section of the planar conductor is not unnecessarily restricted, i. that the electrical resistance of the Dehnschlitzes remains as low as possible.
  • the thickness of the insulating layer is preferably used as the width of the expansion slot. In one embodiment, the width of the Dehnschlitzes deviates by no more than 20% of the thickness of the insulating layer.
  • the width of the resulting conductor web webs ie as a distance from adjacent expansion slots, preferably four to six times the film thickness used.
  • the width of webs of the conductor track which remain adjacent to the Dehnschlitz, between four and six times the thickness of the insulating layer.
  • the width may also be less than four times the thickness of the insulation layer.
  • the Dehnschlitz reduces the width of the conductor, thus reducing the Stromleitense the conductor.
  • the least possible restriction of the current conductivity is desirable, i. the widest possible width of webs of the conductor track.
  • the width of the lands determines how far the insulating layer must deform under the influence of thermal expansion, i. under which thermomechanical load the film is. The narrower the webs, the lower the thermomechanical load. According to the above embodiments, the best possible compromise is achieved when the lands are roughly five times as wide as the thickness of the insulating layer.
  • the method and the arrangement for contacting the contact surface can be used in small structures in which, as described, an expansion slot in a conductor track is used.
  • a more complex electronic circuit for example also with power electronic components.
  • Such a circuit then has a plurality of components applied to the substrate with a plurality of contact surfaces - also per component more contact surfaces - on.
  • the insulation layer is open in several places to allow contacting of the contact surfaces. It can be used in such a case, a plurality of flat conductor tracks, which are not in direct electrical contact and part of which may also have multiple Dehnschlitze. Further advantages and details of the invention will be explained with reference to an embodiment shown in the drawing. Showing:
  • Figure 1 shows an electronic structure in side view
  • Figure 2 shows the electronic structure in supervision.
  • the embodiment of the invention shown in the drawing is based on a ceramic substrate 7, which is covered with a lower conductor track 6, consisting of copper. On the lower conductor 6, a chip 1 is applied.
  • the chip 1 may be any electronic or power electronic device.
  • the chip 1 is a power electronic device, i. a component that processes more than 10 W of electrical power.
  • the exemplary structure further comprises an insulation film
  • the insulating film 2 is used for electrical I-solation of the lower conductor 6 of other structures and is about half a millimeter thick. In order to allow an electrical contacting of the chip 1 from above, a window is opened in the insulating film 2 on the chip 1.
  • a copper trace 3 passes over the chip 1 from one side of the chip 1 to its other side.
  • the copper conductor track 3 thus covers part of the insulating film 2. In this exemplary embodiment, it completely covers the window which has been opened in the insulating film 2 on the chip 1. Since the copper conductor 3 touches the chip 1 through the window, a through-connection 5 is formed in the region of the window.
  • the expansion slots 4 thereby represent a recess in the copper conductor 3.
  • two expansion slots 4 are provided on each side of the feedthrough.
  • the stretching slots 4 intersect the edges of the chip 1.
  • the stretching slots 4 are rectangular in this example, with their width being 500 ⁇ m and their length being 4 mm. They are aligned parallel to the direction of current flow in the copper conductor 3 according to their elongated shape.
  • the distance of the two Dehnschlitze 4, which are present on each of the sides of the feedthrough 5, is about 2 mm. Since the thickness of the insulation film 4 in this exemplary embodiment is about 500 ⁇ m, the width of the expansion slots 4 corresponds approximately to the thickness of the insulation film 2, while the distance between the expansion slots 4 is about four times this thickness.
  • Copper conductor 3 of about 7 mm through the two expansion slots has a width of about 6 mm.
  • the current conductivity of the copper conductor 3 past the Dehnschlitzen 4 is thus reduced by about 15%.
  • the maximum width of the copper conductor track 3 in the region of the stretch slots 4 of 7 mm, ie the total width is reduced to 2 mm since the stretch slots 4 divide the remaining 6 mm width into three approximately equal parts.
  • the deformation of the insulating film 2 and thus the thermomechanical load is now no longer given by the expansion slots 4 to a width of the copper conductor 3 of 7 mm, but only 2 mm.
  • the thermomechanical load is thus considerably reduced by the exemplary arrangement, while the current conductivity of the copper conductor is limited only to a lesser extent.
  • the components of the circuit such as the chip 1, the copper wiring 3, etc., are heated by the electric power converted or guided in the chip 1.
  • the heating ensures thermal expansion of the individual components.
  • the insulating film 2 selected in this exemplary embodiment has a high thermal expansion coefficient, ie it expands when heated. especially strong. Due to the difference in the thermal expansion between the insulating film 2 and the copper conductor 3, a high mechanical stress is generated between them.
  • This special thermo-mechanical load occurring in the region of the plated-through hole 5 is now advantageously mitigated by the stretched slots 4 which are provided in the immediate vicinity of the plated-through hole 5. Cracks in the insulating film 2 are thereby avoided. This in turn increases the life of the circuit.
  • the given embodiment has only one chip 1 with a contact surface. It is clear that real exemplary embodiments can have a plurality of chips 1, each of which - apart from underlying contact surfaces which are contacted with the lower conductor track 6 - can have none, one or more contact surfaces which contact one another from above in the manner described become. In this case, a plurality of windows in the insulating film 2 and also a plurality of separate copper conductor tracks 3 may be necessary. The copper conductors can cover the windows completely or only partially. It is also possible, for example, to use only a single expansion slot 4 in the case of a narrow copper conductor 3. The expansion slots also need not necessarily all be provided in the immediate vicinity of the vias 5.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structure Of Printed Boards (AREA)
  • Multi-Conductor Connections (AREA)

Abstract

Selon l'invention, pour réduire les contraintes thermomécaniques exercées sur un empilement de couches comprenant un film d'isolement et une piste conductrice superficielle, des fentes d'extension allongées sont ménagées dans la piste conductrice à proximité des connexions transversales à travers le film d'isolement.
PCT/EP2008/059058 2007-07-18 2008-07-11 Fentes d'extension destinées à réduire les contraintes thermomécaniques d'une connexion électrique WO2009010457A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102007033465A DE102007033465A1 (de) 2007-07-18 2007-07-18 Dehnschlitze zur thermomechanischen Entlastung einer elektrischen Kontaktierung
DE102007033465.8 2007-07-18

Publications (2)

Publication Number Publication Date
WO2009010457A2 true WO2009010457A2 (fr) 2009-01-22
WO2009010457A3 WO2009010457A3 (fr) 2009-04-30

Family

ID=40101316

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2008/059058 WO2009010457A2 (fr) 2007-07-18 2008-07-11 Fentes d'extension destinées à réduire les contraintes thermomécaniques d'une connexion électrique

Country Status (2)

Country Link
DE (1) DE102007033465A1 (fr)
WO (1) WO2009010457A2 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216280A (en) * 1989-12-02 1993-06-01 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having pads at periphery of semiconductor chip
DE4228274A1 (de) * 1992-08-26 1994-03-03 Siemens Ag Verfahren zur Kontaktierung von auf einem Träger angeordneten elektronischen oder optoelektronischen Bauelementen
EP0880179A2 (fr) * 1997-05-20 1998-11-25 Fujitsu Limited Configuration d'ouvertures d'échappement pour structures conducteur-dielectrique multicouches
US6483714B1 (en) * 1999-02-24 2002-11-19 Kyocera Corporation Multilayered wiring board
WO2003030247A2 (fr) * 2001-09-28 2003-04-10 Siemens Aktiengesellschaft Procede d'etablissement de contact pour des surfaces de contact electriques situees sur un substrat et dispositif constitue d'un substrat pourvu de surfaces de contact electriques

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6127727A (en) * 1998-04-06 2000-10-03 Delco Electronics Corp. Semiconductor substrate subassembly with alignment and stress relief features
US6593527B1 (en) * 2002-04-17 2003-07-15 Delphi Technologies, Inc. Integrated circuit assembly with bar bond attachment
US7038308B2 (en) * 2004-08-17 2006-05-02 Delphi Technologies, Inc. Multi-path bar bond connector for an integrated circuit assembly

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216280A (en) * 1989-12-02 1993-06-01 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having pads at periphery of semiconductor chip
DE4228274A1 (de) * 1992-08-26 1994-03-03 Siemens Ag Verfahren zur Kontaktierung von auf einem Träger angeordneten elektronischen oder optoelektronischen Bauelementen
EP0880179A2 (fr) * 1997-05-20 1998-11-25 Fujitsu Limited Configuration d'ouvertures d'échappement pour structures conducteur-dielectrique multicouches
US6483714B1 (en) * 1999-02-24 2002-11-19 Kyocera Corporation Multilayered wiring board
WO2003030247A2 (fr) * 2001-09-28 2003-04-10 Siemens Aktiengesellschaft Procede d'etablissement de contact pour des surfaces de contact electriques situees sur un substrat et dispositif constitue d'un substrat pourvu de surfaces de contact electriques

Also Published As

Publication number Publication date
DE102007033465A1 (de) 2009-01-22
WO2009010457A3 (fr) 2009-04-30

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