WO2009009612A2 - Étirement de nanofils de gan auto-assemblés et application dans un matériau en vrac semi-conducteur de nitrure - Google Patents

Étirement de nanofils de gan auto-assemblés et application dans un matériau en vrac semi-conducteur de nitrure Download PDF

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WO2009009612A2
WO2009009612A2 PCT/US2008/069552 US2008069552W WO2009009612A2 WO 2009009612 A2 WO2009009612 A2 WO 2009009612A2 US 2008069552 W US2008069552 W US 2008069552W WO 2009009612 A2 WO2009009612 A2 WO 2009009612A2
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group iii
nitride semiconductor
growth
nanowire
quantum dot
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WO2009009612A3 (fr
WO2009009612A9 (fr
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Lei Zhang
Petros M. Varangis
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Nanocrystal, Llc
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Definitions

  • This invention relates generally to Group III nitride semiconductor materials, devices, and methods for their manufacture and, more particularly, relates to Group III nitride semiconductor nanowires and Group III nitride semiconductor nanowire active devices.
  • Group III nitride semiconductors include gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN) and indium gallium nitride (InGaN).
  • Group III nitride semiconductor devices including blue/UV light emitting diodes (LEDs), laser diodes (LDs), and high-power, high speed, high-temperature transistors, have evolved into a multibillion-dollar industry. Due to a lack of Group III nitride bulk single crystal substrates, currently, commercial Group III nitride semiconductor device manufacturing and development relies on Group III nitride epi layers grown on foreign substrates such as sapphire, SiC and Si. Sapphire is the most widely used substrate for Group III nitride device fabrication due to its physical and chemical stability, inexpensiveness and mass manufacturability.
  • III nitride semiconductor device fabrication have large mismatch of lattice constant and coefficient of thermal expansion with respect to group III nitride semiconductors. Because of the large mismatch of lattice constant and coefficient of thermal expansion between GaN and the foreign substrate, the GaN epi-layers grown on these substrates exhibit large density of defects, with threading dislocations (TDs) being the most prevalent (typically, 10 9 - 10 11 TDs/cm 2 ). Such a large density of dislocations in GaN drastically limits the performance and operating lifetime of these nitride-based devices.
  • TDs threading dislocations
  • the nanowire coalescence method has the potential to produce high quality GaN substrates at significantly reduced cost compared to the ELO method and the facet growth methods.
  • This proposed approach is shown in Fig. 1 :
  • the process starts with a high dislocation density GaN underlayer on top of a foreign substrate, namely sapphire, SiC, or Si.
  • a thin layer of dielectric growth mask is deposited on top of the GaN underlayer and patterned into a 2 -D array of nanoscale growth windows.
  • Pulsed MOCVD growth method is applied.
  • the window openings serve as the seeds for GaN nanowire growth.
  • the nano wires grow only upwards with no lateral growth.
  • nano wires achieve a desired height, pulsed MOCVD growth stops and coalescence MOCVD growth starts.
  • the nano wires grow both upwards and laterally until each of the nanowires is joined to its neighboring nanowires and all nanowires are combined into an integral GaN epi film.
  • NHE nano-hetero- epitaxy
  • Self-assembled quantum dots are well-suited as seeds for small pitch, uniform nanowires across large wafers.
  • High quality self-assembled InAs QDs on GaAs substrates for various QD-based laser diodes have been demonstrated by various companies (e.g., Zia Laser, Inc. in U.S. Patents 6,816,525; 6,600,169 and 6,782,021) and many other research institutes.
  • GaN QDs can be formed on foreign substrates, including Si, SiC, and sapphire, through judicious selection of the growth conditions.
  • the growth condition is switched to pulsed MOCVD mode to form high density small pitch GaN nanowires from the QD seeds.
  • the growth condition is switched to coalescence MOCVD mode and a high quality GaN epi layer is formed through the coalescence of the GaN nanowires.
  • Fig. 1 depicts a cross-sectional view of low dislocation density GaN epi films obtained by coalescing nitride semiconductor nanowires grown on GaN underlayer with dielectric masks pre-defined by nanoscale lithographic patterning.
  • FIG. 2 depicts cross-sectional views of an exemplary process flow for obtaining a low dislocation density GaN epi films by coalescing self-assembled nitride semiconductor nanowires directly on a foreign substrate without any dielectric growth mask, in accordance with the present teachings.
  • Fig. 3 depicts exemplary growth parameters for forming a high quality GaN epi film by coalescing a plurality of self-assembled nanowires and/or nanowire arrays using a three-phase growth mode, in accordance with the present teachings.
  • Figs. 4-8 depict exemplary embodiments for nanowire active devices including nanowire LEDs and nanowire lasers, and exemplary processes for manufacturing. DESCRIPTION OF THE EMBODIMENTS
  • Exemplary embodiments provide semiconductor devices including high- quality (preferably, defect free) group III -N nanowires and substantially uniform group III -N nanowire arrays as well as scalable processes for their manufacturing, where the position, orientation, cross-sectional features, length and/or the crystallinity of each nanowire can be sufficiently controlled.
  • a plurality of nano wires and/or nanowire arrays can be formed using a QD growth mode, followed by a growth-mode- transition from the QD growth mode to a pulsed growth mode.
  • the cross-sectional features for example, the cross-sectional dimensions (e.g., diameter or width), and the cross-sectional shapes, of each nanowire obtained from the QD growth mode can be maintained by continuing the growth using the pulsed growth mode. In this manner, nanowires with a high aspect ratio can be formed.
  • the length of each nanowire can be, for example, about 10 nm to about 20 Dm, or more.
  • high-quality group III-N films for example, high-quality GaN films
  • These GaN films can be used as GaN substrate structures to facilitate the fabrication of visible LEDs and lasers for the emerging solid-state lighting and UV sensor industries.
  • nanowire generally refers to any elongated conductive or semiconductive material that includes at least one minor dimension, for example, at least one of the cross-sectional dimensions such as width or diameter, of less than or equal to about 500 nm.
  • the minor dimension(s) can be less than about 100 nm. In various other embodiments, the minor dimension(s) can be less than about 30 nm.
  • the nanowires can have an aspect ratio (e.g., length: width and/or major dimension: minor dimension) of about 30 or greater. In various embodiments, the aspect ratio can be about 100 or greater. In various other embodiments, the aspect ratio can be about 150 or greater.
  • nanowires also encompass other elongated structures of like dimensions including, but not limited to, nano shafts, nanopillars, nanoneedles, nanorods, and nanotubes (e.g., single wall nanotubes, or multiwall nanotubes), and their various functionalized and derivatized fibril forms, such as nanofibers in the form of thread, yarn, fabrics, etc.
  • the nanowires can have various cross-sectional shapes, such as, for example, rectangular, polygonal, square, oval, or circular shape. Accordingly, the nanowires can have cylindrical and/or cone-like three dimensional (3-D) shapes.
  • a plurality of nanowires can be, for example, substantially parallel, arcuate, sinusoidal, etc., with respect to each other.
  • the nanowires can be formed on/from a support, which can include selected surface regions where the nanowires can be connected to and extend (e.g., be grown) from.
  • the support of the nanowires can also include a substrate formed from a variety of materials including Si, SiC, sapphire, III-V semiconductor compounds such as GaN or GaAs, metals, ceramics or glass.
  • nanowire active devices for example, nanowire
  • the nanowires and/or nanowire arrays and the nanowire active devices can be formed using a III-V compound semiconductor materials system, for example, the group Ill-nitride (N) compound materials system.
  • the group III elements can include Ga, In, or Al, which can be formed from exemplary group III precursors, such as trimethylgallium (TMGa) or triethylgallium (TEGa), trimethylindium (TMIn) or trimethylaluminum (TMAl).
  • exemplary N precursors can be, for example, ammonia (NH 3 ).
  • Other group V elements can also be used, for example, P or As, with exemplary group V precursors, such as tertiarybutylphoshine (TBP), or arsine (AsH 3 ).
  • group III-N semiconductor alloy compositions can be described by the combination of group III-N elements, such as, for example, GaN, AlN, InN, InGaN, AlGaN, or AlInGaN.
  • group III-N elements such as, for example, GaN, AlN, InN, InGaN, AlGaN, or AlInGaN.
  • the elements in a composition can be combined with various molar fractions.
  • the semiconductor alloy composition InGaN can stand for In x Ga; _ ⁇ N, where the molar fraction, x, can be any number less than 1.00.
  • various active devices can be made by similar compositions.
  • an Ino 3Gao 7N (where x is about 0.3) can be used in the MQW active region of LEDs for a blue emission
  • an Ino 43G ⁇ 057H (where x is about 0.43) can be used in the MQW active region of LEDs for a green emission.
  • the nanowires, nanowire arrays, and/or the nanowire active devices can include a dopant from a group consisting of: a p-type dopant from Group III of the periodic table, for example B, Al and In; an n-type dopant from Group V of the periodic table, for example, P, As and Sb; a p-type dopant from Group II of the periodic table, for example, Mg, Zn, Cd and Hg; a p-type dopant from Group IV of the periodic table, for example, C; or an n-type dopant selected from a group consisting of: Si, Ge, Sn, S, Se and Te.
  • an n-type dopant from Group V of the periodic table for example, P, As and Sb
  • a p-type dopant from Group II of the periodic table for example,
  • the nano wires and/or nanowire arrays as well as the nanowire active devices can have high-quality heterogeneous structures and be formed by various crystal growth techniques including, but not limited to, metal-organic chemical vapor deposition (MOCVD), molecular-beam epitaxy (MBE), gas source MBE (GSMBE), metal- organic MBE (MOMBE), atomic layer epitaxy (ALE), hydride vapor phase epitaxy (HVPE), or organometallic vapor phase epitaxy (OMVPE).
  • MOCVD metal-organic chemical vapor deposition
  • MBE molecular-beam epitaxy
  • GSMBE gas source MBE
  • MOMBE metal- organic MBE
  • ALE atomic layer epitaxy
  • HVPE hydride vapor phase epitaxy
  • OMVPE organometallic vapor phase epitaxy
  • a multiple-phase growth mode for example, a two- phase growth mode
  • a first phase growth mode such as a quantum dot (QD) growth mode
  • QD quantum dot
  • low temperature standard MOCVD can be used to nucleate and form the QDs with desired size, density, and uniformity.
  • the second phase growth mode can create a close-to-equilibrium growth process to start the growth of nanowires on top of the QDs using QDs as growth seeds and maintain its cross-sectional features (diameter size, density, and uniformity) from the first growth mode, and also provide an arbitrary desired length.
  • the second phase growth mode can be applied by a growth-mode -transition, which can terminate the first phase growth mode.
  • a pulsed growth mode for example, a pulsed MOCVD growth, can be used.
  • the term "pulsed growth mode" refers to a process in which the group III and group V precursor gases are introduced alternately in a crystal growth reactor with a designed sequence.
  • TMGa and NH 3 can be used as the precursors for an exemplary formation of GaN nanowires and/or nanowire arrays and/or GaN nanowire active devices.
  • TMGa and NH 3 can be introduced alternately in a sequence that introduces TMGa with a designed flow rate (e.g., about 10 seem) for a certain period of time (e.g., about 20 seconds) followed by introducing NH 3 with a designed flow rate (e.g., about 1500 seem) for a time period (e.g., about 30 seconds).
  • a designed flow rate e.g., about 10 seem
  • a designed flow rate e.g., about 1500 seem
  • time period e.g., about 30 seconds
  • one or more sequence loops can be conducted (e.g., repeated) for a designed length of each nanowire.
  • the growth rate of each nanowire can be orientation dependent.
  • Self-assembled nitride semiconductor nanowires and/or nanowire arrays can be used to form the base for fabrication of nitride semiconductor nanowire devices.
  • Exemplary embodiments for self-assembled nitride semiconductor nanowires and/or nanowire arrays and their scaleable processes for growth are shown in Figs. 2(l)-2(3) and Fig. 3.
  • Figs. 2(1) and 2(2) depict cross-sectional views of an exemplary process of forming an exemplary nitride semiconductor nanowire device at various stages of fabrication in accordance with the present teachings. It should be readily apparent to one of ordinary skill in the art that the nanowire device depicted in Figs. 2(1) and 2(2) represents a generalized schematic illustration and that other layers/nanowires may be added or existing layers/nanowires may be removed or modified.
  • a nitride semiconductor nanowire device starts with a planar foreign substrate. No dielectric selective growth mask or nanoscale patterning process are needed.
  • the substrate can be any substrate on which a group III-N material can be grown.
  • the substrate can include, but is not limited to, sapphire, silicon carbide, silicon, silicon-on-insulator (SOI), III-V semiconductor compounds such as GaAs, metals, ceramics or glass.
  • various cleaning procedures can be conducted on the device shown in Fig. 2(1) prior to the subsequent growth of the nanowires and/or nanowire arrays.
  • the cleaning processes can include an ex-situ cleaning (i.e., the cleaning is conducted outside the growth reactor) followed by an in-situ cleaning (i.e., the cleaning is conducted within the growth reactor).
  • a substrate can be cleaned by a standard ex-situ cleaning followed by an in-situ cleaning by loading the device into an exemplary MOCVD reactor and heating the device to about 950 0 C for approximately 3 minutes under flowing hydrogen. This hydrogen-reducing-atmosphere can remove undesirable native oxides on the surfaces of the device.
  • the growth sequence of self-assembled nitride semiconductor nanowire formation starts with low temperature QD growth mode. Due to the strain induced by the large lattice mismatch between nitride semiconductor and the substrate, the growth of nitride semiconductor tends to form three-dimensional (3-D) nanoscale structures, these being the QDs, rather than two-dimensional (2-D) planar surfaces.
  • the plurality of QD nuclei can be formed by, for example, a standard low temperature MOCVD process. In this mode, the growth condition is controlled to achieve uniform QDs, in terms of size, density, and uniformity, across the surface of the substrate.
  • the device shown in Fig. 2(1) can be used as a support for nanowires and/or nanowire arrays, which can include a plurality of self-assembled nitride semiconductor QDs on top of the substrate. A plurality of nanowires and/or nanowire arrays can then be grown on top of the plurality of nitride QDs. The size, uniformity, and the density of the QDs can be controlled with judicious selection of the growth conditions. [0042] In Fig.
  • a plurality of nanowires can be formed by continuing the growth of the plurality of QD nuclei by, for example, terminating the QD growth mode and applying a pulsed growth mode, before the plurality of QDs start to merge into each other.
  • the plurality of nanowires can be formed of the same material of the QD nuclei, for example, GaN, AlN, InN, InGaN, AlInGaN, or AlGaN.
  • heterostructures can be formed from each of the plurality of nanowires.
  • n-type and/or p- type dopants can be incorporated into the plurality of nanowires depending on the desired application.
  • each of the plurality of nanowires By transitioning to the pulsed growth mode, features such as cross-sectional shape and dimensions of each of the plurality of nanowires can be preserved until a desired length is reached.
  • the cross-sectional features of the nanowires such as shape and/or dimension, can remain substantially constant, the same or similar as that of the QDs.
  • the length of each nanowire can be on an order of micrometers, for example, about 20 Dm or more.
  • Wafers containing self-assembled nitride semiconductor nanowires grown by 2-phase growth process can be used for making various nitride semiconductor devices, such as LEDs.
  • the growth can also continue into the third-phase growth mode - coalescence growth mode, as shown in Fig. 2(3).
  • the nitride semiconductor nanowires both grow upwards and expend in lateral direction.
  • self- assembled nitride semiconductor nanowires can be coherently unified into a high quality (low dislocation density) GaN epitaxial layer.
  • Such a high quality GaN epitaxial layer can serve as a substrate for homo-epitaxial growth of nitride semiconductor device structures, such as LEDs, LDs, transistors, etc. Since the GaN epitaxial (“epi") film obtained from coalescing nanowires contains considerably fewer (as low as zero) dislocations compared with the conventional GaN-on-sapphire, significantly improved device performance and reliability are expected.
  • Fig. 3 depicts an exemplary process for forming a plurality of nanowires and/or nanowire arrays using the three-phase growth mode in accordance with the present teachings.
  • Fig. 3 illustrates temperature profile and precursor gas flow curves (including a NH3 flow curve and a TMGa flow curve) during a "Low T QD growth" phase for the formation of uniform QD nuclei; a subsequent pulsed growth phase (which includes "Nanowire growth 1 st cycle", “Nanowire growth 2 nd cycle", through “Nanowire growth last cycle") for the formation of the plurality of nanowires on top of the QD nuclei; and a subsequent "Nanowire coalescence growth” phase for the formation of a high quality GaN planar epi film by coalescing the nanowires.
  • the pulsed growth phase can further include a number of pulsed sequence cycles, for example, the "Nanowire growth 1 st cycle", the “Nanowire growth 2 nd cycle”, etc.
  • each of these nanowire growth cycles can be identical to each other. In other embodiments, each of these nanowire growth cycles can also be different from each other.
  • the exemplary GaN QD nuclei can be formed in a MOCVD reactor including the first precursor gas TMGa with a constant flow rate of about 10 seem, the second precursor gas NH 3 with a constant flow rate of about 1500 seem, and growing at low temperature of about 500 0 C or higher. That means, during the QD growth phase, the precursor gases (i.e., TMGa and NH 3 ) can be flowed continuously, not pulsed. Moreover, the group V precursor gas (e.g., TMGa) and group III precursor gas (e.g. NH 3 ) can be introduced simultaneously and the group V / group III ratio can be maintained, for example, at about 50 to about 500.
  • the group V / group III ratio can be maintained at about 150.
  • other reactor conditions for the QD growth phase can include, for example, a reactor pressure of about 100 Torr, and a hydrogen/nitrogen carrier gas mixture having a laminar flow of about 4000 seem.
  • Any suitable MOCVD reactor may be used, such as Veeco TurboDisk model P75 MOCVD reactor in which the substrates are rotated at high speed during deposition.
  • the first precursor gas such as TMGa and the second precursor gas such as NH 3 can be introduced alternately into the growth reactor in a designed sequence, for example, shown as the nanowire growth 1 st cycle.
  • the duration of each alternating step within the pulsed sequence can affect the growth of the nanowires and/or nanowire arrays, which can further be optimized for specific reactor geometries.
  • TMGa in the nanowire growth 1 st cycle, can be introduced with a flow rate of about 10 seem for a certain period of time such as about 20 seconds followed by introducing NH 3 with a flow rate of about 1500 seem for a time period such as about 30 seconds followed by, for example, a 10 second carrier-gas purge (e.g., a mixture of hydrogen/nitrogen) with no precursor gases involved.
  • a 10 second carrier-gas purge e.g., a mixture of hydrogen/nitrogen
  • Other pulse durations may also be used depending on the reactor configurations, such as for example 5-40 seconds for the Group III reactant or precursor gas, 5-40 seconds for the Group V reactant or precursor gas, and 5-25 seconds for the purge gases between each reactant introduction step.
  • the pulsed sequence such as the nanowire growth 1 st cycle can be repeated until a certain length of the GaN nano wires is reached.
  • the nanowire growth 1 st cycle can be repeated as the nanowire growth 2 nd cycle, the nanowire growth 3 rd cycle (not illustrated) and so on.
  • the group V precursor gas e.g., TMGa
  • group III precursor gas e.g. NH 3
  • the group V precursor gas and group III precursor gas e.g. NH 3
  • reactor conditions for the pulsed nanowire growth cycles can include, for example, temperature of about 1015 0 C to about 1060 0 C, reactor pressure of about 100 Torr, and a hydrogen/nitrogen carrier gas mixture having a laminar flow of about 4000 seem.
  • the disclosed growth parameters are exemplary and can vary depending on the specific reactor used.
  • the exemplary uniform GaN nanowires shown in Figure 2 can be of high-quality, that is, with essentially no threading dislocations (TD).
  • the uniform and high-quality GaN nanowires and/or nanowire arrays can be used for fabrication of high-quality GaN substrate structures.
  • GaN substrates can greatly facilitate the fabrication of visible LEDs and lasers for the emerging solid-state lighting and UV sensor industries. Moreover, GaN substrates can also be used in other related applications, such as hi-power RF circuits and devices.
  • GaN substrate structures can be formed by terminating and coalescing the plurality of GaN nanowires using techniques such as nanoheteroepitaxy.
  • Fig. 2(3) depicts exemplary semiconductor devices including GaN substrate formed from the plurality of GaN nanowires.
  • the GaN growth conditions can be modified to allow coalescence of the formed plurality of nanowires after they have grown to a suitable height.
  • the GaN substrate structure can be a continuous, epitaxial, and fully coalesced planar film.
  • the "suitable height" can be determined for each nanowire (e.g., GaN) and substrate (e.g., SiC or Si) combination and can be a height that allows a significant reduction in defect density in the upper coalesced GaN film (i.e., the GaN substrate structure).
  • the "suitable height” can be a height that can maintain a mechanically-robust structure for the resulting semiconductor devices.
  • the coalescence of the GaN substrate structure on top of these pluralities of nano wires can then occur and provide the GaN substrate structure containing an extremely low defect density, such as, for example, about 10 7 defects per square centimeter (cm 2 ) or lower.
  • the process steps can be scaleable to large substrate areas. Since no high density nanoscale growth mask is needed, they can be readily extended to manufacturing requirements including automatic wafer handling and extended to larger size wafers for establishing efficacy of photonic crystals for light extraction from visible and near-UV LEDs.
  • Figs. 4-8 depict exemplary embodiments for nanowire active devices including nanowire LEDs and nanowire lasers, and their scalable processes for manufacturing.
  • the disclosed group III-N nanowires and nanowire arrays such as GaN nanowires and/or nanowire arrays can provide their active devices with unique properties. This is because each pulsed-grown GaN nanowire can have sidewalls of ⁇ 1J . 00 ⁇ family and the normal to each of these side planes can be a nonpolar direction for group III-N materials.
  • High-quality quantum group III-N wells such as quantum InGaN/GaN well, quantum AlGaN/GaN well or other quantum III-N wells, can therefore be formed on these side facets of each GaN nanowire.
  • the nanowire growth behavior can be changed significantly when other precursor gases such as trimethylaluminum (Al) or trimethylindium (In) are added to the exemplary MOCVD gas phase during the pulsed growth mode.
  • other precursor gases such as trimethylaluminum (Al) or trimethylindium (In)
  • Al trimethylaluminum
  • In trimethylindium
  • a small molecular fraction e.g., about 1%) of Al or In added to the GaN nanowires and/or nanowire arrays can result in each GaN nanowire growing laterally with its cross- sectional dimensions (e.g., width or diameter) increasing over time.
  • This lateral growth behavior can allow creation of a core-shell heterostructure, that is, quantum wells including exemplary materials of such as InGaN and AlGaN alloys can be grown on and envelop each GaN nanowire core.
  • the core-shell growth can create a core-shell nanowire/MQW active structure for light emitting devices.
  • an additional growth condition can be established to grow the core-shell of the exemplary InGaN and AlGaN alloys (after the GaN nanowire has been grown using the disclosed pulsed growth phase), which can be a continuous growth, similar to that used for the growth of quantum dots, or pulsed growth mode.
  • the core-shell nanowire/MQW active structure can be used to provide high efficiency nanoscale optoelectronic devices, such as, for example, nanowire LEDs and/or nanowire lasers.
  • the resulting core-shell nanowire/MQW active structure i.e., having the MQW active shell on sidewalls of each nanowire core
  • the elimination of the QCSE can increase the radiative recombination efficiency in the active region to improve the performance of the LEDs and lasers.
  • the absence of QCSE can allow wider quantum wells to be used, which can improve the overlap integral and cavity gain of the nanowire based lasers.
  • a further exemplary efficiency benefit of using the core-shell nanowire/MQW active structure is that the active region area can be significant increased because of the unique core-shell structure.
  • Fig. 4(1) depicts a cross-sectional layered structure of an exemplary core-shell nanowire/MQW active structure device in accordance with the present teachings. It should be readily apparent to one of ordinary skill in the art that the device depicted in Fig. 4(1) represents a generalized schematic illustration and that other materials/layers/shells can be added or existing materials/layers/shells can be removed or modified. [0058] As shown, the device can include a substrate, the quantum dot nucleus
  • n-GaN doped nanowire core
  • n-GaN doped nanowire core
  • a shell structure including a first doped shell (denoted by "Al x Gai_ x N n-cladding"), a MQW shell structure (denoted by "MQW active”), a waveguiding layer (denoted by "GaN waveguide”), a second doped shell (denoted by "Al y Gai_ y N p-cladding”), and a third doped shell (denoted by "p + -GaN cap”).
  • the doped nanowire core can be connected to and extend from the quantum dot nucleus, wherein the doped nanowire core can be isolated from each other by the isolated QD nuclei and subsequent vertical growth of nano wires.
  • the shell structure can be formed to "shell" the doped nanowire core having a core-shell active structure.
  • the shell structure can be formed by depositing the third doped shell over the second doped shell, which can be formed over the MQW shell structure over a first doped shell.
  • the substrate is a conductive substrate including, but not limited to, silicon carbide, silicon and III -V substrates such as GaAs.
  • the doped nanowire core can use any nanowire of the plurality of nano wires formed using the pulsed growth mode.
  • the doped nanowire core can be formed of, for example, GaN, AlN, InN, AlGaN, InGaN or AlInGaN, which can be made an n-type by doping with various impurities such as silicon, germanium, selenium, sulfur and tellurium.
  • the doped nanowire core can be made p-type by introducing beryllium, strontium, barium, zinc, or magnesium. Other dopants known to one of ordinary skill in the art can be used.
  • the height of the doped nanowire core can define the approximate height of the active structure device.
  • the doped nanowire core can have a height of about 0.5 Dm to about 1000 Dm.
  • the doped nanowire core can have non-polar sidewall facets of ⁇ 1100 ⁇ family
  • the shell structure including the MQW shell structure can be grown by core-shell growth on these facets and the device can therefore be free from piezoelectric fields, and free from the associated quantum-confined Stark effect (QCSE).
  • QCSE quantum-confined Stark effect
  • the first doped shell can be formed from and coated on the non-polar sidewall facets of the doped nanowire core by an exemplary core-shell growth, when the pulsed growth mode is used.
  • the first doped shell can be formed by adding a small amount of Al during the pulsed growth of the doped nanowire core forming a core-shell heterostructure.
  • the conductivity type of the first doped shell and the doped nanowire core can be made similar, for example, an n-type.
  • the first doped shell can include a material of Al x Gai_ x N, where x can be any number less than 1.00 such as 0.05 or 0.10.
  • the MQW shell structure can be formed on the first doped shell by the exemplary core-shell growth, when the pulsed growth mode is used. Specifically, the MQW shell structure can be formed by adding a small amount of Al and/or In during the pulsed growth of the first doped shell to continue the formation of the core-shell heterostructure.
  • the MQW shell structure can include, for example, alternating layers of Al x Gai_ x N and GaN where x can be, for example, 0.05 or any other number less than 1.00.
  • the MQW shell structure can also include alternating layers of, for example, In x Gai_ x N and GaN, where x can be any number less than 1.00, for example, any number in a range from about 0.20 to about 0.45.
  • the second doped shell can be formed on the waveguide layer which can be formed on the MQW shell structure.
  • the second doped shell can be used as a barrier layer for the MQW shell structure with a sufficient thickness of, such as, for example, about 500 nm to about 2000 nm.
  • the second doped shell can be formed of, for example, Al x Gai_ x N, where x can be any number less than 1.00 such as 0.20 or 0.30.
  • the second doped shell can be doped with a conductivity type similar to the third doped shell.
  • the third doped shell can be formed by continuing the core-shell growth from the second doped shell to cap the active structure device.
  • the third doped shell can be formed of, for example, GaN and doped to be an n-type or a p-type.
  • the second doped shell and/or the third doped shell can be a p-type shell and vice versa.
  • the third doped shell can have a thickness of about 50 to about 500 nm.
  • Fig. 4(1) can be electrically isolated from each other, when a number of devices are included in a large area such as a wafer.
  • Fig. 4(2) depicts an active structure device including a dielectric material deposited to isolate each core-shell nanowire/MQW active structure shown in Fig. 4(1) in accordance with the present teachings.
  • the dielectric material can be deposited on the substrate and laterally connected with the sidewalls of the shell structure, more specifically, the sidewalls of the third doped shell.
  • the dielectric material can be any dielectric material for electrical isolation, such as, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or other insulating materials.
  • the dielectric material can be a curable dielectric.
  • the dielectric material can be formed by, for example, chemical vapor deposition (CVD) or spin-on techniques, with a desired height or thickness.
  • the height/thickness of the dielectric material can be further adjusted by removing a portion of the dielectric material from the top of the deposited dielectric material using, for example, a etch back process known to one of ordinary skill in the art.
  • the thickness of the dielectric material can be adjusted depending on specific applications where the core-shell nanowire/MQW active structure is used.
  • various nanowire LEDs and nanowire lasers can be formed by the core-shell growth described in Fig. 4, because MQW active shell structures can be created on the nonpolar sidewalls of the pulsed-grown nanowires.
  • a plurality of such nanowire core-shell active structures can be fabricated into individual or connected light emitting devices such as LEDs or laser diodes.
  • Figs. 4(3), 4(4), 5, 6, 7 and 8 depict exemplary nanoscale active devices formed based on the structures in accordance with the present teachings.
  • the nanowire LED device can be fabricated including electrical contacts formed on the device.
  • the electrical contacts can include conductive structures formed from metals such as titanium (Ti), aluminum (Al), platinum (Pt), nickel (Ni) or gold (Au) in a number of multi-layered combinations such as Al/Ti/Pt/Au, Ni/ Au, Ti/ Al, Ti/ Au, Ti/Al/Ti/Au, Ti/ Al/ Au, Al or Au using techniques known to one of ordinary skill in the art.
  • a thin metal layers for example Ni/ Au, is deposited on the entire surface of the wafer to form an p-type ohmic contact to the P + -GaN cap layer.
  • the metal layers preferably are thin enough, for example, 100 angstroms, to be transparent and allow the light generated in the nanowire active region escape from the top.
  • the device can include the n-electrodes (denoted by "n-type ohmic contact”) formed on the bottom surface of the conductive substrate to assure the conduction between the n-side contact and the central conductive nanowire core.
  • the central conductive region can be, for example, a heavily doped n + GaN region.
  • the n-electrodes can include conductive structures formed by depositing electrode materials onto the bottom surface of the n-type substrate after the substrate is thinned to desired thickness and polishing and cleaning.
  • the n-electrodes can be formed of, for example, a layered metal combination. The exact layered metal combination depends on substrate material.
  • a layered metal combination of Al/Ti/Pt/Au can be used to form n-type ohmic contact when n-type Si is used as substrate.
  • the core-shell grown active region area i.e., the MQW active shell area
  • the light extraction can be improved to increase the output efficiency of the LED. This is because the LED device's geometry can make the most of the active region area oriented normal to the wafer surface, i.e., the substrate surface. The confinement regions on either side of the MQW active region can tend to guide the LED light in the vertical direction.
  • the nanowire LED resistance can be significantly decreased because of the increase of the electrical contact area, for example, the contact area of the/?- electrode.
  • a 4-inch diameter wafer can include a number of nanowire LED devices, for example, several hundred thousand devices or more, which can be manufactured simultaneously.
  • Figs. 5-8 depict exemplary nanowire laser devices using the core-shell grown nanowire/MQW active structure shown in Fig. 2(2), 4(1) and 4(2) in accordance with the present teachings.
  • the nanowire laser device can be fabricated from the processes described in Figs. 4(l)-4(4) using the core-shell grown nanowire/MQW active structure as laser active structure.
  • the device shown in Fig. 5 is identical to the one shown in Fig. 4(4), which can be operated as a laser diode.
  • the device includes a plurality of nanowire light emitters.
  • the nanowire core-shell structure of each nanowire light emitter provides the lateral confinement of the optical field.
  • the lasing oscillation cavity is formed between the nanowire-substrate interface (as bottom mirror) and the cap-metal interface (as top mirror). Lasing can be achieved by electrically pumping the device hard enough to reach the threshold condition.
  • Fig. 5 suffers from optical loss due to the absorption as the light passing through the p-ohmic metal.
  • Fig. 6 depicts a core-shell nanowire laser device with the/?-electrode removed on the top end of the core-shell nanowire structure. Still, the nanowire core-shell structure of each nanowire light emitter provides the lateral confinement of the optical field. The lasing oscillation cavity is formed between the nanowire-substrate interface (as bottom mirror) and the cap-air interface (as top mirror). Lasing can be achieved by electrically pumping the device hard enough to reach the threshold condition.
  • Fig. 7 depicts a core-shell nanowire laser device with a bottom distributed
  • the DBR mirror stack can be an epitaxial DBR mirror stack.
  • the DBR mirror stack can include, for example, quarter- wavelength (D /4) thick alternating layers of semiconductor materials with different indices of refraction, for example GaN and AlGaN.
  • the DBR mirror stack can be tuned to improve reflectivity and to increase the cavity Q of the laser.
  • Fig. 8 depicts a core-shell nanowire laser device with a bottom semiconductor
  • the top DBR mirror disposed on top of the nanowire consists of quarter- wave length (D /4) alternating layers of dielectric materials with different indices of refraction, for example, SiO 2 and SiN x .
  • This design can further reduce the optical mirror loss by enhancing the top mirror reflectivity, thus achieving a lower lasing threshold and higher efficiency compared to the device shown in Fig. 7.
  • all the nanowire active devices shown in Figs. 5-8 can provide a low device resistance because more resistive / ⁇ -electrodes of the heterostructure can be located at the larger-area, which is the outer periphery of each core-shell nanowire/MQW active structure.

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Abstract

Selon cette invention, des points quantiques auto-assemblés sont tout à fait appropriés comme germes cristallins pour des nanofils uniformes de petit pas formés dans de grandes plaquettes. Selon une forme d'exécution, après la formation des points quantiques de GaN, l'état d'étirement passe à un mode MOCVD pulsé de façon à former des nanofils de GaN de petit pas et de haute densité à partir des germes cristallins des points quantiques. Une fois que les nanofils de GaN ont atteint une hauteur désirée, l'état d'étirement passe à un mode MOCVD de coalescence et une couche de GaN epi de haute qualité est formée par la coalescence des nanofils de GaN.
PCT/US2008/069552 2007-07-09 2008-07-09 Étirement de nanofils de gan auto-assemblés et application dans un matériau en vrac semi-conducteur de nitrure WO2009009612A2 (fr)

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Publication number Priority date Publication date Assignee Title
WO2011160051A2 (fr) 2010-06-18 2011-12-22 Glo Ab Structure à diodes électroluminescentes de nanofils et procédé de fabrication associé
WO2013034485A1 (fr) * 2011-09-07 2013-03-14 Osram Opto Semiconductors Gmbh Composant optoélectronique
WO2013127672A1 (fr) * 2012-03-01 2013-09-06 Osram Opto Semiconductors Gmbh Puce semi-conductrice optoélectronique
WO2014064220A1 (fr) * 2012-10-26 2014-05-01 Commissariat à l'énergie atomique et aux énergies alternatives Procede de fabrication d'une structure semiconductrice
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6656573B2 (en) * 2001-06-26 2003-12-02 Hewlett-Packard Development Company, L.P. Method to grow self-assembled epitaxial nanowires
US20050082543A1 (en) * 2003-10-15 2005-04-21 Azar Alizadeh Monolithic light emitting devices based on wide bandgap semiconductor nanostructures and methods for making same
US20050161662A1 (en) * 2001-03-30 2005-07-28 Arun Majumdar Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050161662A1 (en) * 2001-03-30 2005-07-28 Arun Majumdar Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
US6656573B2 (en) * 2001-06-26 2003-12-02 Hewlett-Packard Development Company, L.P. Method to grow self-assembled epitaxial nanowires
US20050082543A1 (en) * 2003-10-15 2005-04-21 Azar Alizadeh Monolithic light emitting devices based on wide bandgap semiconductor nanostructures and methods for making same

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