WO2009006818A1 - Procede et equipement de formation de trames de donnees - Google Patents

Procede et equipement de formation de trames de donnees Download PDF

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Publication number
WO2009006818A1
WO2009006818A1 PCT/CN2008/071449 CN2008071449W WO2009006818A1 WO 2009006818 A1 WO2009006818 A1 WO 2009006818A1 CN 2008071449 W CN2008071449 W CN 2008071449W WO 2009006818 A1 WO2009006818 A1 WO 2009006818A1
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WO
WIPO (PCT)
Prior art keywords
check
block
blocks
data
partial
Prior art date
Application number
PCT/CN2008/071449
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English (en)
Chinese (zh)
Inventor
Weiguang Liang
Dongyu Geng
Dongning Feng
Effenberger Frank
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Huawei Technologies Co., Ltd.
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Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of WO2009006818A1 publication Critical patent/WO2009006818A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/33—Synchronisation based on error coding or decoding
    • H03M13/333—Synchronisation on a multi-bit block basis, e.g. frame synchronisation

Definitions

  • the present invention relates to the field of communications, and more particularly to data framing techniques. Background technique
  • the basic working principle of the FEC in the EPON system is to add an FEC check code word after the Ethernet frame transmitted by the sender, and the check code words and the verified Ethernet frame data are mutually determined according to certain rules. Association (constraints), the receiving end checks the relationship between the Ethernet frame data and the check codeword according to the established rules. Once an error occurs in the transmission, the relationship is destroyed, thereby realizing the error correction function of the Ethernet frame data.
  • FEC technology strives to correct as many errors as possible with as few check bytes as possible, in overhead (increased overhead caused by check bytes) and the gain of coding gain Find the best balance between the two.
  • a line coding technique In the EPON system, in order to make the transmitted data a format that the receiver can receive, before using the FEC technology, a line coding technique is required, and the line coding must also ensure that the transmitted data has sufficient switching (ie, 0, 1 The transition between the two is to ensure that the receiver can recover the clock.
  • a more efficient coding scheme such as 64B/66B has been used in the Physical Coding Sublayer (PCS).
  • PCS Physical Coding Sublayer
  • the 64B/66B line coding mechanism is based on 64-bit information, adding two distinct bit synchronization characters ("01" or "10") as a synchronization header (called a data synchronization header) to form a 66-bit line coding.
  • Blocks that is, each block contains 64 bits of information data and its 2-bit data sync header.
  • the data block sync header is "01” (or “10"), indicating that 64-bit information is all data; “10” (or “01”) means that 64-bit information contains data and control information; "00" or "11” indicates that an error occurred during the transfer.
  • FEC encoding is performed when the number of data blocks encoded by the 64/66b line reaches the data length required by the FEC encoding.
  • check sync header a sync header of the check information block
  • Each parity block includes 64 bits of parity information and its 2-bit parity sync header.
  • FIG. 1 An information frame (ie, FEC frame) structure for the PCS layer in the 10GEPON system is shown in FIG. 1 .
  • a complete FEC frame consists of a data block and a check block. The data block is located in front of the FEC frame, and the check block is located behind the FEC frame. Since each 66-bit data block contains a 2-bit data synchronization header, the 2-bit data synchronization headers are always different, and each 66-bit parity block contains a 2-bit parity synchronization header, which is 2 bits. The check sync headers are always the same, so this information can be used to synchronize the data block and the check block at the receiving end, thereby facilitating FEC decoding and line decoding.
  • the inventors of the present invention have found that since the data sync header is irregular in an FEC frame, it may be "01" or "10", which is determined by the type of the transmitted data, and the check sync header is It is defined according to the prior agreement, that is, the system knows whether the check sync header of a certain check block in this FEC frame is "00" or "11". However, in the transmission process, there is noise interference, etc., the data synchronization header in the data block may change from the original "01” or “10” to "00” or "11", and the system will misjudge it as a parity block.
  • the sync header is checked; the check sync header of the check block may also have an error, which is misjudged by the system as the data sync header of the data block. Therefore, in the case of a misjudgment of the system, error synchronization may occur.
  • Figure 2 shows a schematic diagram of the occurrence of error synchronization, if the data synchronization header of the last data block in an FEC frame, the parity synchronization header of the first parity block, and the last parity block in the previous FEC frame
  • a transmission error in the verification sync header that is, the position of (1) ⁇ (3) in Figure 2 occurs at the same time.
  • the position (1) is changed from “00" to "11”, and the position (2) is wrong by the data synchronization header.
  • Verify sync header "00” position (3) is wrong by the check sync header "11” as the data sync header, then the partial frame of this FEC frame and the last check block of the previous FEC frame will be misjudged.
  • an error synchronization occurs.
  • the main technical problem to be solved by the embodiments of the present invention is to provide a data framing method and a device thereof, so that the probability of error synchronization is reduced.
  • an embodiment of the present invention provides a data framing method, including the following steps:
  • each data block includes a data synchronization header, and each parity block includes a verification synchronization header;
  • Divide N data blocks into X parts each part is called a data piece, and divide M check blocks into Y parts, each part is called a whole horse, ⁇ > ⁇ > 1, ⁇ > ⁇ > 1, at least one of X, ⁇ is greater than 1, and the difference between the absolute values of X and ⁇ is less than 2;
  • the X pieces of data are interlaced with the pieces of the check pieces to form a frame.
  • An embodiment of the present invention further provides a data framing apparatus, including:
  • a coding unit configured to encode the data blocks to obtain a check block, where each data block includes a data synchronization header, and each check block includes a check synchronization header, a data synchronization header, and a verification synchronization header Not the same;
  • the dividing unit is configured to divide the data blocks into X parts, and divide the two check blocks into two parts, ⁇ > ⁇ > 1, ⁇ > ⁇ > 1, and at least one of X and ⁇ is greater than 1, The difference between the absolute values of X and ⁇ is less than 2;
  • the arranging unit is configured to divide the data blocks of the X parts divided by the dividing unit and the check blocks of the partial parts into a frame.
  • each data block includes a data synchronization header, and each parity block includes a verification synchronization header, and the data synchronization header and the verification synchronization header are different
  • the data blocks are divided into X parts, and the check blocks are divided into two parts, ⁇ > ⁇ > 1, ⁇ > ⁇ > 1, at least one of X, ⁇ is greater than 1, the absolute value of X and ⁇ The difference is less than 2. Then, the data blocks and the check blocks of each part are arranged at intervals to form one frame.
  • 2 is a schematic diagram of error synchronization occurring according to the prior art
  • 3 is a schematic diagram showing the arrangement of data blocks and check blocks of each part in a data framing method according to the first embodiment of the present invention
  • FIG. 4 is a flow chart of a data framing method according to a first embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a data framing method according to a first embodiment of the present invention.
  • Figure 6 is a schematic view of an error pattern in a first embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a data framing method according to a second embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a data framing apparatus according to a third embodiment of the present invention. detailed description
  • a first embodiment of the present invention relates to a data framing method.
  • an FEC-coded N data block and M check blocks are arranged at intervals to form one FEC frame, that is, N data blocks.
  • the M check blocks are divided into Y parts, and the data blocks and check blocks of each part are arranged at intervals to form one frame; wherein N>X>1, M>Y> 1, X, At least one of the ⁇ is greater than 1, and the difference between the absolute values of X and ⁇ is less than 2.
  • the scrambled Si block information is subjected to 64B/66B line coding to generate a data block.
  • line coding is performed for every 64-bit block.
  • the process of line coding is to add a two-bit synchronization header in front of the block, that is, a data synchronization header, and one bit (such as the second bit) carries the data indicating the data.
  • the type of information, this bit is referred to as the important bit of the data synchronization header. For example, this important bit is "0" (which can also be “1”), indicating that all of the blocks are data; "1" (which can also be "0") means that the block has control information.
  • the other bit of the data sync header (such as the first bit) is called the secondary bit, which is the negation of the important bits of the data sync header to ensure that the 2 bits in the data sync header are mutually different bits.
  • the data block generated by the line coding includes, in addition to 64-bit information data, a 2-bit data synchronization header.
  • step 430 FEC encoding the information data in the generated data block and the important bits in the data synchronization header to obtain verification information, and generating a verification information block.
  • the data block generated by the line coding is transmitted to the line coded codeword buffer/sequence module.
  • the N data blocks are transmitted, wherein the data in the data block is synchronized.
  • the important bits and 64 bits of information data are transferred to the FEC encoder.
  • the secondary bits in the data sync header are passed directly to the sync header cache/sort module.
  • the information data in the received N data blocks and the important bits in the data synchronization header (a total of 65 ⁇ ⁇ bits) are FEC-encoded by the FEC encoder to obtain verification information.
  • the parity information is divided into parity information blocks in units of 64 bits.
  • step 440 adding two identical parity checkers (such as "00" or "11") for each check information block, and obtaining M check blocks. Adding a checksum to the check information block The sync header is used to distinguish the data block from the check block in the frame so that the receiver can synchronize the data block and the check block to perform FEC decoding and line decoding.
  • the N data blocks are divided into X parts, and the M check blocks are divided into Y parts.
  • N 30 and M is 5
  • 30 data blocks can be divided into 2 parts, and the first 12 data blocks are used as the first part N l and 18 data blocks are used as the second part N 2 ;
  • the check blocks are also divided into 2 parts, the first 3 check blocks are used as the first part, and the last 2 check blocks are used as the second part M 2 .
  • the data blocks and the check blocks of each part are arranged at intervals to form one frame.
  • the framing process for N data blocks and M check blocks is actually the position of the aligned data block and the check block in the frame.
  • the previous data block of the N data blocks is placed first, and then the previous parity block of the M check blocks is placed, and then placed, and the last N data blocks are followed by the parity block.
  • the number of all data blocks in the frame is N
  • the number of parity blocks is M
  • the data length in the frame is 66x (N + M), as shown in FIG. 5.
  • the sub-layer can be transmitted to the physical medium through the rate adjuster.
  • the probability of occurrence of FEC frame error synchronization can be reduced.
  • the error pattern of the error pattern to indicate that all the FEC frames generate error synchronization, as shown in FIG. 6.
  • the main cause of error synchronization is due to an error in the sync header of the data block or check block. Caused a misjudgment. Therefore, only the synchronization header sequence of the data block and the check block of the FEC frame is shown in FIG.
  • a complete FEC frame consists of 3 data blocks and 3 parity blocks.
  • the three check block sync headers in the FEC frame are "00", "00", and "11".
  • "4" and "6" are the minimum number of error bits required to cause some kind of error synchronization. More specifically, "4" indicates that the minimum number of error bits required to cause the two types of error synchronization of slipping 1 and 5 blocks is 4.
  • the error pattern is an important indicator to measure the probability of error synchronization.
  • the synchronization probability is determined by the minimum sample value and the minimum number of samples in the error pattern. The larger the minimum sample value, or the smaller the minimum number of samples, the less likely it is to generate false synchronizations.
  • the present embodiment can reduce the probability of occurrence of FEC frame error synchronization, thereby improving the performance of the system.
  • ⁇ indicates the number of blocks of the data block.
  • Table 1 the corresponding optimal parity synchronization header sequence in different segmentation modes is also given.
  • the first optional check sync sequence is "00 1 1 , 1 1 1 1 00" , indicating that the sync headers corresponding to the two check blocks of the first part are "00" and "1 1 "respectively;
  • the sync headers corresponding to some of the three check blocks are respectively "11""11""00"
  • the information data and the data synchronization header in the data block may also be FEC-encoded, that is, the data synchronization header of the two bits in the data block is Participate in FEC coding.
  • the data block generated by the line coding is transmitted to the line code code word buffer/sequence module.
  • the length required for one FEC encoded frame is 66 XN bits
  • the line coded codeword buffer/sequence module receives N data blocks, the N data blocks are grouped into one FEC encoded frame, and the FEC encoded frame is formed. Transfer to the FEC encoder for FEC encoding.
  • the data block and the check block are arranged at intervals to form one.
  • the 64B/66B line coding is taken as an example. In practical applications, other k/(k + 2) line codes may be used, and k is a positive integer, such as 32B/34B. Line coding.
  • a second embodiment of the present invention relates to a data framing method, and the present embodiment is substantially the same as the first embodiment, except that in the first embodiment, the scrambled information data is line coded.
  • the information data in the generated data block is scrambled again, as shown in FIG. 7.
  • This embodiment is specifically applied to the data composition sequence and framing mode of the Ethernet media independent interface data after entering the Ethernet PCS.
  • the Ethernet network-independent interface data constitutes the information data portion of the 64B/66B line code.
  • the length of each Ethernet media independent interface data is 32 bits.
  • the 8 bytes of the 64-bit information data D0 to D7 in the data block generated by the 64B/66B line encoding are sent to the scrambler for scrambling.
  • a 2-bit data sync header obtained in the 64B/66B line coding process is added in front of the scrambled 64-bit information data SO to S7.
  • the second bit of the data sync header is an important bit.
  • the scrambled information data SO ⁇ S7 together with the important bits constitute a coding block in units of 65 bits. After collecting N such coded blocks, they are sent to the FEC encoder for encoding. After the encoding is completed, the encoding blocks (each of which is composed of 64-bit information data and important bits) and the parity information block are output.
  • the 65-bit block is preceded by a secondary bit in the data sync header to form a 66-bit block, and then a 2-bit sync header is added in front of the 64-bit check block to form a check block.
  • the data block and the check block wait for framing.
  • the previous data block is placed in front of the FEC frame, then the check block is placed, then the data block and the M 2 check blocks are placed, and finally the data block and the check block are placed.
  • the number of data blocks and check blocks in this frame are N and M, respectively.
  • This frame is 66x (N + M) bits long. This frame is transmitted after passing through the rate adjuster.
  • a third embodiment of the present invention relates to a data framing apparatus, as shown in FIG. 8, including: a scrambling unit, a line coding unit, an encoding unit, a dividing unit, and an arranging unit.
  • the scrambling unit communicates with the line coding unit
  • the line coding unit communicates with the coding unit
  • the coding unit communicates with the division unit
  • the division unit communicates with the arrangement unit.
  • the scrambling unit is configured to scramble the original information data to be verified, and output the scrambled information data to the line coding unit.
  • the line coding unit is configured to perform k/(k+2) line coding on the information data (such as 64B/66B line coding), generate a data block, and output the generated data block to the coding unit, where k is a positive integer, and each The data block contains a data synchronization header.
  • the coding unit is configured to encode N data blocks to obtain M (preferably M > 5) check blocks, wherein each check block includes a check sync header, and the data sync header and the check sync header are different.
  • the subunit is used to divide the N data blocks into X parts, and divide the M check blocks into Y parts, N > X > 1 , M > Y > 1 , at least one of X and ⁇ is greater than 1 The difference between the absolute values of X and ⁇ is less than 2.
  • an arranging unit configured to block the data blocks and the check blocks of the parts divided by the dividing unit into one frame.
  • the coding unit further includes: an FEC coding subunit, configured to perform FEC encoding on the information data and the data synchronization header in the data block to generate verification information in the check blocks; or, the FEC coding subunit is used to Performing FEC encoding on the information data in the data block and the important bits in the data synchronization header to generate parity information in the parity blocks, wherein the important bits are bits indicating the type of information data in the same data block.
  • the original information data to be checked by the scrambling unit is scrambled, and the scrambled information data is output to the line coding unit.
  • the original information data to be checked by the line coding unit may be first line coded, and then the scrambling unit scrambles the information data in the data block output by the line coding unit, and the scrambled result is obtained. Output to the FEC coding unit.
  • the data blocks are encoded to obtain two check blocks, where each data block includes a data synchronization header, and each check block includes a parity synchronization header.
  • the data synchronization header and the verification synchronization header are different.
  • the data blocks are divided into X parts, and the two verification blocks are divided into two parts, ⁇ > ⁇ > 1 , ⁇ > ⁇ > 1 , X, ⁇ At least one is greater than 1, and the difference between the absolute values of X and ⁇ is less than 2.
  • the data blocks and the check blocks of each part are arranged at intervals to form one frame.
  • the number of check blocks generated after FEC encoding is 5, and if all 5 check blocks are placed after the data block, the minimum number of transmission error bits required for error synchronization is 6, that is, In all sync headers (including the data sync header and the check sync header), as long as there are transmission errors of 6 bits, it is possible to cause error synchronization. But if the check block is placed across the data block, if the five check blocks are divided into two parts, the first two check blocks are taken as the first part, and the last three check blocks are arranged as the second part.
  • the experimental result shows that the minimum number of transmission error bits required for error synchronization is 8, that is, It is said that at least 8 bits of transmission errors occur in all sync headers (including the data sync header and the check sync header), which may lead to error synchronization.
  • the information data in the data block generated by the line coding and the important bits in the data synchronization header are FEC-coded to generate a parity block, which is a bit for indicating the type of information data in the same data block. Since some bits of the data synchronization header for data block synchronization do not participate in FEC coding, the amount of information that needs to be protected by FEC coding is effectively reduced, so that more redundancy (check bits) is used for as little useful information as possible. Data is protected to achieve greater coding gain and increase the system's power budget. Moreover, since the bits used to indicate the data type are FE C-encoded, a larger coding gain can increase the correct probability of data type judgment.
  • the information data is scrambled before the FEC coding is performed, so as to ensure that the transmitted information has sufficient switching to the greatest extent, thereby facilitating the clock of the receiving end. restore.

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un procédé et un équipement de formation de trames de données qui réduisent la probabilité d'erreur de synchronisation dans le domaine des communications. Dans la présente invention, N blocs de données sont codés pour donner M blocs de parité, où l'en tête de synchronisation de données écrit dans chaque bloc de données est différent de l'en-tête de synchronisation de parité écrit dans chaque bloc de parité. Les N blocs de données sont divisés en X parties, et les M blocs de parité sont divisés en Y parties, où N ≥ X ≥ 1, M ≥ Y ≥ 1, X > 1 or Y > 1, et ΙXΙ-ΙYΙ < 2. Finalement, les X parties de données et les Y parties de parité sont entrelacées en une trame.
PCT/CN2008/071449 2007-07-09 2008-06-26 Procede et equipement de formation de trames de donnees WO2009006818A1 (fr)

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CN2007101295772A CN101345745B (zh) 2007-07-09 2007-07-09 数据成帧方法及其设备
CN200710129577.2 2007-07-09

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2187566A1 (fr) * 2008-01-14 2010-05-19 Huawei Technologies Co., Ltd. Procédé et dispositif pour signaler une erreur de données
US8831040B2 (en) 2010-03-03 2014-09-09 Hitachi, Ltd. Data transfer device and data transfer system
CN111984184A (zh) * 2019-05-23 2020-11-24 浙江宇视科技有限公司 固态硬盘的数据管理方法、装置、存储介质及电子设备

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102025448B (zh) * 2010-11-18 2013-11-06 华为技术有限公司 通用公共无线接口业务发送、接收方法及装置
CN102480333B (zh) * 2010-11-22 2014-08-13 华为技术有限公司 线路编码方法、编码数据块同步的处理方法及装置
WO2014106319A1 (fr) 2013-01-04 2014-07-10 华为技术有限公司 Procédé permettant de traiter des données dans l'ethernet, puce de couche physique et dispositif ethernet
CN106254054B (zh) * 2015-06-19 2019-11-15 北京自动化控制设备研究所 一种能够避免误同步的帧结构设计方法
CN110324110B (zh) * 2018-03-30 2020-10-27 华为技术有限公司 一种通信方法、通信设备及存储介质
CN110391871B (zh) * 2018-04-19 2021-11-19 华为技术有限公司 数据编译码方法和装置、olt、onu和pon系统
CN113381836B (zh) * 2020-02-25 2023-03-24 华为技术有限公司 一种线路编码方法及装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1128917A (zh) * 1993-09-10 1996-08-14 休斯航空公司 用在信道编码器和译码器中的高性能差错控制编码
US20040123215A1 (en) * 2002-12-20 2004-06-24 Nokia Corporation Low decoding complexity concatenated codes for high rate coded transmission
CN1606298A (zh) * 2004-11-12 2005-04-13 东南大学 利用快速傅立叶变换实现全数字无线通信系统
US20060031737A1 (en) * 2004-02-19 2006-02-09 Trellisware Technologies, Inc. Method and apparatus for communications using improved turbo like codes
CN1744484A (zh) * 2005-07-25 2006-03-08 深圳市好易通科技有限公司 无线数字信令的编码及解码方法
CN1817041A (zh) * 2003-06-30 2006-08-09 皇家飞利浦电子股份有限公司 用于译码atsc dtv信号的接收机和分组格式化器

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1128917A (zh) * 1993-09-10 1996-08-14 休斯航空公司 用在信道编码器和译码器中的高性能差错控制编码
US20040123215A1 (en) * 2002-12-20 2004-06-24 Nokia Corporation Low decoding complexity concatenated codes for high rate coded transmission
CN1817041A (zh) * 2003-06-30 2006-08-09 皇家飞利浦电子股份有限公司 用于译码atsc dtv信号的接收机和分组格式化器
US20060031737A1 (en) * 2004-02-19 2006-02-09 Trellisware Technologies, Inc. Method and apparatus for communications using improved turbo like codes
CN1606298A (zh) * 2004-11-12 2005-04-13 东南大学 利用快速傅立叶变换实现全数字无线通信系统
CN1744484A (zh) * 2005-07-25 2006-03-08 深圳市好易通科技有限公司 无线数字信令的编码及解码方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2187566A1 (fr) * 2008-01-14 2010-05-19 Huawei Technologies Co., Ltd. Procédé et dispositif pour signaler une erreur de données
EP2187566A4 (fr) * 2008-01-14 2011-06-29 Huawei Tech Co Ltd Procédé et dispositif pour signaler une erreur de données
US8560914B2 (en) 2008-01-14 2013-10-15 Huawei Technologies Co., Ltd. Method and device for indicating an uncorrectable data block
US8831040B2 (en) 2010-03-03 2014-09-09 Hitachi, Ltd. Data transfer device and data transfer system
CN111984184A (zh) * 2019-05-23 2020-11-24 浙江宇视科技有限公司 固态硬盘的数据管理方法、装置、存储介质及电子设备
CN111984184B (zh) * 2019-05-23 2022-05-17 浙江宇视科技有限公司 固态硬盘的数据管理方法、装置、存储介质及电子设备

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