WO2008141582A1 - Procédé et appareil de codage/décodage d'information - Google Patents

Procédé et appareil de codage/décodage d'information Download PDF

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Publication number
WO2008141582A1
WO2008141582A1 PCT/CN2008/071015 CN2008071015W WO2008141582A1 WO 2008141582 A1 WO2008141582 A1 WO 2008141582A1 CN 2008071015 W CN2008071015 W CN 2008071015W WO 2008141582 A1 WO2008141582 A1 WO 2008141582A1
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Prior art keywords
information
block
check
bits
line
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PCT/CN2008/071015
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English (en)
Chinese (zh)
Inventor
Weiguang Liang
Dongyu Geng
Dongning Feng
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Huawei Technologies Co., Ltd.
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Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of WO2008141582A1 publication Critical patent/WO2008141582A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control

Definitions

  • the present invention relates to the field of communications, and in particular to information coding and decoding techniques.
  • PON technology is a point-to-multipoint fiber access technology.
  • the PON is composed of an optical line terminal, an optical network unit ("ONU"), and an optical distribution network (“ODN”).
  • ONU optical network unit
  • ODN optical distribution network
  • EPON is a better access technology. Its main features are simple maintenance, low cost, high transmission bandwidth and high performance price ratio.
  • EPON technology can provide 1GHz (Gigahertz) or even 10GHz. Bandwidth, which makes it possible to simultaneously deliver voice, data and video services.
  • EPON is a technology that uses passive optical transmission, components with amplification and relay functions are not used. Therefore, the transmission distance and number of branches of an EPON network depend on the power budget and various transmission losses. As the transmission distance or the number of branch ratios increases, the Signal Noise Ratio ("SNR") of the transmitted data gradually decreases, resulting in more bit errors.
  • SNR Signal Noise Ratio
  • FEC Forward Error Correction
  • the basic working principle of the FEC in the EPON system is: adding an FEC check code word after the Ethernet frame transmitted by the transmitting end, and the check code words are in a certain relationship with the verified Ethernet frame data. Once an error occurs in the transmission, this relationship is broken, thereby realizing the data of the Ethernet frame. Error correction function. FEC technology seeks to correct as many errors as possible with as few check bytes as possible, finding an optimal balance between overhead (increased overhead of check bytes) and the resulting gain of coding.
  • PCS Physical Coding Sublayer
  • the 64b/66b line coding mechanism adds a 2-bit sync character (also known as a sync header) to 64-bit information.
  • the 2-bit sync character has only two possibilities of "01,, or "10” under normal conditions. Among them, the sync character is "01”, which means that 64 bits are all data; the sync character is "10”, which means that 64-bit information is included. Data and control information.
  • the synchronization character is "00" or "11", indicating that an error occurred during transmission. At the same time, the use of this synchronization character ensures that the transmission data is changed at least once every 66 bits. This method facilitates block synchronization. (block synchronization) 64-bit information is scrambled by a self-synchronizing scrambling mechanism to ensure that the transmitted information has sufficient switching to facilitate clock recovery at the receiving end.
  • FIG. 1 An FEC encoding scheme for the PCS layer in a 10G EPON system is shown in FIG.
  • the left half of Figure 1 is the information data to be verified, and the right half is the verification information associated with the information data.
  • the Ethernet data entering the PCS layer is first encoded by the 64b/66b line to form a line coding block in units of 66 bits (as shown in the left half of FIG. 1).
  • FEC coding is performed.
  • verification information having a multiple of 64 bits is obtained.
  • the check information is formed into a plurality of parity blocks in units of 64 bits.
  • the check block forms a check information block in units of 66 bits (as shown in the right half of Fig. 1), that is, the check information block contains the check sync header and the check block.
  • the information data and the verification information encoded by the FEC system are multiples of 66 bits. Since the information data is line-coded, each 66-bit line coding block contains a 2-bit sync header, which is always different. The 2 bits of the check sync header in the check information block are always the same. Therefore, the information can be simultaneously synchronized between the check information block and the line coding block at the receiving end, thereby facilitating FEC decoding and line decoding.
  • a 2-bit check sync header (ie, "11,” or "00") is added in front of a parity block of 64 bits. Synchronization of the information block, but does not help the performance improvement of the FEC encoding. This is because although the number of bits in the parity block is 66 bits in total, the number of bits used to verify the information data is still only 64 bits. The added 2 bits are only used to implement the synchronization of the check information block. That is to say, in the case where the 2-bit overhead is increased, the gain obtained is relatively small.
  • the prior art performs FEC encoding on the line-coded data, and the line-coded data includes redundant information (ie, a 2-bit sync header of the line coding block), that is, the FEC encodes the line redundancy.
  • the remaining information is also encoded as part of the FEC encoded data, reducing the performance of the FEC encoding.
  • the embodiments of the present invention provide an information coding and decoding method and apparatus, so that the system improves the coding gain without changing the frame structure.
  • an embodiment of the present invention provides an information encoding method, which includes the following steps:
  • the predetermined X bits in the check sync header of the check information block are filled in the partial check information
  • Embodiments of the present invention also provide an information decoding method, including the following steps:
  • An embodiment of the present invention further provides an information encoding apparatus, including:
  • a generating module configured to generate, according to the check information of the X bits, the remaining Y bits in the check sync header
  • An embodiment of the present invention further provides an information decoding apparatus, including:
  • An obtaining module configured to obtain verification information from the check information block, where part of the check information is obtained from predetermined X bits in the check sync header of the check information block, where X is a positive integer;
  • a decoding module configured to decode the line coding block corresponding to the check information block according to the verification information acquired by the acquisition module.
  • the embodiment of the present invention uses part of the bits in the check sync header of the check information block to carry partial check information, and then generates the check sync header according to the bit of the bearer part check information.
  • the remaining bits in Therefore, the information for synchronization in the check information block in the prior art is utilized without changing the frame structure without increasing the complexity, thereby improving the coding gain and increasing the power budget of the system.
  • FIG. 1 is a schematic diagram of an information encoding method for a PCS layer in a 10G EPON system in the prior art
  • FIG. 2 is a flowchart of an information encoding method according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic diagram of an information encoding method according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic diagram of an information decoding method according to Embodiment 2 of the present invention.
  • FIG. 6 is a schematic diagram of a 2-bit line coding block synchronization header according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of information to be verified in an information encoding method according to Embodiment 3 of the present invention, which does not include secondary bits in a line coding block synchronization header;
  • FIG. 8 is a schematic diagram of a secondary bit generated by a 64b/66b line encoder according to Embodiment 3 of the present invention not participating in FEC coding;
  • FIG. 9 is a flowchart of an information encoding method according to Embodiment 3 of the present invention.
  • FIG. 10 is a schematic diagram of an information encoding method according to Embodiment 3 of the present invention
  • FIG. 11 is a schematic diagram of an information decoding method according to Embodiment 4 of the present invention
  • FIG. 12 is a schematic structural diagram of an information encoding apparatus according to Embodiment 5 of the present invention.
  • FIG. 13 is a schematic structural diagram of an information encoding apparatus according to Embodiment 6 of the present invention.
  • Figure 14 is a block diagram showing the structure of an information decoding apparatus according to a seventh embodiment of the present invention.
  • the first embodiment of the present invention relates to an information encoding method.
  • the information encoding method in the present embodiment is applied to encode a line coding block in an EPON system, and the check synchronization header of the generated check information block is 2 bits. as shown in picture 2:
  • step 210 the transmitting end sends the information data from the harmonic sublayer in the form of an Ethernet packet to the PCS layer through an Ethernet medium independent interface, and then the 64b/66b line encoder transmits the information data.
  • the type is line coded, and the type of information data is divided into pure data and data with control information.
  • the received information data is divided into small pieces of information by the 64-bit information module in units of 64 bits. Then, each small block of information is line-encoded by the 64b/66b line encoder, that is, a 2-bit sync header is added in front of each small block of information, and one bit in the sync header carries information indicating the type of data in the block. As shown in Figure 3.
  • the line code block coded by the 64b/66b line is sent to the scrambler for scrambling processing, so as to ensure that the transmitted information has sufficient switching to ensure the clock recovery of the receiving end. That is to say, each line coding block coded by the 64b/66b line is further scrambled (the 2-bit synchronization head added before each line coding block does not participate in the scrambling), and the scrambled line coding block
  • the scrambled line coding block is transmitted to the codeword buffer/sequence module.
  • the codeword buffering/sorting module buffers the received data. After the data received by the codeword buffering/sequencing module reaches the length required by the FEC encoder, the received data is sorted to form an FEC encoded frame, and The FEC encoded frame is transmitted to the FEC encoder. As shown in FIG. 3, the line coding block is buffered. When the data length of the buffered line coding block satisfies the length required by the FEC encoder, It is sent to the FEC encoder, and the data length (i.e., one FEC encoded frame) sent to the FEC encoder is 66xf bits.
  • the FEC encoder performs FEC encoding on the received information to generate corresponding verification information, and the length of the generated verification information is a multiple of 65, such as 65 ⁇ bits, as shown in FIG.
  • the information that is carried in 1 , 2, ... ⁇ ) is the generated verification information.
  • the FEC encoder performs FEC encoding on the received FEC encoded frame, that is, performs FEC encoding on the scrambled line coding block to generate corresponding verification information.
  • the check information There is a constraint relationship between the check information and the line coding block. It is because of this constraint that the anti-interference ability of the line coding block is enhanced.
  • the FEC coded FEC codeword is transmitted to the check word sync header generator, and the check word sync header generator generates a check information block including the check block and the check sync header.
  • a check information block including the check block and the check sync header.
  • one bit of information is added for each block, and the value of the bit information is the same as the value of the first bit of the block, and the added bit is the same as the block.
  • the second bit to the last bit in the check information block of the bit is the check information, that is, the second bit in the check information block is used both for verifying the synchronization of the information block and for the information. Verification of data
  • the check sync header in each check information block is used to distinguish the information data in the FEC coded code word from the school insurance information, that is, to distinguish between blocks and blocks.
  • the embodiment can be understood as filling 64 bits in the block with a length of 65 bits.
  • the remaining 1 bit is filled in the check sync header, and the value of another bit in the check sync header is set to a value equal to the bit.
  • the present embodiment utilizes the bits used for synchronization in the check synchronization header in the check information block without increasing the system complexity and changing the system frame structure, and allows FEC coding to be included. More check digits for information data Protection is provided to increase the coding gain of the FEC, which in turn increases the power budget of the EPON system. Moreover, by setting the value of another bit in the check sync header to a value equal to the bit carrying the check information in the check sync header, the check sync header has the characteristic of equal bit values.
  • the full synchronization head generated in the present embodiment may only be “00, or "11", so it is convenient.
  • the receiving end synchronizes the line coding block and the check information block by using the equal characteristics of the cross-differential check sync header of the line code block sync header. For example, the receiver can pass the sync header to be "00,, (or”11"), or "10” (or "01") directly determines whether the block is a line code block or a check information block, thereby performing block synchronization.
  • the line coding block portion and the check information block portion of the FEC codeword are sent to the framing module for data recombination, framing, and transmitted to the physical medium additional sublayer for transmission in the form of a frame.
  • the line coding block and the check information block are reassembled and framed, and the code rate is adjusted and then transmitted to the physical medium additional sublayer for transmission.
  • the information data is scrambled before the line coding block is FEC-encoded.
  • the information data may be scrambled before the line coding, and the scrambled information data is line coded.
  • the line coding used may also be 32b/34b coding (or other n/(n + 2) coding mode), and the generated verification information is 33 bits long (or n +). 1 bit), the specific implementation is similar to the embodiment, and details are not described herein again.
  • the second embodiment of the present invention relates to an information decoding method, and the embodiment corresponds to the information encoding method of the first embodiment.
  • the specific process is shown in FIG. 4:
  • the physical medium attachment sublayer frames the information received from the physical medium correlation sublayer. Specifically, the physical medium additional sublayer transmits the received information to the FEC frame and the line coding block synchronization module, and completes the line coding block and the check information block by using the equal characteristics of the cross-independence check sync header of the line code synchronization header. Synchronization.
  • step 420 after completing the synchronization of the line coding block and the check information block, the first bit in each check information block is removed. Since one bit of the check sync header of the check information block carries partial check information, and the 2-bit check sync header is "00" or "11", the bit value is the same, so as long as the school is removed By verifying one bit in the synchronization header, the verification information carried in the parity information block can be obtained, which facilitates the FEC decoding performed later.
  • step 430 the synchronized line coding block and the check information block of one bit of the check synchronization header are sent to the FEC codeword sorting module for sorting the FEC frames, in the FEC codeword sorting module.
  • the FEC frame is transmitted to the FEC decoder as shown in FIG.
  • the FEC decoder decodes the received FEC frame, and recovers the synchronization header and the 64-bit information data (ie, the Si block) in the line coding block during the decoding process, and at the same time
  • the remaining check information, that is, the Pi block is removed, as shown in FIG.
  • the FEC decoder performs, according to the check information carried in the obtained check synchronization header, and the check information carried in the check information block except the check sync header, corresponding to the check information block.
  • the line coding block performs FEC decoding.
  • the FEC decoder performs FEC decoding on the line coded block corresponding to the check information block by: FEC decoding the information data in the line coded block and the synchronization header of the line coded block.
  • step 450 segmenting the FEC-decoded information, that is, dividing the FEC-decoded information into K segments (ie, divided into K line coding blocks), each segment including 64 bits.
  • the line-encoded information data and the sync header of the 2-bit line code block are as shown in FIG.
  • step 460 the information divided into K segments is descrambled, that is, the information data in the K line coding blocks is descrambled.
  • 64b/66b line decoding is performed on the descrambled K line coding blocks. Specifically, 64b/66b line decoding is performed on the information data in each line coding block after descrambling and the synchronization header in the line coding block, and the information after decoding the 64b/66b line is completed through the Ethernet.
  • the media independent interface is passed to the harmonic sublayer, as shown in Figure 5.
  • the information data is scrambled before the line coding block is FEC-encoded, so the present embodiment needs to perform FEC decoding and 64b/66b lines. Between decoding, the information data in the K line coding blocks is descrambled. In the first embodiment, before the line coding is performed, the information data is first scrambled, and then the scrambled information data is line coded. In this embodiment, after the 64b/66b line decoding is completed, , then descramble the information data.
  • Embodiment 3 of the present invention relates to an information encoding method, and the present embodiment is substantially the same as Embodiment 1, except that in Embodiment 1, by coding a line coded block in a line
  • the information data and the synchronization header are FEC-encoded to obtain verification information, as shown in FIG. 6.
  • FEC is performed on the information data in the line-coded line coding block and the important bits in the synchronization header.
  • the check information is obtained.
  • the important bit is a bit indicating the type of information data in the same line coding block.
  • the bit may be referred to as an important bit, and the other bit is referred to as a secondary bit.
  • the important bit and the secondary bit are equivalent, that is, Any one of the generated 2 bits may have a function for indicating the type of information data in the line coding block in addition to the block synchronization, as long as the bit having the function is an important bit, then another The bits are secondary bits.
  • the 2-bit sync headers in the line coding block have mutually different characteristics (i.e., "01,, or "10"), that is, the secondary bits are obtained by negating the important bits.
  • the 64-bit information data and the important bit can be sent as input data bits of the FEC encoder to the codeword buffer/sequence module, and when the data bits in the codeword buffer/sequence module form an FEC encoded data frame, And then sent to the FEC encoder for FEC encoding; and the secondary bits in the line coding block synchronization header do not participate in the FEC encoding, as shown in Figure 8.
  • This scheme can make the same size of the check information block less protected. The important information bits, thus improving the performance of FEC encoding.
  • the flowchart and schematic diagram of the present embodiment are shown in Figs. 9 and 10, respectively. Only one of the important bits in the line code block sync header encoded by the 64b/66b line is involved in FEC encoding, so the length of the information participating in the FEC encoding is a multiple of 65 bits, and the length of the check information generated after FEC encoding is still A multiple of 65 bits.
  • the method for generating the check information block is the same as that of the first embodiment.
  • the second bit in each check information block is used for both the synchronization of the check information block and the verification of the information data.
  • Embodiment 4 of the present invention relates to an information decoding method, and the present embodiment corresponds to the information encoding method of Embodiment 3.
  • the present embodiment is substantially the same as the second embodiment, except that in the second embodiment, the receiving end performs FEC decoding on the information data in the line coding block and the synchronization header of the line coding block, and completes the FEC translation.
  • the information for performing the 64b/66b line decoding is the information data in the FEC-decoded line coding block and the synchronization header in the line coding block; in this embodiment, the receiving end is the line coding block.
  • the information data in the data and the important bits in the synchronization header of the line coding block are FEC decoded, and the important bits are bits for indicating the type of information data in the same line coding block, as shown in FIG.
  • the information for performing the 64b/66b line decoding is the information data in the FEC-decoded line coding block and the important bits in the synchronization header in the line coding block, and the non-participating in the FEC decoding.
  • the secondary bit in the sync header is the information data in the FEC-decoded line coding block and the important bits in the synchronization header in the line coding block, and the non-participating in the FEC decoding.
  • the secondary bit in the sync header is the information data in the FEC-decoded line coding block and the important bits in the synchronization header in the line coding block, and the non-participating in the FEC decoding.
  • Embodiment 5 of the present invention relates to an information encoding apparatus, including: a line coding module, performing line coding on information data to be checked, generating a line coding block including a synchronization header; and a verification information generation module for coding a line
  • the information data and the synchronization header in the block are FEC-encoded to obtain verification information
  • the filling module is configured to fill the partial verification information into the predetermined X bits in the verification synchronization header of the verification information block; Generating the remaining Y bits in the check sync header according to the check information of the X bits, where X and Y are positive integers; and sending module, configured to send the check information block and the line corresponding to the check information block Encoding block.
  • the bits used for synchronization in the check sync header in the check information block are utilized, thereby increasing the coding gain without changing the frame structure and increasing the complexity, thereby increasing the coding gain. Power budget for EPON systems.
  • the line coding block in this embodiment is a line coding block of EPON, and the size of the verification synchronization head is
  • the generation module sets the value of 1 bit of one bit to a value equal to 1 bit of 1 bit.
  • the check sync header is made to have the characteristics of equal bit values, so that the receiver can synchronize the line code block and the check information block by using the equal characteristics of the cross-check and sync sync header of the line code sync header.
  • the embodiment may further include a scrambling module for scrambling the information data.
  • the scrambling result of the scrambling module is output to the line coding module; or the scrambling module scrambles the information data output by the line coding module, and then outputs the scrambled result to the verification information generation module.
  • the data from the upper layer enters the 64b/66b line encoder (ie, the line coding module), and the line encoder adds a corresponding synchronization header according to the information type to generate an inclusion.
  • a line coding block of a 2-bit sync header is sent to the scrambler (ie, the scrambling module) for scrambling and then sent to the buffer/sequencer, and the synchronization header in the line coding block is also directly sent to the buffer.
  • the cache/sequencer stores data according to certain rules.
  • the cache/sequencer sequentially transmits the set of information to the FEC code. And then start receiving and storing new blocks of information. After receiving the information group, the FEC encoder performs FEC encoding on the information group according to the selected coding rule to generate corresponding verification information.
  • the check information is sequentially sent to the check block buffer/sequencer in units of 65 bits, and the first bit in each unit is repeatedly sent to the check block buffer/sequencer, thus realizing
  • the function of filling in the module and generating the module is such that the first bit and the second bit in the generated check information block constitute a check sync header of the check information block.
  • the FEC encoder transmits the packet to the information data buffer/sequencer, and the information data buffer/sequencer and the checksum buffer/sequencer receive the full data and then transfer the data to the sending module for framing and then send it to The physical medium is attached to the sublayer.
  • Embodiment 6 of the present invention relates to an information encoding apparatus.
  • the present embodiment is substantially the same as Embodiment 5, except that in Embodiment 5, the verification information generating module is configured to use the information data and the synchronization header in the line coding block.
  • the FEC encoding is performed to obtain the verification information.
  • the verification information generating module is configured to perform FEC encoding on the information data in the line coding block and the important bits in the synchronization header to obtain verification information, the important bit.
  • the data from the upper layer enters the 64b/66b line encoder for encoding, and the line encoder adds the corresponding sync header according to the type of information (the sync header can be placed at the head end or the end of the information) Then, the line encoder transmits the 66-bit information containing the sync header that has been line coded to the corresponding buffer/sequencer. Specifically, the 64b/66b line encoder sends the 64-bit information data to the scrambler for scrambling, and then sends the scrambled 64-bit information data and the important bits in the line-coded block sync header to the first buffer.
  • each cache/sequencer stores data according to certain rules.
  • the first buffer/sequencer sequentially transmits the set of information to the FEC encoder, and then starts receiving and storing new information blocks. .
  • the FEC encoder follows the The selected coding rule performs FEC encoding on the information group to generate corresponding verification information.
  • the check information is sequentially sent to the check block buffer/sequencer in units of 65 bits, and the first bit in each unit is also repeatedly sent to the check block buffer/sequencer, so that The first bit and the second bit in the generated check information block constitute a check sync header of the check information block.
  • the FEC encoder transfers the packet to the information data buffer/sequencer. After the information data buffer/sequencer and the checksum buffer/sequencer receive the full data, the data is transmitted to the transmitting module for framing. Send to the physical media additional sublayer.
  • one bit in the line coding block synchronization header does not participate in FEC coding, which effectively reduces the amount of information that needs to be protected by FEC coding, so that more redundancy (check bits) is useful for as few as possible.
  • the information data is protected to achieve greater coding gain and increase the power budget of the EPON system.
  • a larger coding gain can increase the correct probability of data type judgment.
  • Embodiment 7 of the present invention relates to an information decoding apparatus, corresponding to the information encoding apparatus in Embodiment 5 or 6, specifically as shown in FIG. 14, including a receiving module, configured to receive a check information block and the check information. a line coding block corresponding to the block; a synchronization module, configured to synchronize the received verification information block and the line coding block corresponding to the verification information block according to the synchronization header of the verification synchronization header and the line coding block; For obtaining the check information from the synchronized check information block, where part of the check information is obtained from predetermined X bits in the check sync header of the check information block, and X is a positive integer; And configured to decode the line coding block corresponding to the check information block according to the check information acquired by the acquisition module.
  • the decoding module may decode the line coding block corresponding to the check information block by: performing FEC decoding on the information data in the line coding block and the synchronization header of the line coding block; or
  • the information data in the field and the important bits in the sync header of the line coding block are FEC-decoded, and the important bits are bits for indicating the type of information data in the same line coded block.
  • the information decoding apparatus in this embodiment may further include a line decoding module and a descrambling module.
  • the line decoding module is configured to perform line decoding on the information data in the line coding block outputted by the decoding module and the synchronization header in the line coding block; or, the information data in the line coding block outputted by the decoding module And the important bit in the synchronization header of the line coding block, along with other bits in the synchronization header not input to the decoding module, perform line decoding, and determine the number of information according to important bits in the synchronization header during line decoding According to the type.
  • the descrambling module is configured to descramble the information data. Specifically, the descrambling module descrambles the information data output by the line decoding module, or the descrambling module descrambles the information data output by the decoding module, and then outputs the descrambling result to the line decoding module. .
  • each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may exist physically separately, or two or more units may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules.
  • the integrated modules, if implemented in the form of software functional modules and sold or used as separate products, may also be stored in a computer readable storage medium.
  • the above-mentioned storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
  • part of the bits in the check sync header of the check information block are used to carry partial check information, and then check according to the bearer part.
  • the bits of the information generate the remaining bits in the check sync header. Therefore, the information for synchronization in the check information block in the prior art is utilized without changing the frame structure and without increasing the complexity, thereby improving the coding gain and further increasing the power budget of the system.
  • 1 bit of the 2-bit check sync header carries the check information, and sets the value of the other bit in the check sync header to a value equal to the bit of the bearer check information, so that the check sync header has
  • the bits are equal in characteristics, so that the receiving end can synchronize the line coding block and the check information block by using the equality characteristics of the line code synchronization header and the parity check sync header.
  • the line-encoded information data and the important bits in the sync header of the line coding block are FEC-encoded to obtain check information, which is a bit for indicating the type of information data in the same line coded block. Since some bits of the synchronization header for line coding block synchronization do not participate in FEC coding, the amount of information that needs to be protected by FEC coding is effectively reduced, so that more redundancy (check bits) is used for as little useful information as possible. The data is protected to achieve greater coding gain and increase the power budget of the EPON system. Moreover, since FEC encoding protection is applied to the bits used to indicate the data type, a larger coding gain can improve the correct probability of data type judgment. While the invention has been illustrated and described with reference to the preferred embodiments embodiments The spirit and scope of the invention.

Abstract

Procédé et appareil de codage/décodage d'information peuvent améliorer le gain de codage sans changer la structure de trame dans le système. Lors de la génération d'un bloc d'information de contrôle, la présente invention permet de transporter une partie des informations de contrôle en utilisant certains bits dans l'en-tête de synchronisation de contrôle du bloc d'information de contrôle, puis en générant les bits restants dans l'en-tête de synchronisation de contrôle conformément à ladite partie transportée des bits d'information de contrôle. En exécutant un codage de correction d'erreur sans voie de retour (FEC) sur les données d'information codées de ligne et sur les bits importants dans l'en-tête de synchronisation du bloc de codage de ligne, et en obtenant les informations de contrôle, lesdits bits importants sont les bits qui indiquent le type des données d'information dans le même bloc de codage de ligne.
PCT/CN2008/071015 2007-05-23 2008-05-20 Procédé et appareil de codage/décodage d'information WO2008141582A1 (fr)

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CN200710109329.1 2007-05-23
CN 200710109329 CN101312385B (zh) 2007-05-23 2007-05-23 信息编码译码方法及装置

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