Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31105—Etching inorganic layers
  • H01L21/31111—Etching inorganic layers by chemical means
  • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
  • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
  • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
  • H01L21/0274—Photolithographic processes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
  • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
  • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31105—Etching inorganic layers
  • H01L21/31111—Etching inorganic layers by chemical means
  • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31127—Etching organic layers
  • H01L21/31133—Etching organic layers by chemical means
  • H01L21/31138—Etching organic layers by chemical means by dry-etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
  • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
  • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
  • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T428/00—Stock material or miscellaneous articles
  • Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
  • Y10T428/263—Coating layer not in excess of 5 mils thick or equivalent
  • Y10T428/264—Up to 3 mils
  • Y10T428/265—1 mil or less

Definitions

• Various embodiments of the present invention relate to the field of semiconductor manufacture. More particularly, embodiments of the present invention disclose a method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask.
• Optical lithography the lithographic method most used in leading-edge wafer processing, comprises projecting coherent light of a given wavelength, typically 248 nanometers (nm) or 193 nm, from an illumination source (illuminator) through a quartz photomask or reticle having a chrome pattern representative of features to be formed, and imaging that pattern onto a wafer coated with photoresist.
• the light chemically alters the photoresist and enables the exposed photoresist (if positive resist is used) or the unexposed photoresist (if negative resist is used) to be rinsed away using a developer.
• FIGS. 1-2 are cross sections depicting a starting structure for various embodiments of the present invention.
• FIGS. 3-8 are cross sections depicting a first embodiment of the present invention.
• FIGS. 9-13 are cross sections depicting a second embodiment of the present invention.
• FIG. 14 is an isometric depiction of various components which may be manufactured using devices formed with an embodiment of the present invention.
• FIG. 15 is a block diagram of an embodiment of the invention to form part of a memory device having a storage transistor array.
• wafer is to be understood as a semiconductor-based material including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures.
• SOI silicon-on-insulator
• SOS silicon-on-sapphire
• doped and undoped semiconductors epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures.
• previous process steps may have been utilized to form regions or junctions in or over the base semiconductor structure or foundation.
• substrate assembly may include a wafer with materials including dielectrics and conductors and features such as transistors formed thereover, depending on the particular stage of processing.
• the semiconductor need not be silicon-based, but may be based on silicon-germanium, silicon-on-insulator, silicon-on-sapphire, germanium, or gallium arsenide, among others.
• the term "on” used with respect to two materials, one "on” the other, means at least some contact between the materials, while “over” means the materials are in close proximity, but possibly with one or more additional intervening materials such that contact is possible but not required. Neither "on” nor “over” implies any directionality as used herein.
• the term “conformal” describes a coating material in which angles of the underlying material are preserved by the conformal material.
• FIGS. 1-8 A process which results in the formation of a pattern of asymmetrical features is depicted by FIGS. 1 , 2, and 9-13.
• FIG. 1 depicts a portion of a semiconductor wafer substrate assembly comprising polysilicon 10 about 750 angstroms (A) thick; tungsten suicide (WSi x ) 12 about 900 A thick; tetraethyl orthosilicate (TEOS) 14 about 1 ,400 A thick; transparent carbon (TC) 16 about 2,000 A thick; dielectric antireflective coating (DARC) 18 from about 200 A to about 360 A thick; photoresist (resist) 20 having uniform dimensions from about 40 A to about 70 A in horizontal width, from about 1 ,200 A to about 2,000 A in vertical height, with the resist features having a regular pitch (i.e.
• a uniform distance between analogous points of adjacent resist features of from about 170 A to about 200 A; and conformal spacer material 22, for example comprising silicon nitride (Si 3 N 4 ) from about 300 A to about 500 A thick.
• conformal spacer material 22 for example comprising silicon nitride (Si 3 N 4 ) from about 300 A to about 500 A thick.
• each of the materials depicted in FIG. 1 may be used to form a NAND flash memory device.
• each of materials 10-18 may be replaced by a single dielectric material such as borophosphosilicate glass (BPSG) to form another type of device, or to form other features on a NAND flash device.
• BPSG borophosphosilicate glass
• the thicknesses may vary over a wide range beyond the values listed in the preceding paragraph, but these materials and thicknesses are believed sufficient for use during NAND flash device formation with current technology.
• the thickness variation of the DARC material may be limited by photolithography constraints, and any variation in resist and spacer width may be limited by feature pitch.
• the conformal spacer material 22 of FIG. 1 is etched using a vertical anisotropic etch to form a plurality of spacers 22 as depicted in FIG. 2.
• This etch removes spacer material selective to patterned material 20 and DARC material 18 (i.e. it will remove spacer material 22 while minimizing etching of patterned material 20 and DARC 18).
• FIG. 2 depicts paired cross sectional spacers contacting each mask feature 20.
• DARC 18 is etched selective to patterned material 20 and spacers 22 using an anisotropic etch which has some isotropic properties to result in the FIG. 3 structure.
• This etch will preferably stop on or in TC 16, and may comprise tetrafluoromethane (CF 4 ) at a flow rate of from about 60 seem to about 160 seem, difluoromethane (CH 2 F 2 ) at a flow rate of from about 5 seem to about 60 seem, and trifluoromethane (CHF 3 ) at a flow rate of about 100 seem.
• CF 4 tetrafluoromethane
• CH 2 F 2 difluoromethane
• CHF 3 trifluoromethane
• chamber pressure may be maintained to between about 5 millitorr and about 20 millitorr, and power in the range of about 600 watts to about 1 ,200 watts. While some undercutting of the dielectric under the spacer may occur, undercutting is preferably minimized.
• This etch forms one or more sloped recesses within DARC 18 resulting from the slope of the spacers 22, the pitch of adjacent spacers, and the qualities of the etch. In one embodiment, the sloped recess will have a depth of from about 200 A to about 360 A.
• the patterned material 20 is removed selective to spacers 22, DARC 18, and any exposed TC 16 using any appropriate etch to result in the FIG. 4 structure.
• One preferred etch comprises a mixture of sulfur dioxide (SO 2 ) at a flow rate of about 120 seem and oxygen (O 2 ) at a flow rate of about 80 seem. This etch may comprise the use of about 800 watts power, 8mT pressure, and a bias voltage of 400 V. Another sufficient etch would comprise the use of hydrogen bromide (HBr), O 2 , and nitrogen (N 2 ) optimized for the etch.
• Locations 40 depict openings between spacers 22 where the patterned material 20 has been removed to expose DARC 18.
• regions of exposed DARC 18 have a horizontal profile. Locations 42 depict the sloped recesses within DARC 18 between spacers 22. Regions 42 of exposed DARC 18 have a more vertically oriented profile than the exposed horizontal portions 40 where patterned material 20 has been removed.
• DARC 18, TC 16, TEOS 14, and WSi x 12 are etched using a vertical anisotropic etch which is selective to spacers 22 and which stops on or in polysilicon 10 to result in the structure of FIG. 5.
• Various known etches may be used to remove each of these materials to transfer the initial pattern to the underlayers. As depicted in FIG. 5, a lesser volume of material has been removed from materials 12-18 to form openings 42 than to form openings 40.
• Locations 40 of the depicted materials etch more quickly than locations 42, which may be due to the higher impact energy of the etchant as it contacts the horizontal bottom of the various materials at location 40, while the etchant may be deflected by the sloped sidewalls of spacers 22 at locations 42.
• FIG. 5 depicts regions 40 which have a rectangular profile, which etch deeper than regions 42 which have a "V" shaped profile.
• FIG. 6 depicts openings at location 40 which are asymmetrical with respect to openings at location 42. These openings 40, 42 have been formed using the symmetrical patterned material 20 as depicted in FIG. 1 , and may result from the difference in slope between the two vertically oriented sides of each spacer. As depicted in FIG. 4, for example, the side of each spacer which physically contacts patterned material 20 is linear and generally vertical (i.e. has a vertical or near-vertical profile), while the side of each spacer which does not contact patterned material 20 is more sloped and has a more rounded profile.
• FIGS. 7 and 8 A blanket dielectric material 70 and a blanket conductive material 72 may be formed over the surface of the FIG. 6 structure to fill the openings at locations 40 and 42 as depicted in FIG. 7.
• a planarizing process such as mechanical planarization, for example chemical-mechanical planarization (CMP) is performed on material 70 to result in the FIG. 8 structure.
• FIG. 8 depicts conductive features 80 having a first cross section and features 82 having a second cross section different from the first cross section.
• Features 80 may have different electrical properties than features 82, particularly if the features are generally uniform along their length. For example, the resistance of features 80 may be lower than features 82 due to the larger cross sectional area features 82. Further, the two features 80, 82 may form two different isolation lines, particularly with a doped substrate and oxide or another dielectric filling the trenches.
• FIGS. 1 , 2, and 9-13 symmetrical features using the same reticle used to form the patterned material 20 of FIG. 1 is depicted in FIGS. 1 , 2, and 9-13.
• the structures of FIGS. 1 and 2 are formed in accordance with the embodiment described above.
• patterned material 20 is removed selective to DARC 18 and spacers 22 to result in the structure of FIG. 9.
• DARC 18, TC 16, TEOS 14, and WSi x 12 are etched selective to spacers 22 using an isotropic etch to result in the structure of FIG. 10.
• the DARC may be etched using an isotropic etch such as CF4/CH2F 2 , where the CF ⁇ CHbF 2 ratio is at least 4.
• TC may be etched with SO2/O2 as discussed with the previous embodiment.
• TEOS may be etched with CF 4 at a flow rate of about 75 seem and O 2 at a flow rate of about 45 seem, a chamber pressure of 5 mT, and a power of 1 ,500 watts, and a bias voltage of 300 V.
• Tungsten suicide may be etched with nitrogen trifluoride (NF 3 ) and chlorine (Cl 2 ) each at a flow rate of about 40 seem, a power of about 15 mT, a power of about 400 watts, and an bias voltage of about 150 V, although other etch processes may be used.
• NF 3 nitrogen trifluoride
• Cl 2 chlorine
• spacers 22 may be removed selective to the exposed materials to result in the FIG. 11 structure, which depicts symmetrical openings 110 etched into DARC 18, TC 16, TEOS 14, and WSi x 12. These symmetrical openings are formed using the patterned material 20 of FIG. 2, which was used to form the asymmetrical openings of the previous embodiment. Thus either symmetrical or asymmetrical features may be formed using the same symmetrical pattern.
• the structure of FIG. 11 may have various functions.
• One such function is depicted in FIGS. 12 and 13.
• a blanket dielectric 120 and a blanket conductive material 122 have been formed over the FIG. 11 structure and within openings 110.
• Dielectric 120 and conductive material 122 may then be planarized using mechanical planarization, such as CMP, to result in the structure of FIG. 13.
• CMP mechanical planarization
• These features may be used as conductive lines, or may have other uses.
• each conductive feature 122 would have similar cross sections and electrical properties which may differ because of processing variances.
• FIGS. 8 and 13 may have other features depending on the intended use of the embodiments of the present invention which are not immediately germane to the present processes and structures, and which have not been described or depicted for simplicity of explanation. Various uses for the processes and structures are likely, such as for use for vertical transistors or capacitors, hard masks, shallow trench isolation, and for other device features in the array and periphery.
• a semiconductor device 140 formed in accordance with an embodiment of the disclosed invention may be attached along with other devices such as a microprocessor 142 to a printed circuit board 144, for example to a computer motherboard or as a part of a memory module used in a personal computer, a minicomputer, or a mainframe 146.
• FIG. 14 may also represent use of device 140 in other electronic devices comprising a housing 146, for example devices comprising a microprocessor 142, related to telecommunications, the automobile industry, semiconductor test and manufacturing equipment, consumer electronics, or virtually any piece of consumer or industrial electronic equipment.
• FIG. 15 is a simplified block diagram of a device such as a dynamic random access memory which may comprise conductive interconnects and other features which may be formed using an embodiment of the present invention. The general operation of such a device is known to one skilled in the art.
• FIG. 15 is a simplified block diagram of a device such as a dynamic random access memory which may comprise conductive interconnects and other features which may be formed using an embodiment of the present invention. The general operation of such a device is known to one skilled in the art.
• control circuitry 150 depicts a processor 142 coupled to a memory device 140, and further depicts the following basic sections of a memory integrated circuit: control circuitry 150; row address buffer 152 and column address buffer 154; row decoder 156 and column decoder 158; sense amplifiers 160; memory array 162; and data input/output 164.

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