WO2008155851A1 - 演算処理装置、エントリ制御プログラムおよびエントリ制御方法 - Google Patents

演算処理装置、エントリ制御プログラムおよびエントリ制御方法 Download PDF

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Publication number
WO2008155851A1
WO2008155851A1 PCT/JP2007/062465 JP2007062465W WO2008155851A1 WO 2008155851 A1 WO2008155851 A1 WO 2008155851A1 JP 2007062465 W JP2007062465 W JP 2007062465W WO 2008155851 A1 WO2008155851 A1 WO 2008155851A1
Authority
WO
WIPO (PCT)
Prior art keywords
entry
processing unit
arithmetic processing
entry control
stlb
Prior art date
Application number
PCT/JP2007/062465
Other languages
English (en)
French (fr)
Inventor
Hiroaki Kimura
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2009520205A priority Critical patent/JP4812876B2/ja
Priority to PCT/JP2007/062465 priority patent/WO2008155851A1/ja
Priority to EP07767303A priority patent/EP2159707A4/en
Publication of WO2008155851A1 publication Critical patent/WO2008155851A1/ja
Priority to US12/654,309 priority patent/US8688952B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/681—Multi-level TLB, e.g. microTLB and main TLB

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

　この演算処理装置は、主記憶部上に配置される仮想アドレスから物理アドレスへの変換表の一部をエントリとして保持するｆＴＬＢと、２ｗａｙのｓＴＬＢとから構成される。また、ｓＴＬＢとｆＴＬＢとは、ＬＲＵによって制御される同階層に配置される。そして、演算処理装置は、主記憶部から出力されたエントリをｓＴＬＢに登録する場合に、登録先となるｓＴＬＢの領域に既にエントリが登録されているか否かを判定し、登録先となるｓＴＬＢの領域に既にエントリが登録されていると判定されると、当該既に登録されているエントリを読み出してｆＴＬＢに登録する。
PCT/JP2007/062465 2007-06-20 2007-06-20 演算処理装置、エントリ制御プログラムおよびエントリ制御方法 WO2008155851A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009520205A JP4812876B2 (ja) 2007-06-20 2007-06-20 演算処理装置および演算処理装置の制御方法
PCT/JP2007/062465 WO2008155851A1 (ja) 2007-06-20 2007-06-20 演算処理装置、エントリ制御プログラムおよびエントリ制御方法
EP07767303A EP2159707A4 (en) 2007-06-20 2007-06-20 ARITHMETIC PROCESSING UNIT, INPUT TAX PROGRAM AND INPUT TAX PROCEDURE
US12/654,309 US8688952B2 (en) 2007-06-20 2009-12-16 Arithmetic processing unit and control method for evicting an entry from a TLB to another TLB

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062465 WO2008155851A1 (ja) 2007-06-20 2007-06-20 演算処理装置、エントリ制御プログラムおよびエントリ制御方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/654,309 Continuation US8688952B2 (en) 2007-06-20 2009-12-16 Arithmetic processing unit and control method for evicting an entry from a TLB to another TLB

Publications (1)

Publication Number Publication Date
WO2008155851A1 true WO2008155851A1 (ja) 2008-12-24

Family

ID=40156017

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062465 WO2008155851A1 (ja) 2007-06-20 2007-06-20 演算処理装置、エントリ制御プログラムおよびエントリ制御方法

Country Status (4)

Country Link
US (1) US8688952B2 (ja)
EP (1) EP2159707A4 (ja)
JP (1) JP4812876B2 (ja)
WO (1) WO2008155851A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
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JP2011013858A (ja) * 2009-06-30 2011-01-20 Fujitsu Ltd 演算処理装置およびアドレス変換方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130166846A1 (en) * 2011-12-26 2013-06-27 Jayesh Gaur Hierarchy-aware Replacement Policy
US9396113B2 (en) 2013-08-06 2016-07-19 Oracle International Corporation Flexible configuration hardware streaming unit
US9830275B2 (en) * 2015-05-18 2017-11-28 Imagination Technologies Limited Translation lookaside buffer
US20220206955A1 (en) * 2020-12-26 2022-06-30 Intel Corporation Automated translation lookaside buffer set rebalancing

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JPH05324477A (ja) * 1992-05-21 1993-12-07 Toshiba Corp アドレス変換バッファ機構
JPH11501745A (ja) * 1995-03-03 1999-02-09 ハル コンピュータ システムズ，インコーポレイティド コンピュータシステム内のアドレス変換用ルックアサイドバッファ
JP2000242558A (ja) * 1999-02-19 2000-09-08 Hitachi Ltd キャッシュシステム及びその操作方法

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JPS51140521A (en) * 1975-05-30 1976-12-03 Nec Corp Address exchange device
JPS5998367A (ja) * 1982-11-26 1984-06-06 Nec Corp アドレス変換バツフア方式
JPH01226056A (ja) * 1988-03-04 1989-09-08 Nec Corp アドレス変換回路
JPH03164845A (ja) * 1989-11-22 1991-07-16 Hitachi Ltd アドレス変換バッファ方式
JP3164845B2 (ja) 1991-08-30 2001-05-14 松下電器産業株式会社 書換え可能な記録媒体の記録方法
JP3229045B2 (ja) * 1992-12-22 2001-11-12 株式会社東芝 アドレス変換バッファ機構
DE19526960A1 (de) * 1994-09-27 1996-03-28 Hewlett Packard Co Eine Übersetzungs-Querzuordnungs-Puffer-Organisation mit variabler Seitengrößenabbildung und Opfer-Cache-Speicherung
US5752274A (en) * 1994-11-08 1998-05-12 Cyrix Corporation Address translation unit employing a victim TLB
US5928352A (en) * 1996-09-16 1999-07-27 Intel Corporation Method and apparatus for implementing a fully-associative translation look-aside buffer having a variable numbers of bits representing a virtual address entry
US6418521B1 (en) * 1998-12-23 2002-07-09 Intel Corporation Hierarchical fully-associative-translation lookaside buffer structure
US6941442B2 (en) * 2002-08-02 2005-09-06 Arm Limited Entry lockdown within a translation lookaside buffer mechanism
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JP4233492B2 (ja) 2004-06-02 2009-03-04 富士通マイクロエレクトロニクス株式会社 アドレス変換装置
JP4297846B2 (ja) * 2004-07-27 2009-07-15 富士通株式会社 アドレス変換バッファ制御装置およびアドレス変換バッファ制御方法
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05324477A (ja) * 1992-05-21 1993-12-07 Toshiba Corp アドレス変換バッファ機構
JPH11501745A (ja) * 1995-03-03 1999-02-09 ハル コンピュータ システムズ，インコーポレイティド コンピュータシステム内のアドレス変換用ルックアサイドバッファ
JP2000242558A (ja) * 1999-02-19 2000-09-08 Hitachi Ltd キャッシュシステム及びその操作方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011013858A (ja) * 2009-06-30 2011-01-20 Fujitsu Ltd 演算処理装置およびアドレス変換方法

Also Published As

Publication number Publication date
US8688952B2 (en) 2014-04-01
EP2159707A1 (en) 2010-03-03
EP2159707A4 (en) 2010-11-24
JPWO2008155851A1 (ja) 2010-08-26
JP4812876B2 (ja) 2011-11-09
US20100106938A1 (en) 2010-04-29

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