WO2008146338A1 - 情報処理装置及び情報処理装置の再構成方法 - Google Patents

情報処理装置及び情報処理装置の再構成方法 Download PDF

Info

Publication number
WO2008146338A1
WO2008146338A1 PCT/JP2007/000594 JP2007000594W WO2008146338A1 WO 2008146338 A1 WO2008146338 A1 WO 2008146338A1 JP 2007000594 W JP2007000594 W JP 2007000594W WO 2008146338 A1 WO2008146338 A1 WO 2008146338A1
Authority
WO
WIPO (PCT)
Prior art keywords
partition
register
packet
processing apparatus
information processing
Prior art date
Application number
PCT/JP2007/000594
Other languages
English (en)
French (fr)
Inventor
Jin Takahashi
Toshikazu Ueki
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/000594 priority Critical patent/WO2008146338A1/ja
Priority to EP07737250.6A priority patent/EP2161663B1/en
Priority to JP2009516080A priority patent/JP5136550B2/ja
Publication of WO2008146338A1 publication Critical patent/WO2008146338A1/ja
Priority to US12/626,152 priority patent/US8190805B2/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

 システムの制御を行うMMB1400は、パーティション1000に追加されるシステムボード1130に同期指示命令を送る。システムボード1130は、該同期指示命令を受信すると、パケット発行回路916によりパーティション1000のパーティションIDが付与されたレジスタリセット用パケットを生成し、それをクロスバスイッチ600内のアービタ601に送信する。アービタ601は、レジタリセット用パケットをパーティション内1000、2000の全てのシステムボードにブロードキャストする。パーティション1000内のシステムボードは前記レジスタリセット用パケットを受信すると、リセット信号r2を自ボードのレジスタに加え、該レジスタの値をリセットする。一方、パーティション2000内のSBは、前記レジスタリセット用パケットを受信すると、それを棄却する。
PCT/JP2007/000594 2007-06-01 2007-06-01 情報処理装置及び情報処理装置の再構成方法 WO2008146338A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2007/000594 WO2008146338A1 (ja) 2007-06-01 2007-06-01 情報処理装置及び情報処理装置の再構成方法
EP07737250.6A EP2161663B1 (en) 2007-06-01 2007-06-01 Information processing apparatus and method for reconfiguring information processing apparatus
JP2009516080A JP5136550B2 (ja) 2007-06-01 2007-06-01 情報処理装置及び情報処理装置の再構成方法
US12/626,152 US8190805B2 (en) 2007-06-01 2009-11-25 Information processing apparatus and method for reconfiguring the information processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000594 WO2008146338A1 (ja) 2007-06-01 2007-06-01 情報処理装置及び情報処理装置の再構成方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/626,152 Continuation US8190805B2 (en) 2007-06-01 2009-11-25 Information processing apparatus and method for reconfiguring the information processing apparatus

Publications (1)

Publication Number Publication Date
WO2008146338A1 true WO2008146338A1 (ja) 2008-12-04

Family

ID=40074626

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000594 WO2008146338A1 (ja) 2007-06-01 2007-06-01 情報処理装置及び情報処理装置の再構成方法

Country Status (4)

Country Link
US (1) US8190805B2 (ja)
EP (1) EP2161663B1 (ja)
JP (1) JP5136550B2 (ja)
WO (1) WO2008146338A1 (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010134751A (ja) * 2008-12-05 2010-06-17 Nec Computertechno Ltd マルチパーティション・コンピュータシステム、障害処理方法及びそのプログラム
JP2011013919A (ja) * 2009-07-01 2011-01-20 Fujitsu Ltd 転送速度設定方法、データ転送装置及び情報処理システム
EP2482197A1 (en) * 2009-09-25 2012-08-01 Fujitsu Limited Information processing device and device setting switching method
WO2014112042A1 (ja) * 2013-01-15 2014-07-24 富士通株式会社 情報処理装置、情報処理装置制御方法及び情報処理装置制御プログラム
JP2015220522A (ja) * 2014-05-15 2015-12-07 富士通株式会社 情報処理装置、経路決定方法及びプログラム
WO2017022117A1 (ja) * 2015-08-06 2017-02-09 富士通株式会社 制御装置,制御プログラム及び制御方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010021040A1 (ja) * 2008-08-21 2010-02-25 富士通株式会社 情報処理装置及び情報処理装置の制御方法
CN104272250A (zh) * 2012-04-30 2015-01-07 惠普发展公司,有限责任合伙企业 可配置的计算机存储器
CN105740164B (zh) * 2014-12-10 2020-03-17 阿里巴巴集团控股有限公司 支持缓存一致性的多核处理器、读写方法、装置及设备
US10489257B2 (en) * 2017-08-08 2019-11-26 Micron Technology, Inc. Replaceable memory

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0816534A (ja) * 1994-06-29 1996-01-19 Mitsubishi Electric Corp マルチプロセッサシステム
JPH0895820A (ja) 1994-09-22 1996-04-12 Hitachi Ltd 動的システム再構成時の接続確認方法
US6334177B1 (en) 1998-12-18 2001-12-25 International Business Machines Corporation Method and system for supporting software partitions and dynamic reconfiguration within a non-uniform memory access system
JP2003173325A (ja) * 2001-12-06 2003-06-20 Hitachi Ltd 計算機システムの初期化方法および電源切断方法
JP2003178044A (ja) 2001-09-25 2003-06-27 Sun Microsyst Inc 動的再構成が可能な相互接続
JP2006172483A (ja) 2004-12-18 2006-06-29 Bosch Rexroth Ag 機能モジュールのユーザインタフェースのダイナミックコンフィギュレーション方法、コンピュータプログラム、コンピュータプログラムプロダクト、コンピュータシステムおよびユーザインタフェース

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5253344A (en) * 1991-09-05 1993-10-12 International Business Machines Corp. Method and apparatus for dynamically changing the configuration of a logically partitioned data processing system
JP3163237B2 (ja) * 1995-09-28 2001-05-08 株式会社日立製作所 並列計算機システムの管理装置
US6314501B1 (en) * 1998-07-23 2001-11-06 Unisys Corporation Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory
US6438671B1 (en) * 1999-07-01 2002-08-20 International Business Machines Corporation Generating partition corresponding real address in partitioned mode supporting system
US6725317B1 (en) * 2000-04-29 2004-04-20 Hewlett-Packard Development Company, L.P. System and method for managing a computer system having a plurality of partitions
US6684343B1 (en) * 2000-04-29 2004-01-27 Hewlett-Packard Development Company, Lp. Managing operations of a computer system having a plurality of partitions
US6910142B2 (en) * 2001-07-28 2005-06-21 Hewlett-Packard Development Company, L.P. System for detection and routing of platform events in a multi-cell computer
EP1449052A2 (en) * 2001-08-10 2004-08-25 Sun Microsystems, Inc. Server blade
JP2005527006A (ja) * 2001-08-10 2005-09-08 サン・マイクロシステムズ・インコーポレーテッド コンピュータシステム管理
US6898728B2 (en) * 2001-09-25 2005-05-24 Sun Microsystems, Inc. System domain targeted, configurable interconnection
US20030061326A1 (en) * 2001-09-25 2003-03-27 Gilbert Gary L. Managing one or more domains in a system
US20030079056A1 (en) * 2001-10-18 2003-04-24 Taylor Scott E. Managing network connections in a system
US6915450B2 (en) 2001-11-01 2005-07-05 Sun Microsystems, Inc. Method and apparatus for arbitrating transactions between domains in a computer system
US7480911B2 (en) * 2002-05-09 2009-01-20 International Business Machines Corporation Method and apparatus for dynamically allocating and deallocating processors in a logical partitioned data processing system
US7565398B2 (en) * 2002-06-27 2009-07-21 International Business Machines Corporation Procedure for dynamic reconfiguration of resources of logical partitions
US8914606B2 (en) * 2004-07-08 2014-12-16 Hewlett-Packard Development Company, L.P. System and method for soft partitioning a computer system
US7453816B2 (en) * 2005-02-09 2008-11-18 International Business Machines Corporation Method and apparatus for automatic recovery from a failed node concurrent maintenance operation
JP4791061B2 (ja) * 2005-03-18 2011-10-12 富士通株式会社 計算機システムのファームウェアのバージョン管理方法及び情報処理装置
WO2007099618A1 (ja) * 2006-02-28 2007-09-07 Fujitsu Limited パーティションプライオリティ制御システムおよび方法
US20080126652A1 (en) * 2006-09-27 2008-05-29 Intel Corporation Managing Interrupts in a Partitioned Platform

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0816534A (ja) * 1994-06-29 1996-01-19 Mitsubishi Electric Corp マルチプロセッサシステム
JPH0895820A (ja) 1994-09-22 1996-04-12 Hitachi Ltd 動的システム再構成時の接続確認方法
US6334177B1 (en) 1998-12-18 2001-12-25 International Business Machines Corporation Method and system for supporting software partitions and dynamic reconfiguration within a non-uniform memory access system
JP2003178044A (ja) 2001-09-25 2003-06-27 Sun Microsyst Inc 動的再構成が可能な相互接続
JP2003173325A (ja) * 2001-12-06 2003-06-20 Hitachi Ltd 計算機システムの初期化方法および電源切断方法
JP2006172483A (ja) 2004-12-18 2006-06-29 Bosch Rexroth Ag 機能モジュールのユーザインタフェースのダイナミックコンフィギュレーション方法、コンピュータプログラム、コンピュータプログラムプロダクト、コンピュータシステムおよびユーザインタフェース

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2161663A4 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010134751A (ja) * 2008-12-05 2010-06-17 Nec Computertechno Ltd マルチパーティション・コンピュータシステム、障害処理方法及びそのプログラム
JP2011013919A (ja) * 2009-07-01 2011-01-20 Fujitsu Ltd 転送速度設定方法、データ転送装置及び情報処理システム
US8769142B2 (en) 2009-07-01 2014-07-01 Fujitsu Limited Data transfer apparatus, information processing apparatus and method of setting data transfer rate
EP2482197A1 (en) * 2009-09-25 2012-08-01 Fujitsu Limited Information processing device and device setting switching method
EP2482197A4 (en) * 2009-09-25 2013-12-18 Fujitsu Ltd INFORMATION PROCESSING METHOD AND DEVICE SETTING METHOD
WO2014112042A1 (ja) * 2013-01-15 2014-07-24 富士通株式会社 情報処理装置、情報処理装置制御方法及び情報処理装置制御プログラム
JP2015220522A (ja) * 2014-05-15 2015-12-07 富士通株式会社 情報処理装置、経路決定方法及びプログラム
WO2017022117A1 (ja) * 2015-08-06 2017-02-09 富士通株式会社 制御装置,制御プログラム及び制御方法

Also Published As

Publication number Publication date
EP2161663A1 (en) 2010-03-10
US20100146180A1 (en) 2010-06-10
EP2161663A4 (en) 2011-12-07
JPWO2008146338A1 (ja) 2010-08-12
EP2161663B1 (en) 2014-04-16
US8190805B2 (en) 2012-05-29
JP5136550B2 (ja) 2013-02-06

Similar Documents

Publication Publication Date Title
WO2008146338A1 (ja) 情報処理装置及び情報処理装置の再構成方法
WO2007146506A3 (en) Apparatus for capturing multiple data packets in a data signal for analysis
GB2429540B (en) Simulation system for multi-node process control systems
GB2449013B (en) Service-orientated architecture for process control systems
WO2006115992A3 (en) Reconfigurable backplane power distributor
WO2008039886A3 (en) Main memory in a system with a memory controller configured to control access to non-volatile memory, and related technologies
WO2008024348A3 (en) System for processing input in a wagering game machine
IL204679A0 (en) Method, system, and computer program product for adaptive congestion control on virtual lanes for data center ethernet architecture
WO2005096140A3 (en) Apparatus and method for control processing in dual path processor
GB2466151B (en) Heating system for a double-ovenized oscillator on a single printed circuit board
WO2005038571A3 (en) Data processing system having a serial data controller
GB2411540B (en) Cascade control system for network units
HK1119412A1 (en) Game system, control method thereof, game device
EP4221468A4 (en) PRINTED CIRCUIT BOARD, BACKPLATE ARCHITECTURE SYSTEM AND COMMUNICATIONS DEVICE
EP2003568A4 (en) MEMORY DEVICE, METHOD AND CONTROL PROGRAM, CORRESPONDENTS, MEMORY CARD, PRINTED CIRCUIT BOARD, AND ELECTRONIC DEVICE
DE60103217D1 (de) System zum Bearbeiten von Prozeduren auf Leiterplatten
FR2886500B1 (fr) Systeme de configuration redondante, procede de commutation de configuration redondante et appareil de traitement de communication
GB0610223D0 (en) Circuit, control system, ic, transmitting and receiving apparatus, control method, and program
EP1345109A3 (en) Information processing unit
TW200724394A (en) A multiple passes print apparatus and method
AU2003224471A1 (en) Automatic teaching method for printed circuit board inspection system
FR2906646B1 (fr) Procede de marquage individuel de circuits integres et circuit integre marque selon ce procede.
DE602008002709D1 (de) Verfahren, Vorrichtung und Computerprogrammerzeugnis zum Einsatz in Stellwerken
WO2015187954A1 (en) Decoder for a model train and method of operating a decoder for a model train
HK1105755A1 (en) Placement method and system for defective printed circuit board panel having multiple interconnected printed circuit board units

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07737250

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009516080

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2007737250

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE