Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Definitions

• the present invention relates to a flash memory data read/write processing method, and more particularly to a method of optimizing flash memory operations by performing an encoding/decoding process on data.
• Flash memory is a commonly used storage device. Flash memory is widely used in the fields of personal computers, various digital electronic devices, and other various digital storage devices more and more because it may perform data reading/writing and erasing many times and also has the characteristics of high density, large capacity, low time consumption in reading/writing operations as well as non-volatility and low power consumption.
• the increasing improvements in technology, gradually reduced cell cost prices, and increasing improvement in back-end application technology have all greatly stimulated the development of the flash memory market and made flash memory gradually have equal market share with the hard disk in the storage field.
• the flash memory has had some unavoidable defects since it came into being due to some problems in its own manufacturing process. These defects have limited the further application of the flash memory.
• a general flash memory chip has an operating life span, which is determined by a flash cell's own storage principle.
• the flash cell usually operates as follows. First, a suspended gate of the memory cell is discharged (i.e., commonly described as 'erasing') to reach a general state. Then, during the writing of the data, the suspended gate is charged (i.e., commonly described as 'programming') to reach a state needed for storing the data. As the number of erasing and programming times gradually increases, some tunneling electrons will be gradually accumulate in the suspended gate under such tunneling effect, thereby requiring a larger forward voltage for programming the memory cell again.
• the insulator medium is aging under the repeated tunneling effect and finally fails to function as a barrier (i.e., commonly described as 'barrier punctured'). Both cases will result in the memory cell's inability to operate normally (i.e., the commonly-said ending its operating period).
• the most commonly used NAND-type flash memory is used as an example for illustration below.
• the number of erasing or re-programming times of the NAND-type flash memory is generally around 100,000.
• the writing and erasing operations of the flash memory chip are special in that the flash memory chip performs the writing operation in a unit of a page and performs the erasing operation in the unit of a block.
• the process time for the writing and erasing operations of the flash memory is generally long.
• the process time for writing the data of each page on the inside the flash memory chip is 200 ⁇ s-700 ⁇ s, and the time for the erasing operation of a block is 2 ms.
• the operating time is closely related to the technology of the flash memory chip.
• the erasing operation of the flash memory configures all memory cells within the block to a state 1. During writing of the data, if the data required to be written is 1, a flash memory cell bit corresponding to the data does not need to be re-programmed. If the data required to be written is 0, the re-programming is required, i.e., the suspended gate must be charged.
• the erasing operation must be performed once again first, and those memory cells written as 0 will be discharged again. Therefore, during one operation, the larger the number of Os in the page data, the more the memory cells required to be consumed in the page.
• the time for the writing operation of the flash memory is related to the written data values in that the larger the number of Os written to the page during each operation, the longer the time required by the operation. At the same time, the conclusion is the same for the erasing operation.
• the power consumption of the flash memory chip is related to the written content.
• the existing method for addressing the problem of limited operating life span of the flash memory mainly lies in distributing the writing and erasing operations to each block as equally as possible so that each block is uniformly consumed during the use of the flash memory chip. This method is currently widely used by flash memory manufacturers. However, this method only distributes the operating consumption of the flash memory equally in each block of the flash memory chip without reducing the consumption of the flash memory chip.
• the present invention is directed to provide a flash memory data read/write processing method, which is applicable for reducing the number of times of operations causing consumption on a flash memory cell, increasing the life span and storage efficiency of the flash memory, and reducing the power consumption during the operation of the flash memory.
• the present invention provides a flash memory data read/write processing method, which includes the following steps.
• Step 1 during writing the flash memory data, first, an encoding process is performed on the data to be stored so that the number of specific values in the processed data is reduced compared with that before the encoding, and the encoded data are written into a flash memory cell.
• Step 2 during reading the flash memory data, first the encoded data in the flash memory cell is read out, a decoding process corresponding to the encoding process in Step 1 is performed on the read data, and the decoded original data is output.
• the specific values are 0 or 1.
• Step 1 includes performing the encoding process on the data to be stored at either the system host side, the flash memory controller side, or the flash memory chip side.
• Step 2 includes performing the decoding process on the read data at either the system host side, the flash memory controller side, or the flash memory chip side.
• the method further includes storing the encoded/decoded information within the flash memory chip.
• the number of the specific values in each set of binary data after the encoding process in Step 1 is no more than the number of the specific values in the corresponding set of binary data before the encoding, and Step 2 employs the decoding process corresponding thereto.
• the method further includes creating a mapping relationship between the data and the encoding so that the number of the specific values in the encoding is smaller than that in the data.
• Step 1 includes completing the encoding process of the data by querying the mapping relationship
• Step 2 includes completing the decoding process of the data by querying the mapping relationship.
• the encoding process of Step 1 includes performing an inverse on the data whose number of the specific values is larger than that of another code value
• the decoding process in Step 2 includes performing the inverse on the inversed data in the encoding process to obtain the original data information.
• the total number of the specific values in all sets of binary data after the encoding process in Step 1 is smaller than the total number of the specific values in all sets of binary data before the encoding, and Step 2 employs the decoding process corresponding thereto.
• Step 1 includes performing the encoding process on the binary data to be stored so that the number of Os in the processed binary data is smaller than that before the encoding, and writing the encoded binary data into a flash memory cell.
• the flash memory data read/write processing method of the present invention mainly reduces the number of specific values in the data by way of encoding/decoding, thereby reducing the consumption of the flash memory chip by writing and erasing operations, and prolonging the operating life span of the flash memory chip.
• the algorithm reduces the number of written data with specific values in the flash memory chip, increases the efficiency of writing and erasing operations, and reduces the operating time.
• the encoding/decoding operating method reduces the power consumption of flash memory operations.
• FIG. 1 is a schematic view illustrating the principles of an embodiment of the present invention performing an encoding/decoding process on the flash memory controller side;
• FIG. 2 is a schematic view of a writing operation of the embodiment of the present invention performing the encoding/decoding process on the flash memory controller side;
• FIG. 3 is a schematic view of a reading operation of the embodiment of the present invention performing the encoding/decoding process on the flash memory controller side;
• FIG. 4 is an operating schematic view of a flash memory chip's page data processed by the embodiment method of the present invention.
• FIG. 5 is an operating schematic view of the flash memory chip's page data without being processed by the embodiment method of the present invention
• FIG. 6 is a schematic view of combinations of 4-bit data in a mapping encoding/decoding embodiment of the present invention.
• FIG. 7 is a schematic view of combinations of data increased by 2 bits in width in the mapping encoding/decoding embodiment of the present invention.
• FIG. 8 is a schematic view of a mapping relationship between the 4-bit original data and the data with increased width in the mapping encoding/decoding embodiment of the present invention.
• FIG. 9 is a schematic view of the uncompressed original data in a compression encoding/decoding embodiment of the present invention.
• FIG. 10 is a schematic view of a correspondence between the original data and the compression encoding in the compression encoding/decoding embodiment of the present invention.
• FIG. 11 is a schematic view of the compression-encoded data in the compression encoding/decoding embodiment of the present invention.
• the main reason affecting the life span of the flash memory cell lies in the consumption of the memory cell caused by an operation from 1 to 0 during writing and an operation from 0 to 1 during erasing. Therefore, after the erasing operation of the block, the smaller the number of Os written to a page during each operation, the smaller the number of memory cells consumed during erasing and the larger the number of times of using the block. According to a statistical method, the entire life span of a flash memory chip will be prolonged as well. At the same time, the operating time may be reduced and the efficiency of writing and erasing operations may be increased by a method of controlling the written data value.
• the power consumption of flash memory operations may be reduced by controlling the written data value.
• the present invention achieves the purposes of prolonging the life span of the flash memory, optimizing flash memory operations, and reducing the flash memory power consumption by a method of optimizing the written data through encoding/decoding.
• the encoding manner employed by the present invention may include many types. Codes may be generated directly by using an algorithm so that the number of Os after the encoding is smaller than the number of Os in the original data before the encoding. Besides, the amount of data written to the memory cell, and more importantly, the number of Os in the data may be reduced by a data compression method.
• the encoding/decoding algorithm of the present invention may include many types, of whose main purposes lie in that the written data is encoded during the writing operation so that the generated codes contain as few Os as possible to reduce the consumption of the memory cell by writing and erasing operations, and at the same time the original data may be restored by a corresponding decoding method during the reading operation.
• the flash memory read/write encoding/decoding algorithm provided by the present invention can be realized widely and may be implemented by the following description methods.
• Method 1 is implemented by software.
• an encoding operation is directly performed on the data, and then the encoded data is sent to an interface of the flash memory device.
• a decoding operation is directly performed on the flash memory data read from the interface, and then the data is transmitted to other storage devices.
• Method 2 is implemented by hardware.
• An encoding/decoding module may be added in a controller module in the flash memory device.
• Method 3 includes adding an encoding/decoding module within the flash memory chip.
• the flash memory chip receives the data sent from an external controller module, it directly performs the encoding operation on the data, and then writes the encoded result into a memory cell within the corresponding address.
• the encoding/decoding module within the flash memory chip first performs the decoding operation on the encoded result read from the memory cell with the corresponding address, and then sends the result to the controller module.
• the encoder and decoder can be respectively and separately set at different device sides, including a system host side, a flash memory controller side, or a flash memory chip side.
• FIG. 1 is a schematic view illustrating principles of an embodiment of the present invention performing an encoding/decoding process at a flash memory controller side.
• 11 indicates the device data buffer for buffering the data during operation.
• 12 indicates writing data from the data buffer module to a data encoder during the writing operation of the device.
• 13 indicates the encoder in the encoding/decoding module, which mainly functions to perform an encoding operation on the data written in the buffer and write the corresponding encoded information into a redundant area or information area in the flash memory chip.
• 14 indicates the writing of the data after the processing of the encoder in the encoder/decoder into a flash memory controlling module.
• 15 indicates the flash memory controlling module for controlling flash memory operations and at the same time transmitting the encoded result to the flash memory chip.
• 17 indicates the decoder in the encoder/decoder, which mainly functions to perform a corresponding decoding operation on data in the data area according to the encoded information recorded in the data flash memory chip, and then transmit the decoded result to the data buffer as indicated by 16 in the figure.
• FIG. 2 shows an encoding operation during a writing operation of a certain page by an embodiment algorithm of the present invention.
• a size of the page for data operating is set to be 8 bytes and a redundant area is set to be 1 byte, i.e., each flash memory writing operation has a unit of 9 bytes.
• each flash memory writing operation has a unit of 9 bytes.
• an arbitrarily selected page whose data values are shown in a block in the left of the figure as "01100000 10000100 01000100 10101001 01001001 00101000 00000100 00100001", where the redundant area is "xxxxxxxl".
• the first 7 bits of the redundant area record other data information and the 8 th bit is the designated encoded information.
• the number of Os is 46 and the number of 1 is 18. According to the judgment, the encoding operation needs to be performed on the data.
• the data shown in a block in the right of the figure as "11001111 01111011 10111011 01010110 10110110 11010111 11111011 11011110" is obtained through the embodiment algorithm of the present invention, and the encoded information is written into the redundant area "xxxxxxxO" (here it is defined that the encoded information bit of 0 represents that an inverse operation has been performed; and the encoded information bit of 1 represents that the inverse operation has not been performed).
• the number of Os is 18 and the number of Is is 46.
• the encoded result is written into the flash memory chip, and at the same time a corresponding mark is written in the designated bit within the redundant area to record that the inverse operation has been performed on the page data.
• FIG. 3 shows a decoding operation during a reading operation of data recorded by a certain page by the embodiment algorithm of the present invention.
• a decoder performs the decoding operation on the encoded result and reads out the data originally written to the device according to the marking bit information in the redundant area written during the writing operation.
• FIG. 4 shows the changes of memory cell bits in the data area within the flash memory chip after the writing operation and final erasing operation of a certain page in the embodiment of the present invention.
• an erasing operation is required to be performed on the flash memory page with the address to be operated before writing data. After the erasing operation, as shown in the left block in the figure, all the memory cells are changed to 1. Then, the data is written. During writing, if the value at this position is 1 , the memory cell at this position does not need to be charged. If the value at this position is 0, the charging operation is required and the memory cell is correspondingly written as 0, as shown in the middle block in the figure. Finally, the erasing operation is performed on the written data, i.e. all the bits are discharged. If the bit is 1, it is not consumed during the current writing and erasing operations. If the bit is 0, it is consumed once during the current writing and erasing operations.
• the flash memory cell in the data area would be consumed 46 times without being processed by the encoding/decoding operation of the embodiment of the present invention as shown in FIG. 5, and is consumed 18 times after being processed by the embodiment algorithm of the present invention, so the number of times of consuming the memory cells of this page is greatly reduced.
• the operating life span can be effectively prolonged for both the entire flash memory chip and the flash memory device.
• the smaller the number of Os in the data written or erased during each operation the shorter the operating time, and the higher the efficiency.
• the smaller the number of Os the less the energy consumption required by the operation.
• the present invention is illustratively described in the above example with an inverse operation, which is the most simple and handy algorithm as an example.
• algorithms and implementation methods involved in the present invention may include many types and may be implemented not only by software but also by hardware.
• the ultimate purpose thereof is to reduce operations consuming the flash memory cell as much as possible, and to reduce the consumption of the flash memory chip by the data written into the flash memory chip as much as possible, thereby achieving optimizing purposes of prolonging the operating life span of the flash memory chip and the flash memory device, shortening the operating time, increasing the operating rate of the flash memory, as well as reducing the power consumption of flash memory operations.
• mapping encoding/decoding process manner is introduced below.
• this embodiment uses 4-bit data as an example.
• the figure shows all the collections of the 4-bit data, one of which has zero Os, four have one 0, six have two Os, four have three 0s, and one has four 0s.
• FIG. 7 shows all the combinations of the data after a 2-bit redundant area is added, one of which contains zero 0s, six contain one 0, fifteen contain two 0s, twenty contain three 0s, fifteen contain four 0s, six contain five 0s, and one contains six 0s.
• a new mapping relationship is created between the 4-bit data combinations and the 6-bit data combinations containing the redundant areas.
• the number of Os in the data may be greatly reduced.
• the mapped 6-bit data in the figure one has zero 0s, six have one 0, and nine have two 0s. Statistics are performed on the above results. Since the data is randomly generated, each value in the combination has the same probability of being recorded and written into the flash memory chip.
• the code values after the data encoding are read from the flash memory cell and the decoding operation is performed according to the mapping relationship, where the decoding is an inverse operation of the encoding to obtain the corresponding original data.
• each flash memory page includes a data area of 2048B and a redundant area of 64B.
• An encoding operation may be created.
• the host data is encoded and written into the flash memory cells. Due to the existence of the redundant area, the number of bits of the encoded data is larger than the number of bits of the original host data.
• Such encoding operation creates a new mapping relationship by combining the host data and the data with increased number of bits, so that the number of Os in the data after the encoding operation is smaller than the number of Os in the original host data, thereby achieving purposes of reducing the consumption of the flash memory chip, and prolonging the life span of the flash memory device.
• a compression-encoding process is employed by an embodiment of the present invention is illustrated in detail below.
• the present invention employs an encoding as an embodiment with a simple implementation.
• Statistics are performed on occurrence frequencies of hexadecimal data in a data segment.
• the encoded number of bits is determined according to the occurrence frequencies.
• the code value having the highest occurrence frequency is 0, followed by 10, 110, 1110 ... in turn according to the frequencies.
• One bit is added each time and one 1 is added in the highest bit.
• the encoded value is determined by a hexadecimal value corresponding to the data. The smaller the value, the smaller the number of bits of the encoded value, and vice versa.
• FIG. 9 shows the original 128-bit data without being processed by a compression operation.
• the compression operation is performed in an operational unit of 4 bits. According to statistics, all the number of combinations of 4-bit data unit in the data is shown in FIG. 10.
• a compression encoding is designed according to data writing frequencies of the statistical result, in which a correspondence between the data and the compression encoding is shown in FIG. 10. According to the statistics, the number of Os in the original data without being processed by the compression operation is 72 and the number of Is is 56.
• a result shown in FIG. 11 may be obtained by performing the compression encoding operation on the original 128-bit data.
• the data after the compression operation has 125 bits, wherein the number of Os is 32 and the number of Is is 93. Compared with the data before the compression, it is found that the number of Os is reduced by 40 and the total number of data bits is reduced by 3. Therefore, the number of Os in the data may be effectively reduced, and at the same time the number of written data bits may be reduced by such compression encoding operation.
• the written encoding is read from the flash cell, and the decoding is performed according to the correspondence between the compressed codes and the data in the compression operation, where the decoding operation is an inverse operation of the encoding to obtain the corresponding original data.
• the main purpose thereof is to reduce the number of bits of the written data, especially the number of Os in the data by the compression algorithm, thereby achieving purposes of reducing the consumption of the flash memory, prolonging the life span of the device, as well as optimizing the writing speed, and reducing its power consumption.
• the memory chip provided in the present invention includes not only NAND, NOR etc., other semiconductor memory chips having similar writing consumption all fall in the guiding principle and applying scope of the present invention, and changes apparent to those skilled in the art are within the scope of the present invention.

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• 2007
  • 2007-05-30 CN CNB200710074652XA patent/CN100468576C/zh active Active
  • 2007-09-12 TW TW096134034A patent/TWI342490B/zh not_active IP Right Cessation
• 2008
  • 2008-05-30 WO PCT/CN2008/071142 patent/WO2008145070A1/en not_active Ceased
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