WO2008140249A1 - Gap-fill method for semiconductor device - Google Patents

Gap-fill method for semiconductor device Download PDF

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Publication number
WO2008140249A1
WO2008140249A1 PCT/KR2008/002674 KR2008002674W WO2008140249A1 WO 2008140249 A1 WO2008140249 A1 WO 2008140249A1 KR 2008002674 W KR2008002674 W KR 2008002674W WO 2008140249 A1 WO2008140249 A1 WO 2008140249A1
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WO
WIPO (PCT)
Prior art keywords
gap
filler
filling method
filling
void
Prior art date
Application number
PCT/KR2008/002674
Other languages
French (fr)
Inventor
Young Kim
Original Assignee
Nest Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nest Corp. filed Critical Nest Corp.
Publication of WO2008140249A1 publication Critical patent/WO2008140249A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

Definitions

  • the present invention relates to a semiconductor manufacturing method, and more particularly to a method of filling a gap in a semiconductor device with a feature size below 45 nm.
  • an HDP CVD High Density Plasma Chemical Vapor Deposition
  • IMD InterMetal Dielectric
  • PMD PreMetal Dielectric
  • a conventional HDP CVD method repeatedly performs a deposition step and an etching step until a gap is filled, as shown in FIGs. Ia to Ie.
  • a gap in a semiconductor device having a very small CD cannot be fully filled because a void 14 is formed in the gap.
  • the present invention has been made to solve the above-mentioned problems occurring in the prior art, and the present invention is to provide a gap-filling method capable of completely filling a gap without a void, even in a semiconductor device with a feature size of below 45 nm.
  • the present invention is to provide a gap-filling method capable of completely filing a gap without a void, at the time of filling a gap in a semiconductor with a feature size of below 45 nm through the HDP CVD (High Density Plasma Chemical Vapor Deposition).
  • HDP CVD High Density Plasma Chemical Vapor Deposition
  • a gap-filling method for a semiconductor device including the steps of: a) filling a gap with filler; b) removing the filler to an extent corresponding to the maximum width and depth of a void formed in the filler; and c) repeating step a) and step b) until the gap is filled without the void.
  • step a) is preferably performed by using an HDP
  • Step b) may include the steps of: planarizing the filler; forming a mask pattern on the planarized filler so that the maximum width of the void is exposed; etching the filler so as to remove the filler; and removing the mask pattern, wherein the planarizing step may be performed using a CMP (Chemical Mechanical Polishing) process.
  • the gap may be one formed for any of STI (Shallow Trench Isolation), IMD (Intermetal Dielectric), and PMD (Premetal Dielectric).
  • a gap-filling method for a semiconductor device including the steps of: a) depositing filler on the top of an object with a gap, thereby filling the gap; b) planarizing the filler on the top of the object; c) forming a mask pattern on the planarized filler so that a part of the void is exposed; d) etching the filler; e) removing the mask pattern; and f) filling an etched space in the gap.
  • step b) to step f) may be repeatedly performed.
  • the position of the mask pattern is changed so that the exposure extent of the gap is gradually reduced as the number of times step b) to step f) are repeated is increased.
  • the position of the mask pattern is changed so that the exposure extent of the gap corresponds to the maximum width of the void formed in the filler. Consequently, step b) to step f) are repeatedly performed until the gap is filled without the void.
  • step a) and step f) the filling can be accomplished through a HDP CVD process, and the planarizing in step b) can be accomplished through a CMP process.
  • the gap may be one formed for STI, IMD and PMD.
  • FIGs. Ia to Ie are cross-sectional views for describing the steps of a conventional gap-filling method for a semiconductor device.
  • FIGs. 2 to 14 are cross-sectional views for describing the steps of a gap-filling method for a semiconductor device according to the present invention.
  • FIGs. 2 to 14 are cross-sectional views for describing the steps of a gap-filling method for a semiconductor device according to an embodiment of the present invention.
  • an oxide 230 is formed as a gap-filler on a silicon substrate 210 where a gap 220 for STI (Shallow Trench Isolation) is formed.
  • STI Shallow Trench Isolation
  • the gap 220 is defined as the gap for STI in the present embodiment, but not limited to this.
  • the gap may be one for IDM (InterMetal Dielectric) or PMD (PreMetal Dielectric).
  • the filler may be a conductive filler or another insulating filler rather than an oxide.
  • the gap 220 is one for IMD or PMD, the filler will be a conductive material.
  • the oxide 230 is described as being formed by depositing it through an HDP CVD process by way of an example. However, the present invention is not limited to this, and any process can be employed to fill the gap 220.
  • the oxide 230 is continuously deposited through the HDP CVD process so that it covers the top of the gap 220. At this time, a primary void is formed at the central area of the oxide 230.
  • a void 241 may not be produced depending on the size of the gap 220.
  • the present embodiment is described on the assumption that the void 241 is produced.
  • the top of the oxide 230 is planarized.
  • the planarization will be described as being performed through a CMP process.
  • the present invention is not limited to this, and any process can be employed in the present invention.
  • a mask pattern 250 is formed on the planarized surface of the oxide 230.
  • the mask pattern 250 is arranged so that that the top of the gap 220 is partially exposed, and the exposure extent is equal to or somewhat larger than the maximum width Wl of the primary void.
  • the mask pattern 250 is formed by a photoresist pattern, but is not limited to this. A pattern formed from any material may be employed if it can prevent the oxide 230 from being etched.
  • the mask pattern may be formed by a hard mask or a photoresist.
  • the oxide 230 is etched to a depth corresponding to the maximum depth of the primary void 241 with the mask pattern 250 being used as an etching barrier film.
  • a plasma etching process may be employed for the etching.
  • the mask pattern 250 is removed after completing the etching.
  • the top of the oxide 231 will be planarized like the step of FIG. [26]
  • a mask pattern 251 is formed on the planarized surface of the oxide like the step of FIG. 5.
  • the mask pattern 251 is arranged so that the top of the gap 220 is partially exposed, and the exposure extent is equal to or somewhat larger than the maximum width W2 of the secondary void 242.
  • the oxide 231 is etched to a depth corresponding to the maximum depth of the secondary void 242 with the mask pattern being used as an etching barrier film like the step of FIG. 6.
  • the mask pattern 251 is removed like the step of FIG. 7.
  • another layer of oxide 232 is deposited, and then, as shown in FIG.
  • the present invention it is possible to completely fill a small-sized gap without a void in a semiconductor device with a feature size below 45 nm.
  • the present invention can be used in any type of etching chambers according to a material to be etched (oxide, metal, poly, etc.).

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)

Abstract

Disclosed is a gap-filling method capable of filling a gap in a super-high integrated semiconductor device. The inventive gap-filling method includes the steps of a) filling a gap with filler; b) removing the filler to an extent corresponding to the maximum width and depth of a void formed in the filler; and c) repeating step a) and step b) until the gap is filled without the void. According to the present invention, it is possible to completely fill a small-sized gap without a void in a semiconductor device with a feature size below 45 nm.

Description

Description GAP-FILL METHOD FOR SEMICONDUCTOR DEVICE
Technical Field
[1] The present invention relates to a semiconductor manufacturing method, and more particularly to a method of filling a gap in a semiconductor device with a feature size below 45 nm. Background Art
[2] In general, an HDP CVD (High Density Plasma Chemical Vapor Deposition) equipment is being used for filling a gap in an IMD (InterMetal Dielectric), a PMD (PreMetal Dielectric) or the like. However, due to the super-high integration of semiconductor devices, the sizes of gaps in semiconductors have been reduced to such an extent that the gaps cannot be filled, even with such an HDP CVD equipment.
[3] Currently, it is known that such an HDP CVD equipment can fill gaps exceeding 60 nm with an aspect ratio of 10: 1.
[4] A conventional HDP CVD method repeatedly performs a deposition step and an etching step until a gap is filled, as shown in FIGs. Ia to Ie. However, there is a problem in that a gap in a semiconductor device having a very small CD (Critical Dimension) cannot be fully filled because a void 14 is formed in the gap.
[5] In addition, in a semiconductor device with the CD of 45 nm, such a void is formed within filler 12 filling a gap 10 as shown in FIG. Ie if the HDP CVD is employed so as to fill the gap, and the void 14 has serious deleterious effects on the semiconductor device.
Disclosure of Invention Technical Solution
[6] Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and the present invention is to provide a gap-filling method capable of completely filling a gap without a void, even in a semiconductor device with a feature size of below 45 nm.
[7] In particular, the present invention is to provide a gap-filling method capable of completely filing a gap without a void, at the time of filling a gap in a semiconductor with a feature size of below 45 nm through the HDP CVD (High Density Plasma Chemical Vapor Deposition).
[8] In order to accomplish the above-mentioned objects, according to a first aspect of the present invention, there is provided a gap-filling method for a semiconductor device including the steps of: a) filling a gap with filler; b) removing the filler to an extent corresponding to the maximum width and depth of a void formed in the filler; and c) repeating step a) and step b) until the gap is filled without the void.
[9] In the first aspect, the filling in step a) is preferably performed by using an HDP
CVD process. Step b) may include the steps of: planarizing the filler; forming a mask pattern on the planarized filler so that the maximum width of the void is exposed; etching the filler so as to remove the filler; and removing the mask pattern, wherein the planarizing step may be performed using a CMP (Chemical Mechanical Polishing) process. The gap may be one formed for any of STI (Shallow Trench Isolation), IMD (Intermetal Dielectric), and PMD (Premetal Dielectric).
[10] According to a second aspect of the present invention, there is provided a gap-filling method for a semiconductor device including the steps of: a) depositing filler on the top of an object with a gap, thereby filling the gap; b) planarizing the filler on the top of the object; c) forming a mask pattern on the planarized filler so that a part of the void is exposed; d) etching the filler; e) removing the mask pattern; and f) filling an etched space in the gap.
[11] In the second aspect, step b) to step f) may be repeatedly performed. In that event, the position of the mask pattern is changed so that the exposure extent of the gap is gradually reduced as the number of times step b) to step f) are repeated is increased. For example, the position of the mask pattern is changed so that the exposure extent of the gap corresponds to the maximum width of the void formed in the filler. Consequently, step b) to step f) are repeatedly performed until the gap is filled without the void.
[12] In step a) and step f), the filling can be accomplished through a HDP CVD process, and the planarizing in step b) can be accomplished through a CMP process. The gap may be one formed for STI, IMD and PMD. Brief Description of the Drawings
[13] The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
[14] FIGs. Ia to Ie are cross-sectional views for describing the steps of a conventional gap-filling method for a semiconductor device; and
[15] FIGs. 2 to 14 are cross-sectional views for describing the steps of a gap-filling method for a semiconductor device according to the present invention. Mode for the Invention
[16] Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. In the following description and drawings, the same reference numerals are used to designate the same or similar components. In addition, in the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.
[17] FIGs. 2 to 14 are cross-sectional views for describing the steps of a gap-filling method for a semiconductor device according to an embodiment of the present invention.
[18] As shown in FIG. 2, an oxide 230 is formed as a gap-filler on a silicon substrate 210 where a gap 220 for STI (Shallow Trench Isolation) is formed.
[19] The gap 220 is defined as the gap for STI in the present embodiment, but not limited to this. The gap may be one for IDM (InterMetal Dielectric) or PMD (PreMetal Dielectric). In this case, the filler may be a conductive filler or another insulating filler rather than an oxide. For example, if the gap 220 is one for IMD or PMD, the filler will be a conductive material. In addition, although the oxide 230 is described as being formed by depositing it through an HDP CVD process by way of an example. However, the present invention is not limited to this, and any process can be employed to fill the gap 220.
[20] As shown in FIG. 3, the oxide 230 is continuously deposited through the HDP CVD process so that it covers the top of the gap 220. At this time, a primary void is formed at the central area of the oxide 230. Of course, such a void 241 may not be produced depending on the size of the gap 220. However, the present embodiment is described on the assumption that the void 241 is produced.
[21] As shown in FIG. 4, the top of the oxide 230 is planarized. The planarization will be described as being performed through a CMP process. However, the present invention is not limited to this, and any process can be employed in the present invention.
[22] As shown in FIG. 5, a mask pattern 250 is formed on the planarized surface of the oxide 230. The mask pattern 250 is arranged so that that the top of the gap 220 is partially exposed, and the exposure extent is equal to or somewhat larger than the maximum width Wl of the primary void. The mask pattern 250 is formed by a photoresist pattern, but is not limited to this. A pattern formed from any material may be employed if it can prevent the oxide 230 from being etched. For example, the mask pattern may be formed by a hard mask or a photoresist.
[23] As shown in FIG. 6, the oxide 230 is etched to a depth corresponding to the maximum depth of the primary void 241 with the mask pattern 250 being used as an etching barrier film. A plasma etching process may be employed for the etching. As shown in FIG. 7, the mask pattern 250 is removed after completing the etching.
[24] As shown in FIG. 8, another layer of oxide 231 is deposited on the oxide 230 through the HDP CVD process until the top of the gap 220 is covered. At this time, a secondary void 242 smaller than the primary void will be produced.
[25] As shown in FIG. 9, the top of the oxide 231 will be planarized like the step of FIG. [26] As shown in FIG. 10, a mask pattern 251 is formed on the planarized surface of the oxide like the step of FIG. 5. The mask pattern 251 is arranged so that the top of the gap 220 is partially exposed, and the exposure extent is equal to or somewhat larger than the maximum width W2 of the secondary void 242. [27] As shown in FIG. 11, the oxide 231 is etched to a depth corresponding to the maximum depth of the secondary void 242 with the mask pattern being used as an etching barrier film like the step of FIG. 6. [28] As shown in FIG. 12, the mask pattern 251 is removed like the step of FIG. 7. As shown in FIG. 13, another layer of oxide 232 is deposited, and then, as shown in FIG.
14, the top of the oxides 230, 231 and 232 is removed, so that only the oxide filled in the gap 220 remains. [29] Meanwhile, if the gap 220 is fully filled and another tertiary void (not shown) is produced beyond the primary and secondary voids 241 and 242, the steps of FIGs. 10 to 13 will be repeated until the tertiary void is removed.
[30] Although a preferred embodiment of the present invention has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Industrial Applicability [31] As described above, according to the present invention, it is possible to completely fill a small-sized gap without a void in a semiconductor device with a feature size below 45 nm. [32] In particular, according to the present invention, it is possible to fill a very small gap with an aspect ratio exceeding 10: 1 if it can be etched by repeatedly performing deposition, CMP and etching. [33] In addition, the present invention can be used in any type of etching chambers according to a material to be etched (oxide, metal, poly, etc.).

Claims

Claims
[1] A gap-filling method for a semiconductor device comprising the steps of: a) filling a gap with filler; b) removing the filler to an extent corresponding to the maximum width and depth of a void formed in the filler; and c) repeating step a) and step b) until the gap is filled without the void.
[2] The gap-filling method as claimed in claim 1, wherein the filling in step a) is performed through a HDP CVD process.
[3] The gap-filling method as claimed in claim 1, wherein step b) comprises the steps of: planarizing the filler;
*forming a mask pattern on the planarized filler so that the top of the filler is exposed to an extent corresponding to the maximum width of the void; etching the filler by using the mask pattern as a barrier; and removing the mask pattern.
[4] The gap-filling method as claimed in claim 3, wherein the planarizing step is performed using a CMP (Chemical Mechanical Polishing) process.
[5] The gap-filling method as claimed in claim 1, wherein the gap is one formed for any of STI (Shallow Trench Isolation), IMD (Inetermetal Dielectric), and PMD
(Premetal Dielectric).
[6] A gap-filling method for a semiconductor device comprising the steps of: a) depositing filler on an object with a gap, thereby filling the gap; b) planarizing the filler on the object; c) forming a mask pattern on the planarized filler so that a part of the void is exposed; d) etching the filler; e) removing the mask pattern; and f) filling an etched space in the gap.
[7] The gap-filling method as claimed in claim 6, wherein, after performing step a) to step f), step b) to step f) are repeatedly performed until the gap is filled without the void.
[8] The gap-filling method as claimed in claim 7, wherein the mask pattern is positioned in such a manner that the exposure of the gap is gradually reduced as the number of times step b) to step f) are repeated is increased.
[9] The gap-filling method as claimed in claim 8, wherein the exposure extent of the gap corresponds to the maximum width of the void.
[10] The gap-filling method as claimed in claim 6, wherein the mask pattern is formed in such a manner that the top of the filler is exposed to an extent corresponding to the maximum width of the void formed in the filler. [11] The gap-filling method as claimed in claim 6, wherein the filling in step a) and step f) is performed through a HDP CVD (High Density Plasma Chemical Vapor
Deposition) process. [12] The gap-filling method as claimed in claim 6, wherein the planarizing in step b) is performed through a CMP process. [13] The gap-filling method as claimed in claim 6, wherein the gap is one formed for any of STI (Shallow Trench Isolation), IMD (Inetermetal Dielectric), and PMD
(Premetal Dielectric). [14] The gap-filling method as claimed in claim 13, wherein, if the gap is one for STI, the filler is oxide. [15] The gap-filling method as claimed in claim 13, wherein, if the gap is one for the
IMD, the filler is a conductive material. [16] The gap-filling method as claimed in claim 13, wherein, if the gap is one for
PMD, the filler is a conductive material. [17] The gap-filling method as claimed in claim 6, wherein the mask pattern is a hard mask or photoresist.
PCT/KR2008/002674 2007-05-14 2008-05-14 Gap-fill method for semiconductor device WO2008140249A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020070046560A KR100883974B1 (en) 2007-05-14 2007-05-14 Gap-fill Method for Semiconductor Device
KR10-2007-0046560 2007-05-14

Publications (1)

Publication Number Publication Date
WO2008140249A1 true WO2008140249A1 (en) 2008-11-20

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040008340A (en) * 2002-07-18 2004-01-31 삼성전자주식회사 Method for filling gaps of semiconductor device
KR20040069763A (en) * 2003-01-30 2004-08-06 아남반도체 주식회사 Method of manufacturing semiconductor
KR20040097615A (en) * 2003-05-12 2004-11-18 아남반도체 주식회사 Metal interconnection fabrication method for semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100528073B1 (en) * 2003-04-07 2005-11-15 동부아남반도체 주식회사 Fabricating method of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040008340A (en) * 2002-07-18 2004-01-31 삼성전자주식회사 Method for filling gaps of semiconductor device
KR20040069763A (en) * 2003-01-30 2004-08-06 아남반도체 주식회사 Method of manufacturing semiconductor
KR20040097615A (en) * 2003-05-12 2004-11-18 아남반도체 주식회사 Metal interconnection fabrication method for semiconductor device

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KR20080100625A (en) 2008-11-19

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