WO2008140250A1 - Reverse gap-fill method for semiconductor device - Google Patents
Reverse gap-fill method for semiconductor device Download PDFInfo
- Publication number
- WO2008140250A1 WO2008140250A1 PCT/KR2008/002675 KR2008002675W WO2008140250A1 WO 2008140250 A1 WO2008140250 A1 WO 2008140250A1 KR 2008002675 W KR2008002675 W KR 2008002675W WO 2008140250 A1 WO2008140250 A1 WO 2008140250A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- gap
- layer
- filling
- reverse
- pattern
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000000945 filler Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 4
- 239000011810 insulating material Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000011800 void material Substances 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000007792 addition Methods 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
Definitions
- the present invention relates to a semiconductor manufacturing method, and more particularly to a method of filling a gap in a semiconductor device with a feature size below 45 nm.
- HDP CVD High Density Plasma Chemical Vapor Deposition
- IMD InterMetal Dielectric
- PMD PreMetal Dielectric
- a conventional HDP CVD method repeatedly performs a deposition step and an etching step until a gap is filled, as shown in FIGs. Ia to Ie.
- a gap in a semiconductor device having a very small CD cannot be fully filled because a void 14 is formed in the gap.
- the present invention has been made to solve the above-mentioned problems occurring in the prior art, and the present invention is to provide a gap-filling method capable of completely filling a gap without a void, even in a semiconductor device with a feature size below 45 nm.
- the present invention is to provide a gap-filling method capable of completely filling a gap without a void, at the time of filling a gap for STI (Shallow Trench Isolation), IMD (InterMetal Dielectric), PMD (Premetal Dielectric) or the like in a semiconductor device with a feature size below 45 nm through HDP CVD (High Density Plasma Chemical Vapor Deposition).
- STI Shallow Trench Isolation
- IMD InterMetal Dielectric
- PMD Premetal Dielectric
- HDP CVD High Density Plasma Chemical Vapor Deposition
- a reverse gap-filling method for a semiconductor device including the steps of: a) forming a filler layer on a substrate; b) forming a mask pattern at a gap formation position on the filler layer; c) removing the filler layer using the mask pattern as a barrier, thereby forming a gap filling pattern; d) removing the mask pattern; e) forming an object layer on the substrate with the gap filling pattern; and f) planarizing the object layer by removing the top of the object layer to such an extent that the top of the gap filling pattern is revealed.
- the gap may be one formed in any of STI (Shallow Trench Isolation), IMD
- the filler layer will be formed from an insulating material, such as oxide, and the object layer will be formed from a semiconductor material, such as silicon. If the gap is one formed in the IMD or the PMD, the filler layer may be formed from a conductive material, and the object layer will be formed from an insulating material.
- the filler layer and the object layer in steps a) and d) may be formed through a deposition process
- the mask pattern in step b) may be a hard mask or a photoresist pattern
- the gap filling pattern in step c) may be formed through an etching process
- the planarization in step f) may be carried out through a CMP (Chemical and Mechanical Polishing) process.
- FIGs. Ia to Ie are cross-sectional views for describing the steps of a conventional gap-filling method for a semiconductor device.
- FIGs. 2 to 7 are cross-sectional views for describing the steps of a reverse gap-filling method for a semiconductor device according to the present invention.
- FIGs. 2 to 7 are cross-sectional views for describing the steps of a reverse gap-filling method for a semiconductor device according to an embodiment of the present invention.
- an oxide layer 220 such as SiO
- the oxide layer 220 is formed through a deposition process.
- the filler layer is defined as the oxide (e.g. SiO ) layer 220, in the present embodiment, but is not limited to this.
- the gap to be filled with the filler layer may be one formed in STI (Shallow Trench Isolation), IDM (InterMetal Dielectric) or PMD (PreMetal Dielectric). If the gap is one formed in the STI, the filler layer will be formed from an insulating material, such as an oxide. However, if the gap is one formed in the IMD or PMD, the filler layer will be formed from a conductive material.
- a mask pattern 230 is formed on the oxide layer 220 at a gap formation position. That is, the mask pattern 230 is formed on the oxide layer 220 at a position where a gap for STI will be formed.
- the mask pattern 230 may be a hard mask or a photoresist.
- the present embodiment uses a photoresist.
- the oxide layer 220 is etched and removed by using the mask pattern 230 as an etching barrier, whereby the residual of the oxide layer 220 is formed as a gap filling pattern 225.
- an Si semiconductor layer 240 as an object layer for STI is formed on the substrate 210 with the gap filling pattern 225.
- the semiconductor layer 240 is formed through a deposition process to such an extent that the gap filling pattern 225 is embedded.
- the object layer is defined as an Si semiconductor layer 240 in the present embodiment, but is not limited to this.
- the gap is one formed in STI, the object layer will be formed from a semiconductor material such as Si like the present embodiment.
- the gap is one formed in IMD or PMD, the object layer will be formed from an insulating material.
- the top of the semiconductor layer 240 is planarized to such an extent that the top of the gap filling pattern 225 is revealed.
- the planarization may be carried out through a CMP (Chemical and Mechanical Polishing) process. Consequently, the gap filling pattern 22 fills the gap for STI formed on the semiconductor layer 240.
Abstract
Disclosed is a reverse gap-filling method for a semiconductor device including the steps of: a) forming a filler layer on a substrate; b) forming a mask pattern at a gap formation position on the filler layer; c) removing the filler layer using the mask pattern as a barrier, thereby forming a gap filling pattern; d) removing the mask pattern; e) forming an object layer on the substrate with the gap filling pattern; and f) planarizing the object layer by removing the top of the object layer to such an extent that the top of the gap filling pattern is exposed. With the inventive method, it is possible to completely fill a small-sized gap without a void in a semiconductor device with a feature size below 45 nm.
Description
Description
REVERSE GAP-FILL METHOD FOR SEMICONDUCTOR
DEVICE
Technical Field
[1] The present invention relates to a semiconductor manufacturing method, and more particularly to a method of filling a gap in a semiconductor device with a feature size below 45 nm. Background Art
[2] In general, HDP CVD (High Density Plasma Chemical Vapor Deposition) equipment is being used for filling a gap for STI (Shallow Trench Isolation), IMD (InterMetal Dielectric), PMD (PreMetal Dielectric) or the like. However, due to the super-high integration of semiconductor devices, the sizes of gaps in semiconductors have been reduced to such an extent that the gaps cannot be filled, even with such HDP CVD equipment.
[3] Currently, it is known that such HDP CVD equipment can fill gaps exceeding 60 nm with an aspect ratio of 10:1.
[4] A conventional HDP CVD method repeatedly performs a deposition step and an etching step until a gap is filled, as shown in FIGs. Ia to Ie. However, there is a problem in that a gap in a semiconductor device having a very small CD (Critical Dimension) cannot be fully filled because a void 14 is formed in the gap.
[5] In addition, in a semiconductor device with the CD of 45 nm, such a void is formed within filler 12 filling a gap 10 as shown in FIG. Ie if the HDP CVD is employed so as to fill the gap, and the void 14 has serious deleterious effects on the semiconductor device.
Disclosure of Invention Technical Solution
[6] Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and the present invention is to provide a gap-filling method capable of completely filling a gap without a void, even in a semiconductor device with a feature size below 45 nm.
[7] In particular, the present invention is to provide a gap-filling method capable of completely filling a gap without a void, at the time of filling a gap for STI (Shallow Trench Isolation), IMD (InterMetal Dielectric), PMD (Premetal Dielectric) or the like in a semiconductor device with a feature size below 45 nm through HDP CVD (High Density Plasma Chemical Vapor Deposition).
[8] In order to accomplish the above-mentioned objects, according to a first aspect of the
present invention, there is provided a reverse gap-filling method for a semiconductor device including the steps of: a) forming a filler layer on a substrate; b) forming a mask pattern at a gap formation position on the filler layer; c) removing the filler layer using the mask pattern as a barrier, thereby forming a gap filling pattern; d) removing the mask pattern; e) forming an object layer on the substrate with the gap filling pattern; and f) planarizing the object layer by removing the top of the object layer to such an extent that the top of the gap filling pattern is revealed.
[9] The gap may be one formed in any of STI (Shallow Trench Isolation), IMD
(InterMetal Dielectric) and PMD (PreMetal Dielectric). If the gap is one formed in the STI, the filler layer will be formed from an insulating material, such as oxide, and the object layer will be formed from a semiconductor material, such as silicon. If the gap is one formed in the IMD or the PMD, the filler layer may be formed from a conductive material, and the object layer will be formed from an insulating material.
[10] The filler layer and the object layer in steps a) and d) may be formed through a deposition process, the mask pattern in step b) may be a hard mask or a photoresist pattern, the gap filling pattern in step c) may be formed through an etching process, and the planarization in step f) may be carried out through a CMP (Chemical and Mechanical Polishing) process. Brief Description of the Drawings
[11] The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
[12] FIGs. Ia to Ie are cross-sectional views for describing the steps of a conventional gap-filling method for a semiconductor device; and
[13] FIGs. 2 to 7 are cross-sectional views for describing the steps of a reverse gap-filling method for a semiconductor device according to the present invention. Mode for the Invention
[14] Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. In the following description and drawings, the same reference numerals are used to designate the same or similar components. In addition, in the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.
[15] FIGs. 2 to 7 are cross-sectional views for describing the steps of a reverse gap-filling method for a semiconductor device according to an embodiment of the present invention.
[16] As shown in FIG. 2, an oxide layer 220, such as SiO , is formed as a filler layer on a
substrate 210. The oxide layer 220 is formed through a deposition process. The filler layer is defined as the oxide (e.g. SiO ) layer 220, in the present embodiment, but is not limited to this. For example, the gap to be filled with the filler layer may be one formed in STI (Shallow Trench Isolation), IDM (InterMetal Dielectric) or PMD (PreMetal Dielectric). If the gap is one formed in the STI, the filler layer will be formed from an insulating material, such as an oxide. However, if the gap is one formed in the IMD or PMD, the filler layer will be formed from a conductive material.
[17] As shown in FIG. 3, a mask pattern 230 is formed on the oxide layer 220 at a gap formation position. That is, the mask pattern 230 is formed on the oxide layer 220 at a position where a gap for STI will be formed. The mask pattern 230 may be a hard mask or a photoresist. The present embodiment uses a photoresist.
[18] As shown in FIG. 4, the oxide layer 220 is etched and removed by using the mask pattern 230 as an etching barrier, whereby the residual of the oxide layer 220 is formed as a gap filling pattern 225.
[19] As shown in FIG. 5, the mask pattern 230 is removed.
[20] As shown in FIG. 6, an Si semiconductor layer 240 as an object layer for STI is formed on the substrate 210 with the gap filling pattern 225. The semiconductor layer 240 is formed through a deposition process to such an extent that the gap filling pattern 225 is embedded. The object layer is defined as an Si semiconductor layer 240 in the present embodiment, but is not limited to this. For example, if the gap is one formed in STI, the object layer will be formed from a semiconductor material such as Si like the present embodiment. However, it the gap is one formed in IMD or PMD, the object layer will be formed from an insulating material.
[21] Finally, as shown in FIG. 3f, the top of the semiconductor layer 240 is planarized to such an extent that the top of the gap filling pattern 225 is revealed. The planarization may be carried out through a CMP (Chemical and Mechanical Polishing) process. Consequently, the gap filling pattern 22 fills the gap for STI formed on the semiconductor layer 240.
[22] Although preferred embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. Therefore, the present invention is not limited to the embodiments described above, and the scope of the present invention shall be construed on the basis of the claims, so that the technical ideas equivalent to the claimed invention shall be considered as falling within the scope of the present invention. Industrial Applicability
[23] As described above, according to the inventive reverse gap-filling method, it is possible to completely fill a small-sized gap without a void in a semiconductor device with a feature size below 45 nm.
Claims
[1] A reverse gap-filling method for a semiconductor device comprising the steps of: a) forming a filler layer on a substrate; b) forming a mask pattern at a position for forming a gap on the filler layer; c) removing the filler layer using the mask pattern as a barrier, thereby forming a gap filling pattern; d) removing the mask pattern; e) forming an object layer on the substrate with the gap filling pattern; and f) planarizing the object layer by removing the top of the object layer to such an extent that the top of the gap filling pattern is exposed.
[2] The reverse gap-filling method as claimed in claim 1, wherein the gap is one formed in any of STI (Shallow Trench Isolation), IMD (InterMetal Dielectric) and PMD (PreMetal Dielectric). [3] The reverse gap-filling method as claimed in claim 2, wherein, when the gap is one formed in STI, the filler layer is formed from an insulating material, and the object layer is formed from a semiconductor material. [4] The reverse gap-filling method as claimed in claim 3, wherein the insulating material is an oxide, and the semiconductor material is silicon. [5] The reverse gap-filling method as claimed in claim 2, wherein, when the gap is one formed in IMD, the filler layer is formed from a conductive material, and the object layer is formed from an insulating material. [6] The reverse gap-filling method as claimed in claim 2, wherein, when the gap is one formed in PMD, the filler layer is formed from a conductive material, and the object layer is formed from an insulating material. [7] The reverse gap-filling method as claimed in claim 1, wherein the filler layer and the object layer in steps a) and d) are formed through a deposition process. [8] The reverse gap-filling method as claimed in claim 1, wherein the mask pattern in step b) is a hard mask or a photoresist. [9] The reverse gap-filling method as claimed in claim 1, wherein the gap filling pattern in step c) is formed through an etching process. [10] The reverse gap-filling method as claimed in claim 1, wherein the planarization in step f) is carried out through a CMP (Chemical and Mechanical Polishing) process.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2007-0046563 | 2007-05-14 | ||
| KR1020070046563A KR20080100626A (en) | 2007-05-14 | 2007-05-14 | Reverse gap-fill method for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2008140250A1 true WO2008140250A1 (en) | 2008-11-20 |
Family
ID=40002393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/KR2008/002675 WO2008140250A1 (en) | 2007-05-14 | 2008-05-14 | Reverse gap-fill method for semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR20080100626A (en) |
| WO (1) | WO2008140250A1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59194445A (en) * | 1983-04-19 | 1984-11-05 | Nec Corp | Manufacture of semiconductor device |
| JPS6130047A (en) * | 1984-07-23 | 1986-02-12 | Nec Corp | Manufacture of semiconductor device |
| KR20020045894A (en) * | 2000-12-11 | 2002-06-20 | 박종섭 | Method for forming a isolation film |
| KR20030060048A (en) * | 2002-01-04 | 2003-07-12 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device and manufacturing method thereof |
| KR20060062529A (en) * | 2004-12-03 | 2006-06-12 | 주식회사 하이닉스반도체 | Method of forming field oxide layer of semiconductor |
-
2007
- 2007-05-14 KR KR1020070046563A patent/KR20080100626A/en not_active Application Discontinuation
-
2008
- 2008-05-14 WO PCT/KR2008/002675 patent/WO2008140250A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59194445A (en) * | 1983-04-19 | 1984-11-05 | Nec Corp | Manufacture of semiconductor device |
| JPS6130047A (en) * | 1984-07-23 | 1986-02-12 | Nec Corp | Manufacture of semiconductor device |
| KR20020045894A (en) * | 2000-12-11 | 2002-06-20 | 박종섭 | Method for forming a isolation film |
| KR20030060048A (en) * | 2002-01-04 | 2003-07-12 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device and manufacturing method thereof |
| KR20060062529A (en) * | 2004-12-03 | 2006-06-12 | 주식회사 하이닉스반도체 | Method of forming field oxide layer of semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20080100626A (en) | 2008-11-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7947551B1 (en) | Method of forming a shallow trench isolation structure | |
| JP5706055B2 (en) | Structure and method for strain relaxation of TSV | |
| US8962474B2 (en) | Method for forming an air gap around a through-silicon via | |
| TWI405298B (en) | Sti formation in semiconductor device including soi and bulk silicon regions | |
| KR101615814B1 (en) | Method of forming a shallow trench isolation structure | |
| US7790601B1 (en) | Forming interconnects with air gaps | |
| US20150137378A1 (en) | Semiconductor Device having Voids and Method of Forming Same | |
| JP2008041901A (en) | Semiconductor device and its manufacturing method | |
| KR100251280B1 (en) | Sti method | |
| US20070161203A1 (en) | Method with high gapfill capability and resulting device structure | |
| US9209040B2 (en) | Amorphorus silicon insertion for STI-CMP planarity improvement | |
| KR100500439B1 (en) | method for fabricating semiconductor device with gate spacer of positive slope | |
| CN114530471A (en) | Method for forming trench isolation structure and method for forming image sensor | |
| WO2008140250A1 (en) | Reverse gap-fill method for semiconductor device | |
| KR100731090B1 (en) | Method of forming isolation layer of semiconductor device | |
| WO2008140249A1 (en) | Gap-fill method for semiconductor device | |
| KR100990577B1 (en) | Shallow trench isolation in semiconductor device and method for forming therof | |
| KR100912988B1 (en) | Method of manufacturing a semiconductor device | |
| US10504768B1 (en) | Contact structures to deep trench isolation structures and method of nanufacturing the same | |
| KR100402426B1 (en) | Trench Isolation layer of semiconductor device and method for manufacturing same | |
| US6642139B1 (en) | Method for forming interconnection structure in an integration circuit | |
| US20040253834A1 (en) | Method for fabricating a trench isolation structure | |
| KR100731129B1 (en) | Method for forming shallow trench isolation of semiconductor device | |
| KR101046376B1 (en) | Device Separating Method of Semiconductor Device | |
| KR20090011246A (en) | Method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 08753471 Country of ref document: EP Kind code of ref document: A1 |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 08753471 Country of ref document: EP Kind code of ref document: A1 |