WO2008139390A1 - Circuit mélangeur à deux modes et procédé - Google Patents

Circuit mélangeur à deux modes et procédé Download PDF

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Publication number
WO2008139390A1
WO2008139390A1 PCT/IB2008/051819 IB2008051819W WO2008139390A1 WO 2008139390 A1 WO2008139390 A1 WO 2008139390A1 IB 2008051819 W IB2008051819 W IB 2008051819W WO 2008139390 A1 WO2008139390 A1 WO 2008139390A1
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WO
WIPO (PCT)
Prior art keywords
local oscillator
oscillator signal
mixer circuit
signal
switching
Prior art date
Application number
PCT/IB2008/051819
Other languages
English (en)
Inventor
Xin He
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Priority to AT08751173T priority Critical patent/ATE506743T1/de
Priority to DE602008006393T priority patent/DE602008006393D1/de
Priority to CN200880015555.6A priority patent/CN101682299B/zh
Priority to US12/598,764 priority patent/US8260223B2/en
Priority to EP08751173A priority patent/EP2156550B1/fr
Publication of WO2008139390A1 publication Critical patent/WO2008139390A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
    • H03D7/166—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature using two or more quadrature frequency translation stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1441—Balanced arrangements with transistors using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1466—Passive mixer arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1483—Balanced arrangements with transistors comprising components for selecting a particular frequency component of the output
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0084—Lowering the supply voltage and saving power
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0086—Reduction or prevention of harmonic frequencies

Definitions

  • the present invention relates to a mixer circuit and method of frequency transformation, which can be used for example in transceiver, transmitter or receiver applications of wireless systems.
  • Direct conversion transmitter and receiver circuits can simplify the signal path by translating a desired radio frequency (RF) spectrum to a zero intermediate frequency (IF) via a single mixing stage or circuit, and thus effectively eliminate image frequency problems and hence expensive and bulky off-chip image-reject filters required in conventional heterodyne receivers. It also allows for channel selection to be performed at baseband with a simple low- pass filtering prior to a high dynamic analog-to-digital conversion. Therefore, the direct conversion approach can offer highly integrated, low-cost, low-power and multi- standard solutions e.g. for wireless products.
  • DC direct current
  • sub-harmonic mixer which may also be called harmonic mixer
  • LO local oscillator
  • EHM even-harmonic mixer
  • the sub-harmonic mixer functions transform a desired RF frequency into baseband, while rejecting the fundamental LO frequency.
  • sub-harmonic mixer functions can be implemented by passive or active circuitry, wherein both configurations require an additional 45 -degree phase shift in LO signal generation to obtain both in-phase (I) and quadrature phase (Q) channels in baseband.
  • direct up-conversion is increasingly used in transmitter architectures, due to its high level of integration.
  • the LO frequency is equal to the carrier frequency
  • intermediate up-conversion employed in dual up- conversion architectures can be eliminated. Therefore, the image problem is no longer present and discrete RF filters with high quality factors Q are not required before the power amplifier (PA).
  • PA power amplifier
  • the direct up-conversion architecture suffers from a so-called LO pulling problem.
  • the strong PA output may still be coupled to a voltage controlled oscillator (VCO) circuit which generates the LO signal, and may thus corrupt the LO spectrum (which is called "LO pulling").
  • VCO voltage controlled oscillator
  • the phenomenon of LO pulling is alleviated if the interference is far away from the LO frequency.
  • a VCO circuit with frequency two times the carrier frequency is thus used, followed by a divide-by-two circuit. The LO pulling problem can thus be solved by doubling the VCO frequency.
  • VCO remodulation still exists if the PA needs to be integrated with the RF transceiver into the same chip, for example in a Bluetooth application. Then, the second harmonic of the PA output will modulate the VCO circuit, resulting in RF spurs at the carrier offset of three times the IF input frequency. In principle, the VCO frequency cannot be an integer multiple of the carrier frequency, and vice versa.
  • a possible solution is to resort to a very complex LO generation scheme where the VCO frequency is a fraction of the carrier frequency, such as for example 4/3.
  • An object of the present invention is to provide a mixer circuit and mixing method, by means of which a flexible and efficient transmitter or receiver architecture can be achieved.
  • a dual-mode mixer concept which can be configured either in the harmonic-rejection mode or in the sub-harmonic mode.
  • the sub-harmonic mixer When applied to frequency down-conversion, the sub-harmonic mixer translates or transform the frequency of the RF input at 3rd order and 5th order harmonics of the LO frequency to baseband frequency, thus eliminating the DC offset problem.
  • the proposed solution is also advantageous for high frequency applications where the VCO and the frequency divider are difficult to implement, since the LO required in the sub-harmonic mixer can only be one third or one fifth of the desired RF frequency.
  • the original sub-harmonic mixer By switching the polarity of one of the first and at least one second local oscillator signals, the original sub-harmonic mixer can be operated as a harmonic-rejection mixer. This extends the RF range of the mixer circuit which is thus applicable for multi-standard applications.
  • the use of an odd-harmonic mixer can eliminate the VCO remodulation problem without requiring a frequency tripler. Therefore, the chip area as well as the power consumption can be reduced significantly.
  • the first local oscillator signal can be a 50% duty cycle signal and the at least one second local oscillator signal can be a 25% duty cycle signal.
  • the first local oscillator signal can be a first one of four phases generated by a divide-by- four circuit
  • the at least one second switching arrangement may comprise two switching arrangements switched in accordance with a second and, respectively, third one of said four phases generated by said divide-by- four circuit.
  • the proposed mixer circuit may be configured to operate as a frequency down-converter or alternatively as a frequency up-converter and can thus be used in receiver and transmitter circuits as well.
  • Fig. 1 shows a schematic block diagram of a direct conversion receiver architecture in which the present invention can be implemented
  • Fig. 2 shows a mixer circuit in a harmonic-rejection mode according to an embodiment
  • Fig. 3 shows local oscillator waveforms in a mixer circuit according to the embodiment
  • Fig. 4 shows a schematic block diagram of a direct conversion transmitter in which the present invention can be implemented
  • Fig. 5 shows a schematic circuit diagram similar to Fig. 2 but with an inverted polarity of a local oscillator signal to obtain a sub-harmonic mode
  • Fig. 6 shows local oscillator waveforms in the sub-harmonic mode
  • Fig. 7 shows a schematic circuit diagram of a mixer circuit in a sub-harmonic mode for frequency up-conversion
  • Fig. 8 shows a schematic block diagram of a transmitter with sub-harmonic mixer circuit according to an embodiment
  • Fig. 9 shows a harmonic-rejection mixer circuit according to an embodiment
  • Fig. 10 shows waveforms for harmonic-rejection signal generation
  • Fig. 11 shows waveforms for a sub-harmonic mixer.
  • Fig. 1 shows a schematic block diagram of a direct conversion receiver in which the embodiments can be implemented.
  • the receiver architecture comprises an RF antenna 10 for receiving a desired RF spectrum which is filtered by a band pass filter 20 and then supplied to a low noise amplifier (LNA) 30 before being split into an upper branch for separating an I component of the received signal and a lower branch for separating a Q component.
  • LNA low noise amplifier
  • the received signal is supplied to a first mixer circuit 40 to which an in-phase local oscillator signal generated by a voltage controlled oscillator (VCO) 60 and a phase shifting circuit 50 is supplied in order to extract the I component.
  • VCO voltage controlled oscillator
  • the mixer output signal is supplied to a low pass filter 70 and then via a variable gain amplifier (VGA) 80 to an analog-to-digital converter (ADC) 90 which generates a digital I output.
  • VGA variable gain amplifier
  • ADC analog-to-digital converter
  • the received signal is supplied to a second mixer circuit 42 to which a quadrature phase local oscillator signal is supplied from the local oscillator circuit in order to generate the Q component which is filtered in a low pass filter 72 and supplied to an ADC 92 via a VGA 82 to obtain a digital Q component.
  • the local oscillator circuit thus comprises the VCO 60 which output signal is supplied to the phase shifting circuit 50 to generate the in-phase and quadrature phase local oscillator signals.
  • a dual-mode harmonic-rejection and sub-harmonic mixer for frequency translation is proposed, which can be configured either as an odd-harmonic-rejection mixer or as a sub-harmonic mixer depending on a switched polarity of at least one local oscillator signal or component.
  • the sub-harmonic mixer operates as a frequency down-conversion mixer in a receiver, e.g. as shown in Fig. 1, it rejects RF at fundamental frequency of the local oscillator, while it down-converts the RF input of 3rd order and 5th order harmonics of the local oscillator signal to baseband.
  • the sub-harmonic mixer When the sub-harmonic mixer operates as a frequency up-conversion mixer in a transmitter, it up- converts the baseband input to RF only at the 3rd order and 5th order harmonics of the local oscillator.
  • Such a sub-harmonic mixer can readily be applied to RF systems on chip (SoC) where the PA is integrated into the same chip with the RF transceiver, thereby eliminating the initially mentioned VCO remodulation problem in the transmitter part.
  • SoC RF systems on chip
  • the harmonic-rejection mixer can now be switched to a sub- harmonic mode.
  • Fig. 2 shows a schematic circuit diagram of a mixer circuit according to a first embodiment in a harmonic-rejection mode.
  • This mixer circuit comprises two NMOS (N- channel metal oxide semiconductor) switching cores, wherein the upper switching core comprises transistors T cl , T C 2, T C 3 and T C 4 which are fed by 50% duty cycle local oscillator signals of positive polarity (CLK P) and negative polarity (CLK N), respectively, and a lower switching core which comprises transistors T rl , T 12 , T r 3 and T 14 which are fed by 25% duty cycle local oscillator signals of positive polarity (Roof P) and negative polarity (Roof_N), respectively.
  • the upper switching core comprises transistors T cl , T C 2, T C 3 and T C 4 which are fed by 50% duty cycle local oscillator signals of positive polarity (CLK P) and negative polarity (CLK N), respectively
  • a lower switching core which comprises transistors T rl , T 12 , T
  • the current yielded in the bottom switching core is V2 times the current yielded in the upper switching core when they are both switched on. Due to the current summing at the output terminals, envelopes of the output waveforms IF P and IF N emulate a sine wave and thus reject RF interference at frequencies of 3rd order and 5th order harmonics of the local oscillator, while transforming the input RF signal RF P and RF N to baseband.
  • Fig. 3 shows schematic waveforms of the positive and negative 50% and 25% local oscillator signals and the resulting output signal IF P of the mixer circuit of Fig. 2. Due to the different current values of the above upper and lower switching cores, different step sizes of the output signal 100 of the mixer circuit are obtain to optimize emulation the sine wave 110.
  • Fig. 4 shows a schematic block diagram of a direct conversion transmitter according to a second embodiment. Similar to the above direct conversion receiver architecture, direct up-conversion is introduced in many applications for transmitter architectures, due to its high level integration option. As shown in Fig. 4, the LO frequency is equal to the carrier frequency, thus eliminating any intermediate up-conversion employed in a dual up-conversion architecture.
  • baseband I and Q components are supplied to respective mixer circuits 240, 242 to which an in-phase component and a quadrature component of a local oscillator signal generated by a VCO 260 is applied.
  • the required phase shift is obtained by a phase shifting circuit 250.
  • Both mixer output signals are summed by an adder circuit 230 and supplied to the PA 220 in order to be transmitted via a wireless transmission channel.
  • Fig. 7 shows an example of the mixer circuits 240 and 242 of Fig. 4, which corresponds to the schematic circuit diagram of Fig. 2, wherein however an up-conversion is performed by suitable selection of the 50% duty cycle local oscillator signals CLK P, CLK N and the 25% local oscillator signals Roof N, Roof P, to thereby generate RF transmission output signals RF P and RF N.
  • the 25% local oscillator signals are now applied with an inverted polarity, so that the mixer circuit is now switched from a harmonic-rejection mode to a sub-harmonic mode.
  • Such a sub- harmonic mixer can also be applied to obtain frequency up-conversion in a transmitter circuit as shown in Fig. 4.
  • the harmonic-rejection mode can be switched to the sub- harmonic mode, as mentioned above.
  • Fig. 5 shows a schematic circuit diagram of the mixer circuit of Fig. 2, wherein the 25% duty cycle local oscillator signals have been inverted in their polarity, similar to Fig. 7. Thereby, the mixer circuit can be switched from the harmonic-rejection mode to the sub-harmonic mode in the receiver circuit of Fig. 1.
  • Fig. 6 shows waveforms of the 25% and 50% duty cycle local oscillator signals and the resulting output current of the mixer circuit, which is now obtained by subtracting the current yielded by the lower switching core from the current yielded by the upper switching core.
  • the spectrum of the equivalent local oscillator waveform in case of an operation of the mixer circuit in the sub-harmonic mode is odd-symmetrically and its period is T.
  • the associated Fourier series can be approximated as follows:
  • a RF pre-select filter can reject the RF interference at the unwanted order. This gives freedom to choose either the 3rd order harmonic or the 5th order harmonic in real applications. It is noted that choosing the 3rd order harmonic can achieve higher conversion gains.
  • the waveform combiner circuit 330 has a mode selection input MS, by means of which the mixer circuit 340 can be switched between a harmonic-rejection mode and a sub-harmonic mode.
  • the mode selection input MS is set so as to ensure that the mixer circuit 340 is operated as a sub-harmonic mixer for frequency up-conversion.
  • the mixer circuit 340 could as well be implemented in both modes in a receiver circuit.
  • Fig. 9 shows a schematic circuit diagram of a mixer circuit which can be applied as the mixer circuit 340 of Fig. 8, according to a third embodiment. Additionally, Fig. 9 shows waveforms of the local oscillation signal fVCO generated by the VCO 310 and phase signals f ⁇ (t), fl(t), f2(t) and O(t) to be supplied via the waveform combiner 330 to the mixer circuit 340.
  • Each of four mixers provided in the mixer circuit 340 to translate or transform the frequency of a desired signal from baseband to IF is realized with three active current-commuting sub-mixers all feeding common resistive loads connected to a voltage supply line Vdd, as shown in Fig. 9.
  • Each of the three sub-mixers of Fig. 9 receives the same baseband input BB through scaled input devices. However, the switches in each sub-mixer are driven by respective ones of the four phase components generated by the divide-by- four circuit 320 based on the local oscillator signal. Each sub-mixer generates a typical square wave response with the expected harmonics. However, when the signals are summed at the above resistors connected to the supply voltage Vdd, the baseband signal is effectively multiplied by a three- level, amplitude-quantized sign wave ideally having no 3rd or 5th harmonic content. Both I and Q local oscillator signals are generated using three of the four available phase components f ⁇ (t) to f3(t). In the present example of Fig.
  • the three phase components fl(t), f2(t) and f3(t) are supplied to the sub-mixers.
  • the middle sub- mixer generates a current which is V2 times higher than the currents of the left and right sub- mixers.
  • Fig. 10 shows waveforms of the three phase signals supplied to the sub-mixers and an output signal fLO(t) obtained at the right upper transistor as output signal IF+.
  • the waveform combiner circuit 330 can be controlled by the mode selection input MS to supply either the direct phase component fl(t) or the inverted phase component fl(t) to the respective sub-mixer of the mixer circuit 340.
  • the third phase signal can be output either as direct signal O(t) or inverted signal f 3(t) .
  • the mode selection input MS has no influence on the output of the second phase signal f2(t).
  • Fig. 11 shows waveforms of the three selected phase components fl(t) to O(t) and the combined output signal obtained by the three sub-mixers of Fig. 9, wherein the first and third phase components fl(t) and O(t) are now subtracted from the higher second phase component V2 f2(t) to obtain an output signal fLO(t) which reflects the sub-harmonic mode.
  • the mixer circuit 340 in combination with the waveform combining circuit 330 can be applied in a flexible manner in transmitter and receiver architectures with a desired operation mode.
  • the 50% duty cycle and 25% duty cycle local oscillation signals required for the mixer circuits of Fig. 2, Fig. 5 and Fig. 7 can as well be generated by the waveform combiner circuit 330 by suitably combining respective phase components output from the divide-by- four circuit 320.
  • the invention can be applied to all kinds of multi-mode receivers or transmitters operating in multiple frequency bands.
  • the proposed mixer circuits are configured as harmonic rejection mixers, they can function as a mixer core applicable for example in television on mobile (TVoM) applications where 3rd order and 5th order harmonic rejection is required.
  • TVoM television on mobile
  • the proposed mixer can also work as mixer core of 2G and 3G applications as well as other applications, to thereby eliminate the DC offset problem.
  • the sub-harmonic mixer itself can be applied to very high frequency applications, such as 60 GHz transceivers, where it is difficult to obtain high frequency VCO and divider circuits operating at 60 GHz or higher.
  • the local oscillator in the proposed odd-harmonic mixer can operate at one fifth of the desired RF frequency, thus saving significant power.
  • the proposed sub-harmonic mixer can also be applied to RF SoC applications where the PA is integrated into the same chip with the RF transceiver, to thereby eliminate the VCO remodulation problem in the transmitter.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Superheterodyne Receivers (AREA)
  • Transmitters (AREA)
  • Stereo-Broadcasting Methods (AREA)

Abstract

La présente invention porte sur un circuit mélangeur et sur un procédé de transformation de fréquence, où un signal d'entrée est commuté conformément à un premier signal d'oscillateur local et conformément à au moins un second signal d'oscillateur local ayant un rapport cyclique inférieur audit premier signal d'oscillateur local, ou ayant un déphasage prédéterminé respectif par rapport audit premier signal d'oscillateur local. Des signaux de sortie obtenus par la commutation conformément au premier et au moins au second signaux d'oscillateur local sont totalisés et la polarité de l'un dudit premier signal d'oscillateur local et dudit au moins un second signal d'oscillateur local est commutée en réponse à une entrée de commande, pour ainsi commuter entre un mode de rejet d'harmonique et un mode de mélange de sous-harmonique.
PCT/IB2008/051819 2007-05-11 2008-05-08 Circuit mélangeur à deux modes et procédé WO2008139390A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AT08751173T ATE506743T1 (de) 2007-05-11 2008-05-08 Bimodale mischerschaltung und verfahren
DE602008006393T DE602008006393D1 (de) 2007-05-11 2008-05-08 Bimodale mischerschaltung und verfahren
CN200880015555.6A CN101682299B (zh) 2007-05-11 2008-05-08 双模混频器电路及方法
US12/598,764 US8260223B2 (en) 2007-05-11 2008-05-08 Dual-mode mixer circuit and method
EP08751173A EP2156550B1 (fr) 2007-05-11 2008-05-08 Circuit mélangeur à deux modes et procédé

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07108066 2007-05-11
EP07108066.7 2007-05-11

Publications (1)

Publication Number Publication Date
WO2008139390A1 true WO2008139390A1 (fr) 2008-11-20

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Country Status (6)

Country Link
US (1) US8260223B2 (fr)
EP (1) EP2156550B1 (fr)
CN (1) CN101682299B (fr)
AT (1) ATE506743T1 (fr)
DE (1) DE602008006393D1 (fr)
WO (1) WO2008139390A1 (fr)

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WO2010025556A1 (fr) * 2008-09-05 2010-03-11 Icera Canada ULC Architecture d'émetteur passif à sorties commutables pour des applications sans fil
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CN101682299A (zh) 2010-03-24
EP2156550B1 (fr) 2011-04-20
US8260223B2 (en) 2012-09-04
DE602008006393D1 (de) 2011-06-01
CN101682299B (zh) 2012-10-31
EP2156550A1 (fr) 2010-02-24
US20100120377A1 (en) 2010-05-13
ATE506743T1 (de) 2011-05-15

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