WO2008129601A1 - 半導体装置の製造方法および半導体装置 - Google Patents

半導体装置の製造方法および半導体装置 Download PDF

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Publication number
WO2008129601A1
WO2008129601A1 PCT/JP2007/057668 JP2007057668W WO2008129601A1 WO 2008129601 A1 WO2008129601 A1 WO 2008129601A1 JP 2007057668 W JP2007057668 W JP 2007057668W WO 2008129601 A1 WO2008129601 A1 WO 2008129601A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
leads
exposed
zinc
prevented
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/057668
Other languages
English (en)
French (fr)
Inventor
Ryosuke Kimoto
Kazunari Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to PCT/JP2007/057668 priority Critical patent/WO2008129601A1/ja
Publication of WO2008129601A1 publication Critical patent/WO2008129601A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/456—Materials
    • H10W70/457—Materials of metallic layers on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

　リードレス形の半導体装置を構成する封止体４の４辺の側面および裏面には、複数のリード１ｂの一部が露出されている。この封止体４から露出するリード１ｂの表面（フレーム母材表面）には、錫系の金属メッキを施すことなく、耐熱性プリフラックスにより形成される保護膜５が被着されている。このように、リード１ｂの露出表面に、錫系の金属メッキ層を形成しないので、そのリード１ｂの露出表面での錫ウイスカの発生を防止することができる。したがって、錫ウイスカに起因する端子間の短絡不良を防止することができるので、半導体装置の信頼性を向上させることができる。また、リード１ｂの露出表面に保護膜５を被着することにより、リード１ｂの露出表面の錆や酸化を防止することができるので、半導体装置の電極パッド（リード１ｂの露出部）と、半導体装置を実装する配線基板のランド（電極）との接続状態を良好にすることができる。
PCT/JP2007/057668 2007-04-05 2007-04-05 半導体装置の製造方法および半導体装置 Ceased WO2008129601A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/057668 WO2008129601A1 (ja) 2007-04-05 2007-04-05 半導体装置の製造方法および半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/057668 WO2008129601A1 (ja) 2007-04-05 2007-04-05 半導体装置の製造方法および半導体装置

Publications (1)

Publication Number Publication Date
WO2008129601A1 true WO2008129601A1 (ja) 2008-10-30

Family

ID=39875150

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/057668 Ceased WO2008129601A1 (ja) 2007-04-05 2007-04-05 半導体装置の製造方法および半導体装置

Country Status (1)

Country Link
WO (1) WO2008129601A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013153005A (ja) * 2012-01-24 2013-08-08 Dainippon Printing Co Ltd 樹脂封止型半導体装置、リードフレーム、半導体装置付き配線基板および半導体装置付き配線基板の製造方法
CN107170716A (zh) * 2016-03-08 2017-09-15 株式会社吉帝伟士 半导体封装件及半导体封装件的制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04152661A (ja) * 1990-10-17 1992-05-26 Hitachi Cable Ltd Ｉｃ用リードフレーム
JPH098200A (ja) * 1995-06-26 1997-01-10 Hitachi Ltd 半導体装置の製造方法
JP2002100718A (ja) * 2000-09-21 2002-04-05 Matsushita Electric Ind Co Ltd 半導体装置用リードフレーム及びその製造方法及びそれを用いた半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04152661A (ja) * 1990-10-17 1992-05-26 Hitachi Cable Ltd Ｉｃ用リードフレーム
JPH098200A (ja) * 1995-06-26 1997-01-10 Hitachi Ltd 半導体装置の製造方法
JP2002100718A (ja) * 2000-09-21 2002-04-05 Matsushita Electric Ind Co Ltd 半導体装置用リードフレーム及びその製造方法及びそれを用いた半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013153005A (ja) * 2012-01-24 2013-08-08 Dainippon Printing Co Ltd 樹脂封止型半導体装置、リードフレーム、半導体装置付き配線基板および半導体装置付き配線基板の製造方法
CN107170716A (zh) * 2016-03-08 2017-09-15 株式会社吉帝伟士 半导体封装件及半导体封装件的制造方法
CN107170716B (zh) * 2016-03-08 2022-05-27 安靠科技日本公司 半导体封装件及半导体封装件的制造方法

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