WO2008126165A1 - 試験装置 - Google Patents

試験装置 Download PDF

Info

Publication number
WO2008126165A1
WO2008126165A1 PCT/JP2007/054668 JP2007054668W WO2008126165A1 WO 2008126165 A1 WO2008126165 A1 WO 2008126165A1 JP 2007054668 W JP2007054668 W JP 2007054668W WO 2008126165 A1 WO2008126165 A1 WO 2008126165A1
Authority
WO
WIPO (PCT)
Prior art keywords
status
memory
match
output
under test
Prior art date
Application number
PCT/JP2007/054668
Other languages
English (en)
French (fr)
Inventor
Masaru Doi
Shinya Sato
Original Assignee
Advantest Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corporation filed Critical Advantest Corporation
Priority to PCT/JP2007/054668 priority Critical patent/WO2008126165A1/ja
Priority to KR1020097018457A priority patent/KR101055356B1/ko
Priority to JP2007541562A priority patent/JP4939428B2/ja
Priority to CN200780052075A priority patent/CN101627446A/zh
Priority to TW097107484A priority patent/TW200845019A/zh
Publication of WO2008126165A1 publication Critical patent/WO2008126165A1/ja

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

　被試験メモリのステータス出力端子から出力されるそれぞれのコマンドの処理状態を示すステータス信号をそれぞれ受け取ってステータス信号がレディ状態となったことに応じてマッチ信号をそれぞれ出力する複数のマッチ検出部と、複数のマッチ検出部から出力される複数のマッチ信号の論理積に基づいて、被試験メモリが複数のコマンドの処理を終えたと判定する判定部と、複数のメモリバンクを有する被試験メモリの試験において、複数のマッチ検出部のそれぞれを複数のメモリバンクのそれぞれに対応して割り当てる割当部とを備え、複数のメモリバンクを有する被試験メモリの試験において、複数のマッチ検出部のそれぞれは、被試験メモリのステータス出力端子からメモリバンク毎に異なるサイクルに出力される、それぞれのコマンドの処理状態を示すステータス信号のうち対応するメモリバンクのステータス信号を受け取って、マッチ信号を出力する試験装置を提供する。
PCT/JP2007/054668 2007-03-09 2007-03-09 試験装置 WO2008126165A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/JP2007/054668 WO2008126165A1 (ja) 2007-03-09 2007-03-09 試験装置
KR1020097018457A KR101055356B1 (ko) 2007-03-09 2007-03-09 시험 장치
JP2007541562A JP4939428B2 (ja) 2007-03-09 2007-03-09 試験装置
CN200780052075A CN101627446A (zh) 2007-03-09 2007-03-09 测试装置
TW097107484A TW200845019A (en) 2007-03-09 2008-03-04 Test apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/054668 WO2008126165A1 (ja) 2007-03-09 2007-03-09 試験装置

Publications (1)

Publication Number Publication Date
WO2008126165A1 true WO2008126165A1 (ja) 2008-10-23

Family

ID=39863349

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/054668 WO2008126165A1 (ja) 2007-03-09 2007-03-09 試験装置

Country Status (5)

Country Link
JP (1) JP4939428B2 (ja)
KR (1) KR101055356B1 (ja)
CN (1) CN101627446A (ja)
TW (1) TW200845019A (ja)
WO (1) WO2008126165A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012104204A (ja) * 2010-11-11 2012-05-31 Advantest Corp 試験装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101522293B1 (ko) * 2013-08-29 2015-05-21 주식회사 유니테스트 복수개의 스토리지를 개별 제어 가능한 테스트 장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02275545A (ja) * 1989-04-17 1990-11-09 Mitsubishi Electric Corp データ処理システム
JP2002288999A (ja) * 2001-03-27 2002-10-04 Fujitsu Ltd 半導体メモリ
JP2003036681A (ja) * 2001-07-23 2003-02-07 Hitachi Ltd 不揮発性記憶装置
JP2003141888A (ja) * 2001-11-01 2003-05-16 Mitsubishi Electric Corp 不揮発性半導体記憶装置
JP2007102832A (ja) * 2005-09-30 2007-04-19 Advantest Corp 試験装置、及び試験方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02275545A (ja) * 1989-04-17 1990-11-09 Mitsubishi Electric Corp データ処理システム
JP2002288999A (ja) * 2001-03-27 2002-10-04 Fujitsu Ltd 半導体メモリ
JP2003036681A (ja) * 2001-07-23 2003-02-07 Hitachi Ltd 不揮発性記憶装置
JP2003141888A (ja) * 2001-11-01 2003-05-16 Mitsubishi Electric Corp 不揮発性半導体記憶装置
JP2007102832A (ja) * 2005-09-30 2007-04-19 Advantest Corp 試験装置、及び試験方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012104204A (ja) * 2010-11-11 2012-05-31 Advantest Corp 試験装置

Also Published As

Publication number Publication date
TWI361435B (ja) 2012-04-01
CN101627446A (zh) 2010-01-13
KR20100005000A (ko) 2010-01-13
JPWO2008126165A1 (ja) 2010-07-15
JP4939428B2 (ja) 2012-05-23
TW200845019A (en) 2008-11-16
KR101055356B1 (ko) 2011-08-09

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