WO2008120325A1 - スイッチ、情報処理装置およびアドレス変換方法 - Google Patents

スイッチ、情報処理装置およびアドレス変換方法 Download PDF

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Publication number
WO2008120325A1
WO2008120325A1 PCT/JP2007/056695 JP2007056695W WO2008120325A1 WO 2008120325 A1 WO2008120325 A1 WO 2008120325A1 JP 2007056695 W JP2007056695 W JP 2007056695W WO 2008120325 A1 WO2008120325 A1 WO 2008120325A1
Authority
WO
WIPO (PCT)
Prior art keywords
input
address translation
switch
address
guest
Prior art date
Application number
PCT/JP2007/056695
Other languages
English (en)
French (fr)
Inventor
Tsunehisa Doi
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/056695 priority Critical patent/WO2008120325A1/ja
Priority to JP2009507317A priority patent/JP5056845B2/ja
Publication of WO2008120325A1 publication Critical patent/WO2008120325A1/ja
Priority to US12/555,343 priority patent/US8707010B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures

Abstract

　本発明は、ゲストＯＳでの入出力処理における入出力制御の負荷を軽減し、もって、ゲストＯＳ上でアプリケーションの処理性能を向上させることができるスイッチ、情報処理装置およびアドレス変換方法を提供することを目的とする。この目的を達成するため、入出力制御装置４０と入出力デバイス８０ａおよび７０ｂの間を接続するスイッチ９０ａは、入出力デバイス８０ａおよび７０ｂがゲストＯＳによってＤＭＡの転送先として指定された仮想計算機上の物理アドレスを実計算機上の物理アドレスへ変換するためのアドレス変換表９１ａを記憶する記憶部９２０と、入出力デバイス８０ａおよび７０ｂが発行したＤＭＡ要求に含まれるアドレスを、アドレス変換表９１ａを参照して実計算機上の物理アドレスへ変換するアドレス変換部９１４とを備える。
PCT/JP2007/056695 2007-03-28 2007-03-28 スイッチ、情報処理装置およびアドレス変換方法 WO2008120325A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/056695 WO2008120325A1 (ja) 2007-03-28 2007-03-28 スイッチ、情報処理装置およびアドレス変換方法
JP2009507317A JP5056845B2 (ja) 2007-03-28 2007-03-28 スイッチおよび情報処理装置
US12/555,343 US8707010B2 (en) 2007-03-28 2009-09-08 Switch, information processing apparatus, and address translation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056695 WO2008120325A1 (ja) 2007-03-28 2007-03-28 スイッチ、情報処理装置およびアドレス変換方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/555,343 Continuation US8707010B2 (en) 2007-03-28 2009-09-08 Switch, information processing apparatus, and address translation method

Publications (1)

Publication Number Publication Date
WO2008120325A1 true WO2008120325A1 (ja) 2008-10-09

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056695 WO2008120325A1 (ja) 2007-03-28 2007-03-28 スイッチ、情報処理装置およびアドレス変換方法

Country Status (3)

Country Link
US (1) US8707010B2 (ja)
JP (1) JP5056845B2 (ja)
WO (1) WO2008120325A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012133601A (ja) * 2010-12-22 2012-07-12 Nec Access Technica Ltd 情報機器制御装置、情報機器制御システムおよび情報機器の制御方法
JP2012519316A (ja) * 2009-04-06 2012-08-23 株式会社日立製作所 ストレージサブシステム、及びその制御方法
JP2018526696A (ja) * 2015-07-27 2018-09-13 グーグル エルエルシー スイッチへのアドレスキャッシュ

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6070357B2 (ja) 2013-03-28 2017-02-01 富士通株式会社 ストレージ装置
US9952979B1 (en) * 2015-01-14 2018-04-24 Cavium, Inc. Methods and systems for direct memory access operations
KR102473665B1 (ko) 2015-07-28 2022-12-02 삼성전자주식회사 스토리지 디바이스 및 스토리지 가상화 시스템
US11030144B2 (en) 2018-12-14 2021-06-08 Texas Instruments Incorporated Peripheral component interconnect (PCI) backplane connectivity system on chip (SoC)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05250251A (ja) * 1992-03-04 1993-09-28 Nec Corp 情報処理装置
JPH086893A (ja) * 1994-06-20 1996-01-12 Internatl Business Mach Corp <Ibm> マルチプル・バス情報処理システム及びブリッジ回路
JP2002304364A (ja) * 2001-03-01 2002-10-18 Internatl Business Mach Corp <Ibm> Ｐｃｉ入出力スロットの論理分割を実施する方法および装置
JP2004302922A (ja) * 2003-03-31 2004-10-28 Toshiba Corp 情報機器およびトランザクション制御方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005122640A (ja) * 2003-10-20 2005-05-12 Hitachi Ltd サーバシステム及びｉ／ｏスロット共有方法。
US7917723B2 (en) * 2005-12-01 2011-03-29 Microsoft Corporation Address translation table synchronization

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05250251A (ja) * 1992-03-04 1993-09-28 Nec Corp 情報処理装置
JPH086893A (ja) * 1994-06-20 1996-01-12 Internatl Business Mach Corp <Ibm> マルチプル・バス情報処理システム及びブリッジ回路
JP2002304364A (ja) * 2001-03-01 2002-10-18 Internatl Business Mach Corp <Ibm> Ｐｃｉ入出力スロットの論理分割を実施する方法および装置
JP2004302922A (ja) * 2003-03-31 2004-10-28 Toshiba Corp 情報機器およびトランザクション制御方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012519316A (ja) * 2009-04-06 2012-08-23 株式会社日立製作所 ストレージサブシステム、及びその制御方法
JP2012133601A (ja) * 2010-12-22 2012-07-12 Nec Access Technica Ltd 情報機器制御装置、情報機器制御システムおよび情報機器の制御方法
JP2018526696A (ja) * 2015-07-27 2018-09-13 グーグル エルエルシー スイッチへのアドレスキャッシュ

Also Published As

Publication number Publication date
US20090327645A1 (en) 2009-12-31
JP5056845B2 (ja) 2012-10-24
JPWO2008120325A1 (ja) 2010-07-15
US8707010B2 (en) 2014-04-22

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