WO2008111177A1 - 半導体装置とその製造方法 - Google Patents

半導体装置とその製造方法 Download PDF

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Publication number
WO2008111177A1
WO2008111177A1 PCT/JP2007/054974 JP2007054974W WO2008111177A1 WO 2008111177 A1 WO2008111177 A1 WO 2008111177A1 JP 2007054974 W JP2007054974 W JP 2007054974W WO 2008111177 A1 WO2008111177 A1 WO 2008111177A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
manufacturing
dummy patterns
same
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/054974
Other languages
English (en)
French (fr)
Inventor
Takashi Watanabe
Naoki Idani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Priority to PCT/JP2007/054974 priority Critical patent/WO2008111177A1/ja
Publication of WO2008111177A1 publication Critical patent/WO2008111177A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Drying Of Semiconductors (AREA)
  • Dicing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

【課題】スクラッチ等の欠陥が発生するのを抑制することが可能な半導体装置とその製造方法を提供すること。 【解決手段】シリコン基板１と、シリコン基板１の上方、又は該シリコン基板１に形成されたダミーパターン１ｂ、９ｂ、３１ｂと、少なくともダミーパターン１ｂ、９ｂ、３１ｂの側面に形成された絶縁膜４、１６、３２とを有し、ダミーパターン１ｂ、９ｂ、３１ｂの最短方向の幅Xが、該ダミーパターン１ｂ、９ｂ、３１ｂの高さaの３．５倍以上である半導体装置による。
PCT/JP2007/054974 2007-03-13 2007-03-13 半導体装置とその製造方法 Ceased WO2008111177A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/054974 WO2008111177A1 (ja) 2007-03-13 2007-03-13 半導体装置とその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/054974 WO2008111177A1 (ja) 2007-03-13 2007-03-13 半導体装置とその製造方法

Publications (1)

Publication Number Publication Date
WO2008111177A1 true WO2008111177A1 (ja) 2008-09-18

Family

ID=39759128

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/054974 Ceased WO2008111177A1 (ja) 2007-03-13 2007-03-13 半導体装置とその製造方法

Country Status (1)

Country Link
WO (1) WO2008111177A1 (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05243403A (ja) * 1992-02-28 1993-09-21 Nec Corp 半導体装置
JP2000294557A (ja) * 1999-04-05 2000-10-20 Sony Corp 研磨して使用する電子装置
JP2004265989A (ja) * 2003-02-28 2004-09-24 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05243403A (ja) * 1992-02-28 1993-09-21 Nec Corp 半導体装置
JP2000294557A (ja) * 1999-04-05 2000-10-20 Sony Corp 研磨して使用する電子装置
JP2004265989A (ja) * 2003-02-28 2004-09-24 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

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