WO2008102411A1 - 信号処理装置および方法 - Google Patents

信号処理装置および方法 Download PDF

Info

Publication number
WO2008102411A1
WO2008102411A1 PCT/JP2007/000105 JP2007000105W WO2008102411A1 WO 2008102411 A1 WO2008102411 A1 WO 2008102411A1 JP 2007000105 W JP2007000105 W JP 2007000105W WO 2008102411 A1 WO2008102411 A1 WO 2008102411A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
clock signal
signal processing
mixer
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/000105
Other languages
English (en)
French (fr)
Inventor
Daisuke Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2007/000105 priority Critical patent/WO2008102411A1/ja
Priority to JP2009500012A priority patent/JPWO2008102411A1/ja
Publication of WO2008102411A1 publication Critical patent/WO2008102411A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronizing For Television (AREA)

Abstract

　第１のミキサは、第１の入力信号と第１のクロック信号を混合して第１の出力信号を生成し、第２のミキサは、第２の入力信号と第２のクロック信号を混合して第２の出力信号を生成する。クロック回路は、第１のクロック信号を第１のミキサに出力し、第１のクロック信号に対して位相差９０度だけ遅れたクロック信号を第２のクロック信号として第２のミキサに出力する第１の動作と、第１のクロック信号を第１のミキサに出力し、第１のクロック信号に対して位相差９０度だけ進んだクロック信号を第２のクロック信号として第２のミキサに出力する第２の動作とを、制御信号の値に応じて切り替える。
PCT/JP2007/000105 2007-02-20 2007-02-20 信号処理装置および方法 Ceased WO2008102411A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2007/000105 WO2008102411A1 (ja) 2007-02-20 2007-02-20 信号処理装置および方法
JP2009500012A JPWO2008102411A1 (ja) 2007-02-20 2007-02-20 信号処理装置および方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000105 WO2008102411A1 (ja) 2007-02-20 2007-02-20 信号処理装置および方法

Publications (1)

Publication Number Publication Date
WO2008102411A1 true WO2008102411A1 (ja) 2008-08-28

Family

ID=39709696

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000105 Ceased WO2008102411A1 (ja) 2007-02-20 2007-02-20 信号処理装置および方法

Country Status (2)

Country Link
JP (1) JPWO2008102411A1 (ja)
WO (1) WO2008102411A1 (ja)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157605A (en) * 1981-03-24 1982-09-29 Mitsubishi Electric Corp Calibration method of orthogonal synchronous wave detector
JPH05129839A (ja) * 1991-11-05 1993-05-25 Fujitsu Ten Ltd ダイレクトコンバージヨン受信方式を用いたラジオの発振回路
JPH0645925A (ja) * 1992-07-23 1994-02-18 Mitsubishi Electric Corp 周波数シンセサイザ
JPH11331011A (ja) * 1998-05-08 1999-11-30 Sharp Corp ダイレクトコンバージョン方式デジタルチューナ

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09247226A (ja) * 1996-03-14 1997-09-19 Hitachi Ltd 直交変調波復調装置
JP2001257538A (ja) * 2000-03-14 2001-09-21 Nippon Telegr & Teleph Corp <Ntt> 直交ミキサ回路及び複素ミキサ回路
JP4393926B2 (ja) * 2004-05-31 2010-01-06 シャープ株式会社 ミキサ回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157605A (en) * 1981-03-24 1982-09-29 Mitsubishi Electric Corp Calibration method of orthogonal synchronous wave detector
JPH05129839A (ja) * 1991-11-05 1993-05-25 Fujitsu Ten Ltd ダイレクトコンバージヨン受信方式を用いたラジオの発振回路
JPH0645925A (ja) * 1992-07-23 1994-02-18 Mitsubishi Electric Corp 周波数シンセサイザ
JPH11331011A (ja) * 1998-05-08 1999-11-30 Sharp Corp ダイレクトコンバージョン方式デジタルチューナ

Also Published As

Publication number Publication date
JPWO2008102411A1 (ja) 2010-05-27

Similar Documents

Publication Publication Date Title
TW201130229A (en) Delay locked loop and method of driving delay locked loop
TW200703337A (en) Duty cycle correction device
WO2008114446A1 (ja) クロック信号選択回路
WO2011009001A3 (en) Systems and methods for reducing average current consumption in a local oscillator path
WO2012138509A3 (en) Techniques for reducing duty cycle distortion in periodic signals
TW200636754A (en) Clock generator and clock duty cycle correction method
EP2360834A3 (en) Frequency multiplier
WO2012151313A3 (en) Apparatus and method to hold pll output frequency when input clock is lost
WO2007120957A3 (en) Dynamic timing adjustment in a circuit device
WO2010033308A3 (en) High speed pll clock multiplier
WO2007100529A3 (en) Spread-spectrum clocking
WO2010033436A3 (en) Techniques for generating fractional clock signals
WO2010047471A3 (en) Phase shifter and control method thereof
WO2008027066A3 (en) Clock and data recovery
WO2012098399A8 (en) Low-power oscillator
TW200642280A (en) Clock synthesizer and method thereof
WO2010032182A3 (en) Method of controlling a system and signal processing system
WO2013188272A3 (en) Optimizing power in a memory device
WO2011070013A3 (en) Mixer arrangement
WO2012033410A3 (en) Led driver circuit and method
TW200701647A (en) Delay locked loop circuit
WO2008027792A3 (en) Power line communication device and method with frequency shifted modem
WO2009038588A8 (en) Signal generator with adjustable phase
TW200729734A (en) Delay locked loop with selectable delay
TW200721672A (en) System and method for clock switching

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07713487

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2009500012

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07713487

Country of ref document: EP

Kind code of ref document: A1