WO2008099872A1 - Système de module de circuit intégré - Google Patents

Système de module de circuit intégré Download PDF

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Publication number
WO2008099872A1
WO2008099872A1 PCT/JP2008/052415 JP2008052415W WO2008099872A1 WO 2008099872 A1 WO2008099872 A1 WO 2008099872A1 JP 2008052415 W JP2008052415 W JP 2008052415W WO 2008099872 A1 WO2008099872 A1 WO 2008099872A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
module
power source
main
module system
Prior art date
Application number
PCT/JP2008/052415
Other languages
English (en)
Japanese (ja)
Inventor
Sadahiko Miura
Toru Mori
Koichi Takemura
Shigeyuki Iwasa
Jiro Iriyama
Yuki Kusachi
Yukiko Morioka
Kentaro Nakahara
Masahiro Suguro
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2008558112A priority Critical patent/JPWO2008099872A1/ja
Publication of WO2008099872A1 publication Critical patent/WO2008099872A1/fr

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Abstract

L'invention concerne un système de module de circuit intégré qui comprend : une première et une seconde ligne principale connectées aux deux extrémités d'une source d'alimentation principale en courant continu ; un module de circuit intégré ; une première et une seconde ligne de module connectées au module de circuit intégré ; et une source d'alimentation en courant continu distribuée agencée séparément de la source d'alimentation principale et ayant une cellule radicale organique ; et une première et une seconde ligne de distribution connectées respectivement aux deux extrémités de la source d'alimentation en courant continu distribuée. La première ligne principale est connectée à la première ligne de module et à la première ligne de distribution. La seconde ligne principale est connectée à la seconde ligne de module et à la seconde ligne de distribution.
PCT/JP2008/052415 2007-02-14 2008-02-14 Système de module de circuit intégré WO2008099872A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008558112A JPWO2008099872A1 (ja) 2007-02-14 2008-02-14 Icモジュールシステム

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007033341 2007-02-14
JP2007-033341 2007-12-05

Publications (1)

Publication Number Publication Date
WO2008099872A1 true WO2008099872A1 (fr) 2008-08-21

Family

ID=39690099

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/052415 WO2008099872A1 (fr) 2007-02-14 2008-02-14 Système de module de circuit intégré

Country Status (2)

Country Link
JP (1) JPWO2008099872A1 (fr)
WO (1) WO2008099872A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010068745A (ja) * 2008-09-18 2010-04-02 Fumakilla Ltd 送風式薬剤放散装置
JP2010075085A (ja) * 2008-09-25 2010-04-08 Fumakilla Ltd 送風式の薬剤放散装置
JP2013055874A (ja) * 2011-09-05 2013-03-21 Taida Electronic Ind Co Ltd 電気エネルギー適応制御機能を備えた太陽光発電システムおよびその制御方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0260435A (ja) * 1988-08-25 1990-02-28 Toshiba Corp バックアップ電源装置
JPH0794901A (ja) * 1993-06-30 1995-04-07 Nec Corp 素子分離型複合マイクロ波回路モジュール
JP2002261449A (ja) * 2000-12-27 2002-09-13 Matsushita Electric Ind Co Ltd 部品内蔵モジュール及びその製造方法
JP2005018825A (ja) * 2003-06-23 2005-01-20 Renesas Technology Corp 半導体記憶装置
JP2006166577A (ja) * 2004-12-07 2006-06-22 Ricoh Co Ltd 電源供給制御方法及び電源装置
JP2007037291A (ja) * 2005-07-27 2007-02-08 Nec Corp 自動車用蓄電システム

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0260435A (ja) * 1988-08-25 1990-02-28 Toshiba Corp バックアップ電源装置
JPH0794901A (ja) * 1993-06-30 1995-04-07 Nec Corp 素子分離型複合マイクロ波回路モジュール
JP2002261449A (ja) * 2000-12-27 2002-09-13 Matsushita Electric Ind Co Ltd 部品内蔵モジュール及びその製造方法
JP2005018825A (ja) * 2003-06-23 2005-01-20 Renesas Technology Corp 半導体記憶装置
JP2006166577A (ja) * 2004-12-07 2006-06-22 Ricoh Co Ltd 電源供給制御方法及び電源装置
JP2007037291A (ja) * 2005-07-27 2007-02-08 Nec Corp 自動車用蓄電システム

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010068745A (ja) * 2008-09-18 2010-04-02 Fumakilla Ltd 送風式薬剤放散装置
JP2010075085A (ja) * 2008-09-25 2010-04-08 Fumakilla Ltd 送風式の薬剤放散装置
JP2013055874A (ja) * 2011-09-05 2013-03-21 Taida Electronic Ind Co Ltd 電気エネルギー適応制御機能を備えた太陽光発電システムおよびその制御方法

Also Published As

Publication number Publication date
JPWO2008099872A1 (ja) 2010-05-27

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