WO2008096752A1 - エッチング方法および記憶媒体 - Google Patents

エッチング方法および記憶媒体 Download PDF

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Publication number
WO2008096752A1
WO2008096752A1 PCT/JP2008/051862 JP2008051862W WO2008096752A1 WO 2008096752 A1 WO2008096752 A1 WO 2008096752A1 JP 2008051862 W JP2008051862 W JP 2008051862W WO 2008096752 A1 WO2008096752 A1 WO 2008096752A1
Authority
WO
WIPO (PCT)
Prior art keywords
etching method
recording medium
plasma
fluorine
etching
Prior art date
Application number
PCT/JP2008/051862
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
Toshihisa Nozawa
Kotaro Miyatani
Toshiyasu Hori
Shigekazu Hirose
Original Assignee
Tokyo Electron Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2007123820A external-priority patent/JP4919871B2/ja
Application filed by Tokyo Electron Limited filed Critical Tokyo Electron Limited
Priority to CN2008800044252A priority Critical patent/CN101606234B/zh
Priority to KR1020097014154A priority patent/KR101179111B1/ko
Priority to US12/526,471 priority patent/US8383519B2/en
Publication of WO2008096752A1 publication Critical patent/WO2008096752A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Manufacturing Optical Record Carriers (AREA)
  • ing And Chemical Polishing (AREA)
PCT/JP2008/051862 2007-02-09 2008-02-05 エッチング方法および記憶媒体 WO2008096752A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2008800044252A CN101606234B (zh) 2007-02-09 2008-02-05 蚀刻方法及存储介质
KR1020097014154A KR101179111B1 (ko) 2007-02-09 2008-02-05 에칭 방법 및 기억 매체
US12/526,471 US8383519B2 (en) 2007-02-09 2008-02-05 Etching method and recording medium

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007031162 2007-02-09
JP2007-031162 2007-02-09
JP2007123820A JP4919871B2 (ja) 2007-02-09 2007-05-08 エッチング方法、半導体装置の製造方法および記憶媒体
JP2007-123820 2007-05-08

Publications (1)

Publication Number Publication Date
WO2008096752A1 true WO2008096752A1 (ja) 2008-08-14

Family

ID=39681661

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/051862 WO2008096752A1 (ja) 2007-02-09 2008-02-05 エッチング方法および記憶媒体

Country Status (2)

Country Link
KR (1) KR101179111B1 (ko)
WO (1) WO2008096752A1 (ko)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011023449A (ja) * 2009-07-14 2011-02-03 Renesas Electronics Corp 半導体装置
WO2015069613A1 (en) * 2013-11-06 2015-05-14 Mattson Technology, Inc. Novel mask removal process strategy for vertical nand device
CN114645281A (zh) * 2022-04-06 2022-06-21 岭南师范学院 一种褪除金属工件表面碳膜的方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6817692B2 (ja) * 2015-08-27 2021-01-20 東京エレクトロン株式会社 プラズマ処理方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0467655A (ja) * 1990-07-09 1992-03-03 Nippon Telegr & Teleph Corp <Ntt> 半導体装置およびその製造方法
JP2004530287A (ja) * 2000-12-26 2004-09-30 ハネウェル・インターナショナル・インコーポレーテッド フォトレジストとｏｓｇの間の反応を除く方法
JP2005123406A (ja) * 2003-10-16 2005-05-12 Tokyo Electron Ltd プラズマエッチング方法。
JP2005223360A (ja) * 1999-03-09 2005-08-18 Tokyo Electron Ltd 半導体装置の製造方法
JP2006302924A (ja) * 2005-04-15 2006-11-02 Hitachi High-Technologies Corp プラズマ処理方法およびプラズマ処理装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3683570B2 (ja) * 2003-02-19 2005-08-17 松下電器産業株式会社 半導体装置の製造方法
JP4715207B2 (ja) * 2004-01-13 2011-07-06 東京エレクトロン株式会社 半導体装置の製造方法及び成膜システム

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0467655A (ja) * 1990-07-09 1992-03-03 Nippon Telegr & Teleph Corp <Ntt> 半導体装置およびその製造方法
JP2005223360A (ja) * 1999-03-09 2005-08-18 Tokyo Electron Ltd 半導体装置の製造方法
JP2004530287A (ja) * 2000-12-26 2004-09-30 ハネウェル・インターナショナル・インコーポレーテッド フォトレジストとｏｓｇの間の反応を除く方法
JP2005123406A (ja) * 2003-10-16 2005-05-12 Tokyo Electron Ltd プラズマエッチング方法。
JP2006302924A (ja) * 2005-04-15 2006-11-02 Hitachi High-Technologies Corp プラズマ処理方法およびプラズマ処理装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011023449A (ja) * 2009-07-14 2011-02-03 Renesas Electronics Corp 半導体装置
WO2015069613A1 (en) * 2013-11-06 2015-05-14 Mattson Technology, Inc. Novel mask removal process strategy for vertical nand device
JP2016517179A (ja) * 2013-11-06 2016-06-09 マットソン テクノロジー インコーポレイテッドＭａｔｔｓｏｎ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 垂直ｎａｎｄ素子のための新規のマスク除去方法
CN114645281A (zh) * 2022-04-06 2022-06-21 岭南师范学院 一种褪除金属工件表面碳膜的方法
CN114645281B (zh) * 2022-04-06 2023-11-24 岭南师范学院 一种褪除金属工件表面碳膜的方法

Also Published As

Publication number Publication date
KR101179111B1 (ko) 2012-09-07
KR20090094363A (ko) 2009-09-04

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