WO2008083557A1 - Procédé de correction d'erreur de codage pour secteurs multiples - Google Patents

Procédé de correction d'erreur de codage pour secteurs multiples Download PDF

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Publication number
WO2008083557A1
WO2008083557A1 PCT/CN2007/003895 CN2007003895W WO2008083557A1 WO 2008083557 A1 WO2008083557 A1 WO 2008083557A1 CN 2007003895 W CN2007003895 W CN 2007003895W WO 2008083557 A1 WO2008083557 A1 WO 2008083557A1
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WO
WIPO (PCT)
Prior art keywords
flash memory
ecc
data
bytes
byte
Prior art date
Application number
PCT/CN2007/003895
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English (en)
Chinese (zh)
Inventor
Chingyi Lin
Original Assignee
Fortune Spring Technology (Shenzhen) Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fortune Spring Technology (Shenzhen) Corporation filed Critical Fortune Spring Technology (Shenzhen) Corporation
Publication of WO2008083557A1 publication Critical patent/WO2008083557A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk

Definitions

  • the invention belongs to the field of flash memory, and proposes a new ECC architecture, which can be applied to all flash memory storage devices currently on the market.
  • This method is no longer limited to the storage mode of the traditional ECC encoding, and can improve the error correction code ( The ability to modify the ECC), especially when used in multiple flash memories that require simultaneous access, does not reduce the capacity of the flash memory storage device.
  • This method can satisfy the application of flash memory in future SSD (Solid State Disk) solid state drives. Background technique
  • flash memory has the above advantages, market acceptance and demand are rapidly expanding.
  • flash memory semiconductor technology was mainly based on Single Level Cell (SLC), and its capacity was improved by utilizing the semiconductor process technology.
  • SLC Single Level Cell
  • various flash memory manufacturers have not paid much attention to the development of process technology.
  • MLCs multiple level cells
  • LLCs multiple level cells
  • Such future capacity enhancement will not only rely on advances in process technology, but also on some aspects of analog technology.
  • the current flash memory on the market provides a 16-byte spare (Sparse) space for a 512-byte sector to store the wear leveling and ECC error correction codes.
  • the Reed-Solomon ECC can have up to 6 bytes of error correction capability if the spare space does not store the data needed for the leveling theory.
  • one sector 512 bytes
  • the conventional ECC code storage method is sufficient at this stage.
  • the efficiency of flash memory access is to be accelerated, the data of one sector is spread in two flash memories, so it is necessary to access two flash memories at the same time, so it is necessary to have an error correction capability of 8 bytes. In this way, if you access 4 flash memories at the same time, you need 16 bytes of error correction capability. It can be seen that this is not the way the traditional ECC is stored. Summary of the invention
  • the present invention utilizes a new ECC encoding storage method, which breaks through the traditional flash memory.
  • a sector can only store the ECC encoding limit by 16 bytes, and the 512-byte (sector size) + 16-byte (ECC-encoded) architecture is used. Upgrade to (N*512+N*16) bytes of architecture.
  • This architecture allows N sectors to share a set of ECC codes and increase the length of the ECC code to improve the error correction capability of the ECC.
  • the first byte of the data will be written to the first flash memory, and the second byte of the data will be written.
  • Two flash memories three bytes will be written to the first flash memory, and the fourth byte will be written to the second flash memory until all data is written.
  • the first byte of the ECC error correction code will be written to the first flash memory
  • the second byte of the ECC error correction code will be written to the second flash memory
  • the third byte will be written to the first In the flash memory
  • the fourth byte is written to the second flash memory until all ECC error correction codes are written.
  • the first byte of the data will be written to the (1%M) flash memory, the second word of the data.
  • the section will be written to the (2%M) flash memory, and the third byte will be written to the (3%M) flash memory, the Nth word.
  • the section is written to the (N%M)th flash memory until all data (length 512*N bytes) is written.
  • the first byte of the ECC error correction code will be written to the first (1%M) flash memory, and the second two bytes of the ECC error correction code will be written to the (2%M) flash memory.
  • the byte will be written to the (3%M) flash memory, and the Nth byte will be written to the (N%M) flash memory until all ECC error correction codes (length 16*N words) Section) until the writing is completed.
  • Figure 1 System architecture diagram.
  • FIG. 1 Traditional ECC code placement.
  • Figure 5 Schematic of the N sector.
  • Figure 6 ECC coded placement with sector 2 and flash memory number 2.
  • Figure 7 ECC coded placement with sector 3 and flash memory number 3.
  • Figure 8 ECC code placement when N sector and flash memory number is M.
  • Figure 9 Flow when reading flash memory.
  • Figure 10 Flow when writing to flash memory.
  • Flash memory controller The center of work, coordinating all actions.
  • the DMA controller moves the data from the buffer to the flash memory or from the flash memory to the buffer without the intervention of the CPU, which saves system resources and increases performance.
  • Flash memory The space for data storage is non-volatile, permanently saved memory.
  • the flash memory controller When the DMA controller finishes moving the general data, the flash memory controller notifies the ECC controller to take over the DMA and perform ECC encoding control.
  • the ECC controller acts on the buffer. When reading, the data encoded in the ECC code in the flash memory is read to judge the integrity of the data. When the data in the buffer is detected to be wrong, the error correction is performed and the data is corrected. Does not work when writing.
  • ECC controller Perform ECC encoding, detection, and correction actions.
  • the ECC controller clears the internal check code to 0, and the English name of this check code is Syndrome Bits.
  • the system then starts the DMA controller and reads the data from the flash memory.
  • the first byte is read by the first flash memory, the second byte is read by the second flash memory, and so on.
  • the Xth byte is read by the XMth flash memory.
  • the total read length is N* ( 512+16 ) bytes, but only N*512 bytes will be moved to the buffer memory (Buffer), and the remaining N* 16 bytes are only the error correction code for checking, so It does not have to be moved to the buffer (Buffer).
  • the detection circuit in the ECC controller monitors all the data on the data bus in real time, and updates the internal inspection in time. Check the code.
  • the ECC controller checks whether the internal check code is 0. If it is 0, it indicates that all transmitted data is correct, and the flash memory controller is notified that the reading operation has been successful. If the result is not 0, the internal correction circuit is started, the erroneous data is searched through the positive circuit, and the erroneous data is repaired, and the location of the error and the correct data are used to modify the buffer. data. If it cannot be repaired, the flash memory controller is notified, the data is incorrect and cannot be repaired.
  • the ECC controller When the data of N sectors is to be written to M flash memory, as shown in Figure 10, the ECC controller first clears the internal check code to 0.
  • the English name of this check code is Parity Bits.
  • the DMA controller transfers the data in the buffer (N*512) bytes to the flash memory via the data bus. The first byte of data is transferred to the first flash memory, the second byte of data is transferred to the second flash memory, and so on, the Xth byte of the data is transferred To the X%M flash memory.
  • the ECC controller While the data is being written, the ECC controller also monitors the data on the data bus in real time and updates the check code inside the controller.
  • the ECC controller writes the check code inside the ECC to the flash memory.
  • the first check code is written to the first flash memory
  • the second check code is written to the second flash memory
  • the Xth check code is written to the X%M flash memory.
  • the invention utilizes the new ECC encoding storage method, breaks through the traditional flash memory, and can only use 16 bytes to store the ECC encoding limit, and the 512-byte (sector size) + 16-byte (ECC encoding) architecture is improved.
  • the architecture is (N*512+N*16) bytes. This architecture allows N sectors to share a set of ECC codes and increase the length of the ECC code to improve the error correction capability of the ECC.
  • N 2
  • the flash memory provides a 16-byte Sparc area for each sector, so the Spare area of two sectors can have up to 32 bytes. According to the Reed-Solomon ECC algorithm theory, 32 bytes can provide 11 bytes of error correction for two sectors of data.
  • N 3, as shown in Fig. 4, there may be 48 bytes for storing the ECC encoded space, which can provide 17 bytes of error correction capability. Therefore, the larger the N is, the stronger the error correction capability that can be provided.
  • the sector is N, as shown in Figure 5, up to 6*N- L log 2 N" bytes can be provided for error correction. And so on, when N is larger, the ECC (Error Detection Correction) is more powerful, and this method can also meet the requirements when accessing multiple flash memories simultaneously.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

Nouveau procédé servant à mémoriser le codage de ECC quand on accède à des données stockées dans une mémoire flash. Ceci consiste à élever un bloc de 512 octets (dimension du secteur) + 16 octets (codage de ECC) à un bloc de N*512+N*16. Quand N est 1, selon la théorie de l'algorithme ECC de Reed-Solomon, ce procédé peut corriger une erreur de 6 octets maximum. Quand N est 2, il peut corriger une erreur de 11 octets, comme indiqué ci-dessus, la capacité du code de correction d'erreur ECC étant d'autant plus puissante que n est plus élevé.
PCT/CN2007/003895 2006-12-29 2007-12-29 Procédé de correction d'erreur de codage pour secteurs multiples WO2008083557A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CNB200610157783XA CN100458718C (zh) 2006-12-29 2006-12-29 一种闪存存储装置及其数据读取和写入方法
CN200610157783.X 2006-12-29

Publications (1)

Publication Number Publication Date
WO2008083557A1 true WO2008083557A1 (fr) 2008-07-17

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WO (1) WO2008083557A1 (fr)

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CN100458718C (zh) * 2006-12-29 2009-02-04 福昭科技（深圳）有限公司 一种闪存存储装置及其数据读取和写入方法
US8234539B2 (en) * 2007-12-06 2012-07-31 Sandisk Il Ltd. Correction of errors in a memory array
CN101246742B (zh) * 2008-03-25 2010-06-16 威盛电子股份有限公司 电子装置与其数据传输方法
CN101752010B (zh) * 2008-12-01 2013-01-09 创惟科技股份有限公司 闪存控制器及设定闪存的错误修正码容量的方法
CN101853212B (zh) * 2009-03-30 2012-11-14 芯邦科技（深圳）有限公司 数据写入方法、数据读取方法和数据存储器
CN101996688B (zh) * 2009-08-31 2013-03-06 银灿科技股份有限公司 应用可变动错误更正码容量的快闪存储器控制方法
CN103329103B (zh) * 2010-10-27 2017-04-05 希捷科技有限公司 使用用于基于闪存的数据存储的自适应ecc技术的方法和设备
CN102063342A (zh) * 2010-12-28 2011-05-18 深圳市江波龙电子有限公司 一种闪存存储设备数据的管理方法及系统
CN102081970B (zh) * 2010-12-31 2012-12-19 成都市华为赛门铁克科技有限公司 纠错处理的方法、装置及固态硬盘设备
JP6227616B2 (ja) * 2015-10-23 2017-11-08 ファナック株式会社 通信システム
CN108073473A (zh) * 2018-01-12 2018-05-25 江苏华存电子科技有限公司 一种闪存坏列表压缩方法
CN111863080A (zh) * 2020-07-08 2020-10-30 上海威固信息技术股份有限公司 一种基于层间差异的3d闪存读性能优化方法

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US6684289B1 (en) * 2000-11-22 2004-01-27 Sandisk Corporation Techniques for operating non-volatile memory systems with data sectors having different sizes than the sizes of the pages and/or blocks of the memory
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CN101000569A (zh) * 2006-12-29 2007-07-18 福昭科技（深圳）有限公司 一种对多重扇区进行错误修正编码的方法
WO2007137013A2 (fr) * 2006-05-17 2007-11-29 Sandisk Corporation Codage de correction d'erreurs pour pages à secteurs multiples dans des dispositifs de mémoire flash

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