WO2008082894A1 - Commande de tension de polarisation de ligne de bits - Google Patents

Commande de tension de polarisation de ligne de bits Download PDF

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Publication number
WO2008082894A1
WO2008082894A1 PCT/US2007/087299 US2007087299W WO2008082894A1 WO 2008082894 A1 WO2008082894 A1 WO 2008082894A1 US 2007087299 W US2007087299 W US 2007087299W WO 2008082894 A1 WO2008082894 A1 WO 2008082894A1
Authority
WO
WIPO (PCT)
Prior art keywords
control signal
bitline
bitline bias
bias control
circuit
Prior art date
Application number
PCT/US2007/087299
Other languages
English (en)
Inventor
Feng Pan
Trung Pham
Original Assignee
Sandisk Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/617,514 external-priority patent/US20080158972A1/en
Priority claimed from US11/617,531 external-priority patent/US7529135B2/en
Application filed by Sandisk Corporation filed Critical Sandisk Corporation
Publication of WO2008082894A1 publication Critical patent/WO2008082894A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits

Definitions

  • the present invention relates generally to programmable memory devices. More particularly, the present invention relates to a biasing circuit for non- volatile memory devices.
  • Non-volatile memory devices and particularly FLASH memory devices, rely upon sense amplifiers to ascertain the programming state of the various memory cells by sensing a change, if any, in either a bitline voltage or current during a read or verify operation.
  • a bitline bias (of approximately 1.0V) is applied to the bitline prior to the initiation of the read/verify operation.
  • the bitline voltage is generated by a bitline bias voltage generator circuit, which includes a current source that generates a pre-determined current I REF (I REF may be on the order of lO ⁇ A) using a charge pump to provide the necessary supply voltage V DD (generally 5V).
  • Typical charge pumps are not very efficient, and consequently, the charge pump may consume a current of much greater than that of lOuA from the chip power supply in order to provide an I REF of only lO ⁇ A. Therefore, as a result of the large number of bitlines in a typical FLASH memory device (on the order of 128K), the charge pumps used to generate the bitline bias voltages alone can account for up to 15% of the total power requirement of the FLASH memory device.
  • one embodiment of the invention includes the following steps: sensing a bitline bias control signal associated with a bitline; if the sensed bitline bias control signal indicates that the bitline is coupling low, then determining if the sensed bitline bias control signal is less than a first reference value; modifying the bitline bias control signal when the sensed bitline bias control signal is greater than a first reference value; if the sensed bitline bias control signal indicates that the bitline is coupling high, then determining if the sensed bitline bias control signal is greater than a second reference value; and modifying the bitline bias control signal when the sensed bitline bias control signal is greater than a second reference value.
  • bitline bias voltage As a method of controlling a bitline bias voltage, one embodiment of the invention includes the following steps: sensing the bitline bias voltage; modifying a bitline bias control signal in accordance with the sensed bitline bias voltage; and controlling the bitline bias voltage in accordance with the modified bitline bias control signal.
  • the bitline is connected to non-volatile memory cells arranged to form a non- volatile memory array suitable for storing data.
  • the nonvolatile memory array is arranged in a NAND-type memory array architecture having a number of wordlines and bitlines.
  • the described method is contemplated for use on a multilevel type memory array that when programmed stores data in the form of at least one lower page and at least one associated upper page.
  • one embodiment of the invention includes the following: a detector for sensing a bitline bias control signal associated with the bitline bias voltage of a bitline that generates a first control signal if the sensed bitline bias control signal indicates that the bitline is coupling low and is less than a first reference value and generates a second control signal if the sensed bitline bias control signal indicates that the bitline is coupling high and is greater than a second reference value; and a bitline bias control signal modification circuit coupled to the detector that modifies the bitline bias control signal in accordance with the first control signal and modifies the bitline bias control signal in accordance with the second control signal.
  • an apparatus for controlling a bitline bias voltage includes a detector for sensing the bitline bias voltage; a bitline bias control signal generation circuit coupled to the detector for generating a bitline bias control signal in accordance with the sensed bitline bias voltage; and a bitline bias voltage controller unit for controlling the bitline bias voltage in accordance with the bitline bias control signal.
  • the bitline is connected to non-volatile memory cells arranged to form a non- volatile memory array suitable for storing data.
  • the nonvolatile memory array is arranged in a NAND-type memory array architecture having a number of wordlines and bitlines. Additionally, the described method is contemplated for use on a multilevel type memory array that when programmed stores data in the form of at least one lower page and at least one associated upper page.
  • FIG. 1 illustrates a representative circuit for generating a bitline bias voltage control signal according to an embodiment of the present invention.
  • FIG. 2 illustrates a particular implementation of the circuit for generating a bitline bias voltage control signal shown in Fig. 1 according to an embodiment of the present invention.
  • FIGS. 3A-3B show a flowchart illustrating a method of generating a bias voltage control signal according to an embodiment of the present invention.
  • like reference numerals designate like structural elements. Also, it should be understood that the depictions in the figures are not to scale.
  • the method of the present invention is described in relation to a non- volatile memory storage system, and particularly, in relation to a FLASH memory device comprising an array of memory cells organized into an array of memory strings, each memory string comprising one or more memory cells.
  • V READ may be on the order of IV. Unselected bitlines are often grounded.
  • the wordline coupled with the control gate terminal of the selected memory cell is generally raised to a positive voltage V SEL , although in some operations, the wordline may be grounded.
  • V SEL is set so as to be in between the programmed (generally positive) and non-programmed/erased (generally negative) gate threshold voltages.
  • Wordlines corresponding to unselected memory cells on the same string as the selected memory cell may be biased to a pass voltage, V PASS , such that the unselected memory function to pass the bitline voltage to the drain of the selected memory cell.
  • V PASS pass voltage
  • the current, I DS running from the drain terminal to the source terminal of the selected memory cell will vary depending upon V READ , V SEL and the threshold voltage, V T , of the memory cell; the threshold voltage being a direct indication of the logic state stored by the memory cell.
  • the current I DS (if any), also flows through the bitline, and additionally, through a sense amplifier coupled with the bitline.
  • the voltage V SEL applied to the gate of the selected memory cell will either be sufficient to turn on the memory cell such that it becomes conducting, or will be insufficient to turn on the selected memory cell leaving the selected memory cell in a non-conducting state.
  • the sense amplifier is configured to detect a current rather than a change in bitline voltage. If the memory cell does turn on, the bitline associated with the selected memory cell will discharge and the sense amplifier will sense a change in voltage. The change in voltage detected by the sense amplifier (or alternatively the magnitude of the current detected) is indicative of the logic state of the memory cell.
  • the transconductance of the memory cell is a function of the threshold voltage V T of the memory cell and the voltage V SEL applied to the gate, the current passing through the sense amplifier, and therefore the change in voltage sensed by the amplifier, will vary according to the threshold voltage of the memory cell.
  • the sense amplifier is able to discern the programmed threshold voltage from the overall change in bitline voltage, and subsequently, the system is able to ascertain the logic state of the memory cell.
  • the voltages V SEL and V BL should be carefully controlled, especially for multi-bit memory cells.
  • the present invention relies upon current sensing in order to avoid varying of the bitline voltage such that any capacitive current does not interfere with the actual cell current thereby avoiding any read/verify errors.
  • a potential bitline voltage level variation based upon operations may be sub-divided into four distinct regions. It should be noted that this subdivision is intended for descriptive purposes only.
  • Region 1 is a voltage-settling region in which the bitline may be pre-charged from a starting pre-read or pre-verify voltage level up to a desired read or verify voltage level.
  • a typical starting voltage may be OV while the desired level may be IV.
  • Region 2 is characterized by a relatively stable bitline voltage at the desired level. This is the region that sensing operation has not start.
  • Region 3 results from the bitline coupling low, that is, the bitline bias voltage level has fallen due to discharging as a result of a read/verify operation.
  • Discharging may additionally be extended as a result of capacitive coupling between the memory cell and the bitline, and particularly, between the gate and source terminals of the memory cell. Furthermore, when memory cells are arranged in a string, capacitive coupling may exist between the bitline and all of the memory cells on the string, not just the selected memory cell. Lastly, region 4 results from the bitline coupling high. During this region, the bitline is charged by the supply to prepare for the next sensing. Charging may also result through capacitive coupling between the memory cell(s) and the bitline. It should be appreciated that these coupling capacitors (particularly between gate and source terminals) may store a significant amount of charge, which may lead to increased bitline charging and discharging times and bitline biasing control signal setting time.
  • the circuit 100 illustrated in FIG. 1 is a bitline bias control signal generation circuit arranged to provide control of the biasing of a bitline (not shown) in accordance with an embodiment of the invention. It should be noted that the circuit 100 provides improvements in regulating the bitline voltage resulting in better noise margin, reduced settling time and improved stability immediately prior to and after a read/verify operation of a selected memory cell. Circuit 100 includes a pull-up circuit 102 and a pull-down circuit 104 that in cooperation with each other affect a bitline biasing control signal 106. Circuit 100 also includes a detector 108 having an input arranged to monitor bitline biasing control signal 106.
  • the detector 108 can adjust the delta V values based upon known bitline operations in advance described in more detail in co- pending U.S. Patent Application No. that is incorporated by reference in its entirety for all purposes.
  • Detector 108 is further configured to enable the pull-up circuit 102 and disable the pull-down circuit 104 when the bitline biasing control signal 106 is low (as in region 3 described above).
  • the detector 108 enables the pull-up circuit 102 and disables the pull-down circuit 104 by outputting a first pull-up signal when the bitline biasing control signal 106 indicates that a bitline bias voltage falls below a first reference voltage.
  • the first reference voltage may be obtained by subtracting a first threshold voltage V TLOW from the desired read/verify bitline bias voltage.
  • a suitable first threshold voltage V TLOW may be approximately 1OmV for a desired read/verify bitline bias voltage.
  • detector 108 is further configured to enable the pull-down circuit 104 and disable the pull-up circuit 102 when the bitline biasing control signal 106 indicates that the bitline bias voltage is being coupled high during bitline recovery, such as in region 4 described above.
  • the detector 108 enables the pull-down circuit 104 and disables the pull-up circuit 102 by outputting a second pulldown signal when the bitline biasing control signal 106 indicates that the bitline bias voltage rises above a second reference voltage.
  • the second reference voltage may be obtained by adding a second threshold voltage V THIGH to the desired read/verify bitline bias voltage.
  • a suitable second threshold voltage V THIGH may be approximately 1OmV.
  • FIG. 2 illustrates a circuit 200 as one particular embodiment of the bitline biasing control signal circuit illustrated in FIG. 1.
  • the circuit 200 includes a diode-connected NMOS transistor 201, a second NMOS transistor 202, resistive elements 206 and 208, and a current source 204 coupled with a supply voltage V DD that generates a current I REF (I REF may be on the order of lO ⁇ A).
  • the circuit 200 also includes the detector 108. Again, detector 108 is configured to detect the voltage level of the bitline biasing control signal 106. A more detailed description of the detector
  • the detector 108 is presented in co-pending Patent Application No. , which is incorporated by reference herein in its entirety.
  • the detector 108 is coupled with a control gate of a pull-up transistor 220 and a control gate of a pull-down transistor 222.
  • pull-up transistor 220 is a PMOS transistor and pull-down transistor 222 is an NMOS transistor.
  • Vcc may be approximately 1.8V.
  • the charge pump is used to ramp up the chip power supply voltage Vcc to the supply voltage V DD , which is typically 5V.
  • Vcc the supply voltage
  • V DD the supply voltage
  • Typical charge pumps are less efficient, and consequently, the charge pump may consume much higher amount of current from the chip power supply in order to provide an I REF of only lO ⁇ A.
  • the source of pull-up transistor 220 is coupled to the supply voltage V DD , while the drain of pull-up transistor 220 is connected with the drain of transistor 202. If the detector 108 senses that the voltage level on the bitline biasing control signal 106 is below the first reference voltage level, the pull-up signal is output from the detector 108 to the control gates of pull-up transistor 220 and pull-down transistor 222. The pull-up signal is sufficient to turn on pull-up transistor 220 thereby providing a current path from the bitline biasing power supply V DD to the bitline biasing control signals.
  • the pull-up signal also turns off the pull-down transistor 222 (if not already off) thereby preventing any current flow from the bitline biasing control signal 106 through the resistor and subsequently to ground.
  • the pull-up signal has the effect of raising the voltage level on the bitline biasing control signal 106.
  • the voltage level on the bitline biasing control signal 106 rises to the first reference voltage level (i.e. within V TLOW of the desired read/verify voltage V READ )
  • the pull-up signal is terminated.
  • the source of pull-down transistor 222 is coupled to ground, while the drain of pull-down transistor 222 is coupled with resistive element 208, which is coupled with the bitline biasing control signal 106. If the detector 108 senses that the voltage level on the bitline biasing control signal 106 is above the second reference voltage level, the pulldown signal is output from the detector 108 to the control gates of pull-up transistor 220 and pull-down transistor 222. The pull-down signal is sufficient to turn on pull-down transistor 222 thereby providing a current path from the bitline biasing control signal through the resistor and subsequently to ground.
  • the pull-down signal also turns off the pull-up transistor 220 (if not already off) thereby preventing any current flow from the bitline biasing power supply to the bitline biasing control signal.
  • the pull-down signal has the effect of lowering the voltage level on the bitline biasing control signal.
  • bitline biasing control circuit 200 may be present. As these elements are not necessary to implement the present invention, they have not been described here. Moreover, it should be noted that the conductivity types of the transistors described in biasing circuit 200 may be reversed such that the NMOS transistors become PMOS transistors and vice versa. In this embodiment, various biases are also reversed.
  • FIGS. 3 A and 3B show a flowchart illustrating a method of providing a bitline biasing control signal according to various embodiments of the present invention.
  • the voltage level on the bitline biasing control signal is biased to a desired read/verify voltage.
  • the bitline may be biased to a V READ of approximately IV.
  • the bitline biasing control signal voltage is sensed and compared with a desired read/verify voltage.
  • bitline biasing control signal voltage level is below a first reference voltage level.
  • this first reference voltage level is obtained by subtracting a threshold voltage, V TLOW , from the desired read/verify voltage level V READ -
  • V TLOW may be 1OmV. If it is determined that the bitline biasing control signal voltage level is still above the first reference voltage level, then the operation returns to step 304. If it is determined that the bitline biasing control signal voltage level is below the first reference level, then at step 310 the pull-down circuit is disabled (if it is not already disabled).
  • step 312 the pull-up circuit is enabled, which results in raising the bitline biasing control signal voltage level.
  • the operation then proceeds back to step 304, where the bitline biasing control signal voltage is sensed again.
  • step 304 the bitline biasing control signal voltage is sensed again.
  • the method proceeds according to FIG. 3B where the bitline biasing control signal voltage is sensed at 314.
  • bitline biasing control signal voltage is sensed at 314.
  • this second reference voltage level is obtained by adding a threshold voltage, V THIGH , to the desired read/verify voltage level V READ -
  • V THIGH may be 1OmV.

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Abstract

L'invention concerne une commande de tension de polarisation de ligne de bits par la détection de la tension de polarisation de ligne de bits, la modification d'un signal de commande de polarisation de ligne de bits en fonction de la tension de polarisation de ligne de bits détectée, et la commande de tension de polarisation de ligne de bits en fonction du signal de commande de polarisation de ligne de bits modifié. La modification du signal de commande de polarisation de ligne de bits est effectuée par l'activation d'un circuit d'excursion haute et désactivation d'un circuit d'excursion basse, en réponse à un premier signal de commande, et par la désactivation du circuit d'excursion haute et l'activation du circuit d'excursion basse, en réponse à un second signal de commande.
PCT/US2007/087299 2006-12-28 2007-12-12 Commande de tension de polarisation de ligne de bits WO2008082894A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/617,514 US20080158972A1 (en) 2006-12-28 2006-12-28 Method of controlling bitline bias voltage
US11/617,531 US7529135B2 (en) 2006-12-28 2006-12-28 Apparatus for controlling bitline bias voltage
US11/617,514 2006-12-28
US11/617,531 2006-12-28

Publications (1)

Publication Number Publication Date
WO2008082894A1 true WO2008082894A1 (fr) 2008-07-10

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PCT/US2007/087299 WO2008082894A1 (fr) 2006-12-28 2007-12-12 Commande de tension de polarisation de ligne de bits

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TW (1) TW200842892A (fr)
WO (1) WO2008082894A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0321226A1 (fr) * 1987-12-18 1989-06-21 Kabushiki Kaisha Toshiba Circuit générateur d'un potentiel intermédiaire entre un potentiel d'alimentation et un potentiel de masse
US4943945A (en) * 1989-06-13 1990-07-24 International Business Machines Corporation Reference voltage generator for precharging bit lines of a transistor memory
US6535427B1 (en) * 1999-11-12 2003-03-18 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device with initialization circuit and control method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0321226A1 (fr) * 1987-12-18 1989-06-21 Kabushiki Kaisha Toshiba Circuit générateur d'un potentiel intermédiaire entre un potentiel d'alimentation et un potentiel de masse
US4943945A (en) * 1989-06-13 1990-07-24 International Business Machines Corporation Reference voltage generator for precharging bit lines of a transistor memory
US6535427B1 (en) * 1999-11-12 2003-03-18 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device with initialization circuit and control method thereof

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TW200842892A (en) 2008-11-01

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