WO2008082244A1 - Dispositif émettant de la lumière semi-conducteur de nitrure iii - Google Patents

Dispositif émettant de la lumière semi-conducteur de nitrure iii Download PDF

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Publication number
WO2008082244A1
WO2008082244A1 PCT/KR2007/007060 KR2007007060W WO2008082244A1 WO 2008082244 A1 WO2008082244 A1 WO 2008082244A1 KR 2007007060 W KR2007007060 W KR 2007007060W WO 2008082244 A1 WO2008082244 A1 WO 2008082244A1
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nitride semiconductor
layer
type nitride
type
light emitting
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PCT/KR2007/007060
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English (en)
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Eun Hyun Park
Soo Kun Jeon
Jae Gu Lim
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Epivalley Co., Ltd.
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Publication of WO2008082244A1 publication Critical patent/WO2008082244A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to a Ill-nitride semiconductor light emitting device, and more particularly, to a Ill-nitride semiconductor light emitting device, wherein one or more anisotropic conductive layers for effectively improving a lateral current conductivity are inserted between a substrate and an active layer for generating light by recombination of electrons and holes so as to improve a current spreading in the lateral direction of the device.
  • the Ill-nitride semiconductor light emitting device means a light emitting device such as a light emitting diode including a compound semiconductor layer composed of AI( X )Ga(y)ln(i -x .
  • y may further include a material composed of other group elements, such as SiC, SiN, SiCN and CN, and a semiconductor layer made of such materials.
  • FIG. 1 is a view illustrating one example of a conventional Ill-nitride semiconductor light emitting device.
  • the Ill-nitride semiconductor light emitting device includes a substrate 100, a buffer layer 200 epitaxially grown on the substrate 100, an n-type nitride semiconductor layer 300 epitaxially grown on the buffer layer 200, an active layer 400 epitaxially grown on the n- type nitride semiconductor layer 300, a p-type nitride semiconductor layer 500 epitaxially grown on the active layer 400, a p-side electrode 600 formed on the p-type nitride semiconductor layer 500, a p-side bonding pad 700 formed on i the p-side electrode 600, an n-side electrode 800 formed on the n-type nitride semiconductor layer exposed by mesa-etching the p-type nitride semiconductor layer 500 and the active layer 400, and a protective film 900.
  • a GaN substrate can be used as a homo-substrate, and a sapphire substrate, a SiC substrate or a Si substrate can be used as a hetero-substrate.
  • a SiC substrate or a Si substrate can be used as a hetero-substrate.
  • any type of substrate that can grow a nitride semiconductor layer thereon can be employed.
  • the SiC substrate is used, the n-side electrode 800 can be formed on the side of the SiC substrate.
  • the nitride semiconductor layers epitaxially grown on the substrate 100 are grown usually by metal organic chemical vapor deposition (MOCVD).
  • the buffer layer 200 serves to overcome differences in lattice constant and thermal expansion coefficient between the hetero-substrate 100 and the nitride semiconductor layers.
  • U.S. Pat. No. 5,122,845 discloses a technique of growing an AIN buffer layer with a thickness of 100 to 500 A on a sapphire substrate at 380 to 800 0 C.
  • U.S. Pat. No. 5,290,393 discloses a technique of growing an AI( X )Ga(i -X )N (0 ⁇ x ⁇ 1) buffer layer with a thickness of 10 to 5000 A on a sapphire substrate at 200 to 900 0 C.
  • PCT Publication No. WO/2017053042 discloses a technique of growing a SiC buffer layer (seed layer) at 600 to 990 0 C, and growing an ln( X )Ga ( i -X )N (0 ⁇ x ⁇ 1) thereon.
  • the n-side electrode 800 formed region is doped with a dopant.
  • the n-type contact layer is made of GaN and doped with Si.
  • U.S. Pat. No. 5,733,796 discloses a technique of doping an n-type contact layer at a target doping concentration by adjusting the mixture ratio of Si and other 5 source materials.
  • the active layer 400 generates light quanta (light) by recombination of electrons and holes. Normally, the active layer 400 contains ln( X) Ga(i -X )N (0 ⁇ x ⁇ 1) and has single or multi-quantum well layers.
  • PCT Publication No. WO/02/021121 discloses a technique of doping some portions of a plurality of i o quantum well layers and barrier layers.
  • the p-type nitride semiconductor layer 500 is doped with an appropriate dopant such as Mg, and provided with p-type conductivity by an activation process.
  • an appropriate dopant such as Mg
  • U.S. Pat. No. 5,247,533 discloses a technique of activating a p-type nitride semiconductor layer by electron beam irradiation.
  • U.S. Pat. No. 5,247,533 discloses a technique of activating a p-type nitride semiconductor layer by electron beam irradiation.
  • No. 5,306,662 discloses a technique of activating a p-type nitride semiconductor layer by annealing over 400 0 C.
  • PCT Publication No. WO/2017022655 discloses a technique of endowing a p-type nitride semiconductor layer with p-type conductivity without an activation process, by using ammonia and a hydrazine-based source material together as a nitrogen
  • the p-side electrode 600 is provided to facilitate current supply to the whole p-type nitride semiconductor layer 500.
  • U.S. Pat.. No. 5,563,422 discloses a technique associated with a light transmitting electrode composed of Ni and Au and formed almost on the entire surface of the p-type nitride semiconductor layer 500 in ohmic-contact with the p-type nitride semiconductor layer 500.
  • U.S. Pat. No. 6,515,306 discloses a technique of forming an n-type superlattice layer on a p-type nitride semiconductor layer, and forming a light transmitting electrode made of ITO thereon.
  • the light transmitting electrode 600 can be formed thick not to transmit but to reflect light toward the substrate 100.
  • This technique is called a flip chip technique.
  • U.S. Pat. No. 6,194,743 discloses a technique associated with an electrode structure including an Ag layer with a thickness over 20 nm, a diffusion barrier layer covering the Ag layer, and a bonding layer containing Au and Al, and covering the diffusion barrier layer.
  • the p-side bonding pad 700 and the n-side electrode 800 are provided for current supply and external wire bonding.
  • U.S. Pat. No. 5,563,422 discloses a technique of forming an n-side electrode with Ti and Al. Unlike a vertical light emitting device, the light emitting device includes the p-side bonding pad 700 and the n-side electrode 800 which are all positioned at one side of the substrate 100. Referring to FIG. 2, as distant from the n-side electrode 800, a lateral resistance of the n-type nitride semiconductor layer 300 is increased (R(n) > R(I)). Therefore, the current are inclined to be focused about the n-side electrode 800, thereby resulting in a current crowding. When a size of the light emitting device is large and when an operation current is high, the current crowding becomes serious. [Disclosure] [Technical Problem]
  • an object of the present invention is to provide a nitride semiconductor light emitting device, wherein one or more anisotropic conductive layers having a lateral conductivity higher than a lengthwise (thin film growth direction) conductivity are inserted between a substrate and an active layer for generating light by recombination of electrons and holes so as to improve a current spreading in a lateral direction of the device.
  • FIG. 1 is a view illustrating one example of a conventional Ill-nitride semiconductor light emitting device.
  • FIG. 2 is an explanatory view illustrating a phenomenon where a current is inclined to be focus about an n-side electrode due to a lateral resistance of an n-type nitride in the conventional Ill-nitride semiconductor light emitting device.
  • FIG. 3 is a view illustrating a Ill-nitride semiconductor light emitting device according to an embodiment of the present invention.
  • FIG. 4 is an explanatory view illustrating a current spreading improved by the present invention.
  • FIG. 5 is a view illustrating a method of forming an anisotropic conductive layer using a method of forming V-shaped pinholes by means of a low temperature nitride growth.
  • FIG. 6 is an SEM image after nonconductive regions are grown on a first n-type nitride layer at 750 0 C by means of the method of FIG. 5.
  • FIG. 7 is an SEM image showing a section of the device after a second n-type nitride layer is formed.
  • FIG. 8 is a view illustrating a method of forming an anisotropic conductive layer according to Embodiment 2 of the present invention.
  • FIG. 9 is a view illustrating a method of forming an anisotropic conductive layer according to Embodiment 3 of the present invention.
  • FIG. 3 is a view illustrating a Ill-nitride semiconductor light emitting device according to an embodiment of the present invention.
  • the light emitting device includes a substrate 10, a buffer layer 20 grown on the substrate 10, an n-type nitride semiconductor layer 30 epitaxially grown on the buffer layer 20 and having an anisotropic conductivity, an active layer 40 epitaxially grown on the n-type nitride semiconductor layer 30 having the anisotropic conductivity, a p-type nitride semiconductor layer 50 epitaxially grown on the active layer 40, a p-side electrode 60 formed on the p-type nitride semiconductor layer 50, a p-side bonding pad 70 formed on the p-side electrode 60, and an n-side electrode 80 formed on an n-type nitride semiconductor layer 30 exposed by mesa-etching at least the p-type nitride semiconductor layer 50 and the active layer 40.
  • the n-type nitride semiconductor layer 30 includes a first n-type nitride layer 31 on which the n- side electrode 80 is to be formed, a current showerhead layer 32 composed of nonconductive regions and conductive regions, and a second n-type nitride layer 33.
  • the nitride semiconductor layers are made of AI(x)B(y)Ga(z)ln(1 -x-y-z)N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ z ⁇ 1 , 0 ⁇ x+y+z ⁇ 1). If necessary, each layer may be formed of a single layer or a plurality of layers with different element ratios.
  • the first n-type nitride layer 31 is made of AI(x)B(y)Ga(z)ln(1-x-y-z)N (0 ⁇ x ⁇ 1 , 0 ⁇ y ⁇ 1 , 0 ⁇ z ⁇ 1, 0 ⁇ x+y+z ⁇ 1), and may have an electron concentration between 1 ⁇ 10 16 and 5x10 19 cm "3 and a thickness between 50 nm and 10 ⁇ m.
  • an electron concentration below 1x10 16 cm '3 is not preferable because an ohmic electrode is not easily formed and a lateral resistance is raised.
  • a high concentration silicon should be doped on the nitride.
  • cracks may be formed in the thin film due to a stress, and the quality of the thin film may be degraded sharply.
  • the thickness of the first n-type nitride layer 31 is below 50 nm, a lateral current spreading is weakened due to a high lateral resistance, and if the thickness is over 10 ⁇ m, cracks or bending of the substrate is accelerated due to a stress of the thin film caused by lattice mismatching with the substrate, thereby complicating a process.
  • a silicon element is used as a dopant.
  • the first n-type nitride layer 31 serves to form the n-side electrode 80 thereon and to perform a lateral (x, y) current spreading of electrons.
  • the current showerhead layer 32 formed on the first n-type nitride layer 31 is composed of n-type nitride regions that are relatively high electric conductivity regions 32-A, and relatively low electric conductivity regions 32-B.
  • the regions 32-A, through which electrons pass, may have an electron concentration between 1x10 16 and 1x10 20 cm “3 by means of n-type doping, a lengthwise thickness between 10 nm and 1 ⁇ m, a lateral area between 100 nm 2 and 100 ⁇ m 2 as an average lengthwise area, and a density between 5x10 5 and 10 11 cm '2 .
  • the current showerhead layer 32 can be relatively thinned unlike the n-type nitride layer 31. Therefore, even if the doping concentration is increased to 1x10 20 cm “3 , the quality of the thin film is not degraded. It is difficult to implement a higher doping concentration with reproducibility by a general silicon doping technique.
  • the lengthwise thickness is preferably over 10 nm to sufficiently block electrons in the nonconductive regions 32-B. If the lengthwise thickness is below 10 nm, although the regions 32-B have non-conductivity, electrons may pass therethrough due to an electron tunneling effect.
  • a thickness limit may exceed 1 ⁇ m. However, if the lengthwise thickness is over 1 ⁇ rn, a substrate bending and a dry etching defect may occur due to increase of a device growth time and an entire thin film thickness in the realistic application to the device. Accordingly, it is preferable that the lengthwise thickness is below 1 ⁇ m.
  • the average lengthwise area may be below 100 nm 2 , but is preferably over 100 nm 2 in the aspect of the realistic implementation. If the average lengthwise area is over 100 ⁇ m 2 , it is difficult to improve the current spreading remarkably.
  • the density is preferably over 5x10 5 cm "2 in consideration of the area. A density limit may exceed 10 11 cm "2 . However, it is actually difficult to implement such a high density.
  • the regions 32-A may be formed of AI(x)Ga(y)ln(1-x-y)N (0 ⁇ x ⁇ 1 , 0 ⁇ y ⁇ 1 , 0 ⁇ x+y ⁇ 1).
  • the regions 32-B may also be formed of AI(x)Ga(y)ln(1-x-y)N (0 ⁇ x ⁇ 1 , 0 ⁇ y ⁇ 1 , 0 ⁇ x+y ⁇ 1), but needs not to have the same material composition as the regions 32-A.
  • the regions 32-B, which are nonconductive regions, are defined by the regions 32-A in the structural aspect.
  • the regions 32-B may be formed of an intendedly-undoped nitride, an n-type or p-type nitride doped with a p-type dopant such as Mg, or a semi- insulating nitride doped with a dopant such as Fe and Mn.
  • a concrete forming method will be explained in detail in the following embodiments.
  • the second n-type nitride layer 33 serves to enhance the lateral spreading of the electrons once more, and may have the same conditions as the first n-type nitride layer 31. If necessary, the first n-type nitride layer 31 and the second n-type nitride layer 33 may be composed of multiple layers of different material composition or doping.
  • FIG. 4 is an explanatory view illustrating the current spreading improved by the present invention. Effectively, the first n-type nitride layer 31 and the current showerhead layer 32 constitute an anisotropic conductive layer where a lengthwise conductivity is different from a lateral conductivity.
  • the first n-type nitride layer 31 and the current showerhead layer 32 may be assumed to constitute a virtual layer, and the virtual layer may be assumed as an anisotropic conductive layer where a lengthwise electron mobility (mobility_z) is differentiated from a lateral electron mobility (mobility_x&y).
  • a lateral mobility is equal to a lengthwise mobility.
  • the lengthwise mobility mobility_z of the anisotropic conductive layer that is the virtual layer composed of the first n-type nitride layer 31 and the current showerhead layer 32 can be expressed by '(entire area of regions 32-A) / (entire area of regions 32-A + entire area of regions 32-B) x mobility_x&y'. That is, since a conductivity of a semiconductor is expressed by a multiplication of a concentration of a carrier, a mobility of the carrier and a charge amount of electrons, as the concentration and charge amount of the electrons are values fixed by a material, a mobility can be regarded as a variable.
  • a mobility of electrons is 200 cm 2 ⁇ / ⁇ s
  • an area of the regions 32-A is 400 nm 2 with a density of 10 9 cm "2
  • an area of a chip is 300x300 ⁇ m 2
  • formed is a virtual anisotropic conductive layer where a lateral mobility is 200 cm 2 ⁇ / ⁇ s and a lengthwise mobility is 0.8 cm 2 ⁇ / ⁇ s. Consequently, the lateral electron mobility is 250 times as high as the lengthwise electron mobility, so that the lateral current spreading is improved considerably.
  • Embodiment 1 a method of forming an anisotropic conductive layer and effects thereof will be explained in the following embodiments.
  • the fundamental structure is adopted from the structure of FIG. 3 in the following embodiments.
  • a concrete method of implementing an anisotropic conductive layer will be described in these embodiments.
  • Embodiment 1
  • FIG. 5 is a view illustrating a method of forming an anisotropic conductive layer using a method of forming V-shaped pinholes by means of a low temperature nitride growth.
  • a first n-type nitride layer 31 is grown, and then a nitride layer is grown at a low temperature of 600 to 900 0 C.
  • a nitride is grown at a low temperature, a lateral mobility of Ga elements is lowered, and thus high density V-shaped pinholes are formed. It is a well- known fact in the general nitride growth.
  • FIG. 5 is a view illustrating a method of forming an anisotropic conductive layer using a method of forming V-shaped pinholes by means of a low temperature nitride growth.
  • a first n-type nitride layer 31 is grown, and then a nitride layer is grown at a low temperature of 600 to 900 0 C.
  • FIG. 6 is an SEM image after nonconductive regions 32-B are grown on the first n-type nitride layer 31 at 750 0 C by means of the method of FIG. 5.
  • Regular hexagonal inverse pyramid-shaped pinholes are formed thereon with a high density. Since the low temperature nitride layer should finally obtain non- conductivity, it is preferable that a conductivity thereof is lowered as much as possible by not using a dopant or using a p-type dopant such as Mg or a semi- insulating dopant such as Mn and Fe during the growth.
  • the nitride layer is sufficiently thick to block an electron flow in a lengthwise direction. A preferable thickness thereof has been mentioned above.
  • a current block layer of about 300 nm is formed.
  • V-shaped inverse pyramid pinholes are formed by means of the low temperature growth, as a temperature is raised, a silicon-doped nitride is grown. The temperature is finally raised to a temperature between 950 and 1100 0 C, that is a normal nitride growth temperature.
  • the silicon-doped nitride is grown during the temperature raise, the lateral mobility of Ga is increased so sharply that the V-shaped pinholes can be filled with the n-type nitride, thereby planarizing the surface again.
  • regions 32-A with a conductivity are formed by means of the high temperature n-type nitride growth, and then a second n-type nitride layer 33 is formed thereon.
  • FIG. 7 is an SEM image showing a section of the device after the second n-type nitride layer 33 is formed.
  • the V-shaped grooves are normally filled with the n-type nitride.
  • an AIN layer is artificially inserted to define a boundary. While the temperature is raised or after the temperature is raised to a high temperature, the regions 32-A and the second n-type nitride layer 33 may be grown. However, in the latter, as the temperature is raised without a thin film growth, the V-shaped grooves may be possibly filled with Ga of the previously- grown regions or thin film 32-B during the temperature raise. In this case, the conductivity of the regions 32-A may be degraded seriously.
  • the concrete growth conditions of a light emitting device with an improved lateral current conductivity according to Embodiment 1 are as follows. An MOCVD is performed on C surface of a sapphire substrate that is used as a major surface, H 2 and/or N 2 are/is used as a carrier gas, and a pressure of a reactor is maintained between 100 and 500 Torr during the growth of a Ill- nitride semiconductor.
  • a GaN layer is grown on a sapphire substrate at 550 0 C as a buffer layer, and then a GaN layer is grown at 1050 °C.
  • the GaN layer is grown at 550 0 C, it is grown with a thickness of 300 A by using TMGa (50 seem) and NH 3 (15000 seem) as a source, and when the GaN layer is grown at 1050 0 C, it is grown with a thickness of 2 ⁇ m by using TMGa (250 seem) and NH 3 (18000 seem) as a source.
  • an n-type GaN layer is grown at 1050 0 C as a first n-type nitride layer 31.
  • the n-type GaN layer is grown with a thickness of 2 ⁇ m by using TMGa (250 seem) and NH 3 (18000 seem) as a source.
  • SiH 4 (8 seem) is used as an n-type dopant.
  • a temperature of a reactor is lowered to 750 0 C, and then a GaN layer 32-B with a low conductivity is grown by 300 nm at 750 0 C, having Mg- doped (100 seem) V-shaped high density pinholes.
  • a temperature of the reactor is raised to 1050 0 C, an n-type
  • GaN 32-A and 33 is grown.
  • a thickness of a second n-type nitride layer 33 is 500 nm, and SiH 4 (8 seem) is used as an n-type dopant.
  • an lno. 15 Gao. 85 N layer is grown at 800 0 C as a quantum well layer.
  • the lno. 15 Gao. 85 N layer is grown with a thickness of 25 A by using TMIn (400 seem), TMGa (30 seem) and NH 3 (28000 seem) as a source.
  • an lno.o 1 Gao. 99 N layer is grown at 900 0 C as a barrier layer.
  • the lno.o 1 Gao. 99 N layer is grown with a thickness of 100 A by using TMIn (20 seem), TMGa (30 seem) and NH3 (28000 seem) as a source.
  • a quantum well layer and a barrier layer are alternately grown three times under the above growth conditions.
  • a p-type GaN layer is grown at 1000 °C as a p-type nitride semiconductor layer.
  • the p-type GaN layer is grown with a thickness of 2000 A by using TMGa (100 seem) and NH 3 (18000 seem) as a source.
  • CP 2 Mg (500 seem) is used as a p-type dopant.
  • FIG. 8 is a view illustrating a method of forming an anisotropic conductive layer according to Embodiment 2 of the present invention.
  • Embodiment 2 employs the method of Embodiment 1 , and suggests a method of increasing a contact area of a first n-type nitride layer 31 and regions 32-A that are conductive regions.
  • an n-type nitride is grown to some extent by means of silicon doping during the initial growth, and nonconductive regions 32-B are successively grown. Therefore, as shown in FIG.
  • the n-type nitride is formed at lower portions of the V-shaped inverse pyramids.
  • an effective area of the regions 32-A is increased, and thus a contact area with the first n-type nitride layer 31 is increased. It is thus possible to control a conductivity.
  • the first n-type nitride layer 31 , the current showerhead layer 32 and the second n-type nitride layer 33 may be composed of one or more layers respectively within the generally-accepted range on the basis of the above method.
  • Embodiments 1 and 2 provide the methods of forming the spontaneous anisotropic conductive layer by means of the low temperature growth. As compared with a method of a general light emitting device, such methods do not need an additional process. Therefore, these methods can be easily applied to the realistic production.
  • a first n-type nitride layer 31 and a high temperature growth nonconductive layer 32-C are grown, and then patterns are formed by means of a semiconductor lithography process. Thereafter, holes are formed in the nonconductive layer 32-C by means of a dry etching method.
  • An n-type nitride thin film is regrown in a thin film growth equipment, thereby forming regions 32-A and a second n-type nitride layer 33.
  • this method needs an additional semiconductor process and a nitride regrowth process, to thereby relatively complicate the whole process.

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Abstract

La présente invention porte sur un dispositif émettant de la lumière semi-conducteur de nitrure III comprenant un substrat, une couche semi-conductrice du type n positionnée sur le substrat et ayant une conductivité du type n, la couche semi-conductrice du type n étant dotée d'une couche conductrice anisotrope formée par une première région ayant une première conductivité et une seconde région une seconde conductivité inférieure à la première conductivité, une couche semi-conductrice de nitrure du type p ayant une conductivité du type p, une couche active positionnée entre la couche semi-conductrice de nitrure du type n et la couche semi-conductrice de nitrure du type p pour générer de la lumière par recombinaison d'électrons et de trous, une première électrode en contact électrique avec la couche semi-conductrice de nitrure du type n, et une seconde électrode en contact électrique avec la couche semi-conductrice de nitrure du type p.
PCT/KR2007/007060 2006-12-30 2007-12-31 Dispositif émettant de la lumière semi-conducteur de nitrure iii WO2008082244A1 (fr)

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EP3276677A4 (fr) * 2015-03-23 2018-10-31 Stanley Electric Co., Ltd. Elément électroluminescent à semi-conducteur
WO2020148121A1 (fr) * 2019-01-14 2020-07-23 Osram Opto Semiconductors Gmbh Composant semi-conducteur optoélectronique et son procédé de fabrication

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US8569784B2 (en) 2008-11-24 2013-10-29 Lg Innotek Co., Ltd. Light emitting device and method for manufacturing the same
EP3276677A4 (fr) * 2015-03-23 2018-10-31 Stanley Electric Co., Ltd. Elément électroluminescent à semi-conducteur
WO2020148121A1 (fr) * 2019-01-14 2020-07-23 Osram Opto Semiconductors Gmbh Composant semi-conducteur optoélectronique et son procédé de fabrication
US11990576B2 (en) 2019-01-14 2024-05-21 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor device and method for manufacturing the same

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