WO2008078740A1 - 非同期式論理回路の論理回路設計装置、論理回路設計方法および論理回路設計プログラム - Google Patents

非同期式論理回路の論理回路設計装置、論理回路設計方法および論理回路設計プログラム Download PDF

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Publication number
WO2008078740A1
WO2008078740A1 PCT/JP2007/074833 JP2007074833W WO2008078740A1 WO 2008078740 A1 WO2008078740 A1 WO 2008078740A1 JP 2007074833 W JP2007074833 W JP 2007074833W WO 2008078740 A1 WO2008078740 A1 WO 2008078740A1
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WO
WIPO (PCT)
Prior art keywords
logic circuit
circuit designing
state storage
storage element
restriction
Prior art date
Application number
PCT/JP2007/074833
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English (en)
French (fr)
Inventor
Katsunori Tanaka
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2008551115A priority Critical patent/JP5120785B2/ja
Priority to US12/518,686 priority patent/US20090271747A1/en
Priority to EP07860062A priority patent/EP2098969A4/en
Publication of WO2008078740A1 publication Critical patent/WO2008078740A1/ja

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/35—Delay-insensitive circuit design, e.g. asynchronous or self-timed

Abstract

課題　ラッチやフリップ・フロップに代表される状態記憶素子の特性制約を満たす非同期式論理回路を設計する論理回路設計装置を提供する。 解決手段　状態記憶素子の制御信号パルスを生成する信号遷移系列を、状態記憶制御信号遷移系列抽出部１１２によって、論理回路設計装置に入力された状態遷移グラフから抽出し、パルス生成パス遅延制約設定追加部１１５によって、当該信号遷移系列に対応する信号線パスの最小遅延制約を当該状態記憶素子の最小パルス幅制約値として設定して論理合成を行う。
PCT/JP2007/074833 2006-12-26 2007-12-25 非同期式論理回路の論理回路設計装置、論理回路設計方法および論理回路設計プログラム WO2008078740A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008551115A JP5120785B2 (ja) 2006-12-26 2007-12-25 非同期式論理回路の論理回路設計装置、論理回路設計方法および論理回路設計プログラム
US12/518,686 US20090271747A1 (en) 2006-12-26 2007-12-25 Logic circuit designing device, logic circuit designing method and logic circuit designing program for asynchronous logic circuit
EP07860062A EP2098969A4 (en) 2006-12-26 2007-12-25 LOGIC CIRCUIT DESIGN DEVICE FOR ASYNCHRONOUS LOGIC CIRCUITS, LOGIC CIRCUIT DESIGN METHOD, AND LOGIC CIRCUIT DESIGN PROGRAM

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006349365 2006-12-26
JP2006-349365 2006-12-26

Publications (1)

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WO2008078740A1 true WO2008078740A1 (ja) 2008-07-03

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PCT/JP2007/074833 WO2008078740A1 (ja) 2006-12-26 2007-12-25 非同期式論理回路の論理回路設計装置、論理回路設計方法および論理回路設計プログラム

Country Status (5)

Country Link
US (1) US20090271747A1 (ja)
EP (1) EP2098969A4 (ja)
JP (1) JP5120785B2 (ja)
TW (1) TWI402708B (ja)
WO (1) WO2008078740A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8086975B2 (en) * 2008-04-10 2011-12-27 University Of Southern California Power aware asynchronous circuits
US8448105B2 (en) 2008-04-24 2013-05-21 University Of Southern California Clustering and fanout optimizations of asynchronous circuits

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US8024696B1 (en) * 2008-11-13 2011-09-20 Xilinx, Inc. Clock speed for a digital circuit
DE102010032314A1 (de) * 2010-07-27 2012-02-02 Volkswagen Ag Verfahren und Vorrichtung zum modellbasierten Entwurf einer elektronischen Schaltung
WO2013118119A1 (en) * 2012-02-09 2013-08-15 B.G. Negev Technologies & Applications Ltd. Design of dual mode logic circuits
US8901965B2 (en) 2011-08-03 2014-12-02 Ben-Gurion University Of The Negev Research And Development Authority Device and method for dual-mode logic
US8656326B1 (en) * 2013-02-13 2014-02-18 Atrenta, Inc. Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design

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JP2633648B2 (ja) 1988-09-16 1997-07-23 富士通株式会社 シミュレーション装置のパルス幅チェック方式
JP2004030186A (ja) * 2002-06-25 2004-01-29 Renesas Technology Corp 論理シミュレータ
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See also references of EP2098969A4
SHIMIZU M. ET AL.: "Kyokusho Dokigata Hidokishiki Kairo ni Okeru Locally-timed Shingo Seisei Kairo no Teishohi Denryoku Sekkei", IEICE TECHNICAL REPORT, THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, vol. 103, no. 480, 21 November 2003 (2003-11-21), pages 259 - 264 (VLD2003-113) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8086975B2 (en) * 2008-04-10 2011-12-27 University Of Southern California Power aware asynchronous circuits
US8448105B2 (en) 2008-04-24 2013-05-21 University Of Southern California Clustering and fanout optimizations of asynchronous circuits

Also Published As

Publication number Publication date
US20090271747A1 (en) 2009-10-29
EP2098969A1 (en) 2009-09-09
TW200846960A (en) 2008-12-01
JPWO2008078740A1 (ja) 2010-04-30
JP5120785B2 (ja) 2013-01-16
EP2098969A4 (en) 2013-01-02
TWI402708B (zh) 2013-07-21

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