WO2008074464A1 - Arrondissement d'arête de tranches - Google Patents

Arrondissement d'arête de tranches Download PDF

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Publication number
WO2008074464A1
WO2008074464A1 PCT/EP2007/011107 EP2007011107W WO2008074464A1 WO 2008074464 A1 WO2008074464 A1 WO 2008074464A1 EP 2007011107 W EP2007011107 W EP 2007011107W WO 2008074464 A1 WO2008074464 A1 WO 2008074464A1
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WO
WIPO (PCT)
Prior art keywords
edge profile
ingot
edge
wafer
impressed
Prior art date
Application number
PCT/EP2007/011107
Other languages
German (de)
English (en)
Inventor
Werner Bergholz
Original Assignee
Jacobs University Bremen Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jacobs University Bremen Gmbh filed Critical Jacobs University Bremen Gmbh
Publication of WO2008074464A1 publication Critical patent/WO2008074464A1/fr

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor

Definitions

  • the invention relates to a method for rounding the edges of wafers, wherein, prior to the production of the wafers, an ingot, from which the wafer is obtained, an edge profile is impressed. Furthermore, the wafer thus obtained and the ingot are loaded with embossed edge profile.
  • PV photovoltaic
  • non-treated edge areas of a wafer cause disturbances in the material which reduce the energy yield by up to 7%. This follows from the inventor's many years of experience, which reports on mainly mussel-like eruptions at the edges of said wafers. A treatment of these border areas by prior art methods is very costly and therefore not performed.
  • the object of the present invention is to provide a method for rounding wafers, in particular of silicon wafers for photovoltaics, in which the disadvantages are avoided.
  • the object is achieved according to the invention with a method for rounding wafers, in particular of silicon wafers for photovoltaic, characterized in that the ingot an edge profile is impressed.
  • the future partial edge profile of the wafer is already determined before the separation process for obtaining the wafer.
  • the currently practiced procedure of edge processing of the wafer after the separation from the ingot can be circumvented.
  • Wafers are understood to mean a wide variety of types of semiconductor and ceramic materials. Thus, such a wafer can consist of monocrystalline or polycrystalline silicon. Other ceramics that come as a carrier material in question are covered by the term wafer.
  • a wafer of the type described here is not limited to the use of photovoltaic m, but also the m of the semiconductor industry for other purposes, such as chip and component manufacturing used wafers erfmdungsgewait includes.
  • the ingot may have any desired shape, with the monocrystalline silicon preferred being the shape obtained by pulling from a single crystal and the square column shape being preferred for polycrystalline silicon.
  • the edge profile is the shape on the ingot, which is created by the impact process on the ingot. In a preferred embodiment of the method, the edge profile is impressed along at least one cutting edge of the ingot. Where the cut edge includes the location on the ingot where the separation process is to obtain the wafer.
  • various separation means can be used to separate the wafer, the separation means being guided substantially along the edge profile.
  • separation means it is preferable to use legends or also splitting agents as described in JP2003332273 or DE3029828 or also DE1207636. Combinations of splitting and Sagevorgangen are erfmdungsgewait includes.
  • the edge profiling and the subsequent separation process which has taken place before the separation, a substantially predetermined partial edge profile is formed on the edge of the wafer according to the invention.
  • the partial edge profile corresponds to the edge profile. This is the case when the separation process of the wafer is performed by a splitting operation. If the separation process is carried out by means of say, the sub-edge profile deviates essentially by the proportionate contribution of the legend from the edge profile.
  • the edge profile is rubbing or chipping stamped on the ingot, wherein combinations are erfmdungsgehold included. Machining processes are described, for example, in Chao et al. in Journal of Materials Processing Technology (pages 187-190).
  • the imprinting of the edge profile can be carried out by etching, wherein the preferred At fluids are HF + HNO 3 , KOH or HF + HNO 3 + acetic acid.
  • the preferred At fluids are HF + HNO 3 , KOH or HF + HNO 3 + acetic acid.
  • laser beam treatments in the UV and VIS range and ion beam treatments are included.
  • the embossing tool is designed as a grinding or cutting tool with a shape which corresponds to the edge profile as a negative.
  • the edge profile m is preferably imprinted on the ingot by means of an embossing tool in one process step or else in several successive process steps. The imprinting of several edge profiles on the ingot is also true of a process step.
  • the edge profile impressed on the ingot is polished by a polishing tool. This reduces possible particle showers and reduces disturbances in the peripheral areas of the later wafer. Em polishing according to the invention can also be done on the wafer.
  • the forms for the edge profile are included, which after the separation process of the wafer have a partial edge profile on the wafer, which is formed as a circle segment or parabolic segment. Furthermore, the edge profile forms are included, in which after the separation process of the wafer substantially smooth transitions to the disk surface are obtained. Smooth transitions are characterized by small curvatures according to the second mathematical derivation. But even transitions that do not allow a mathematical description of the derivative at the transition from disk edge to disk surface, as they arise in triangular or trapetzformigen Kantenprofllen are embraced according to the invention. PAGE INTENTIONALLY LEFT BLANK
  • Figure 1 representation of various ingots.
  • Figure 3 Example of a shape for edge profiles plus legend and separated wafer.
  • Figure 4 Example of a form for edge profiles plus legend and separated wafer.
  • Figure 5 Example of a form for edge profiles plus legend and separated wafer.
  • FIG. 6 shows an example of a shape for edge profiles plus the legend and separated wafers.
  • FIG. 7 shows an example of a shape for edge profiles relative to saw and separated wafer.
  • FIG. 2 shows a processed monocunted ingot 1. This will be in a further process step
  • the edge profile 4 imprinted an edge profile 4.
  • a wafer 7 is cut off along the edge profile 5.
  • This wafer contains at its edges a partial profile which no longer tends to break and has reduced storage areas.
  • the typical thicknesses of the wafers at 150 microns and the typical thicknesses of the legends used are between 80 and 150 microns, the typical widths and depths of the edge profiles are similarly wide and deep, with the edge profiles regularly wider than the release means used.
  • the depth (m arrow) includes values between 1 and 300 microns, wherein m a special embodiment, the depth values between 10 and 250 microns and has in a very particular embodiment, the depth values between 50 and 150 microns.
  • FIGS. 3 to 7. Corresponding edge and part edge profiles are shown in FIGS. 3 to 7.
  • the identifiers for all figures are uniformly chosen. The identifiers are introduced with reference to FIG.
  • the ingot 1 has a trapetzformiges edge profile 2.
  • This edge profile 2 has a region 3, which is the separating tool - here a legend A, having a sawtooth region 5, with sawtooth effect 6 vertical to Viewing level, where the legend acts in the direction of arrow 7 through the ingot 1 or works - leads.
  • the wafer 8 After the legend has separated a part of the ingot (wafer 8), the wafer 8 has a partial edge profile 9, which is designed as a trap trailing arm.
  • the wafer 8 has a cut surface 10.
  • the wafer 8 contains a defined Operathrefil. 9
  • FIG. 4 shows a further preferred embodiment for the edge profile.
  • the edge profile 2 is formed m triangular shape.
  • the legend 4 separates the wafer 8 from the ingot 1 in step 7, which indicates the effective direction of the legend 4.
  • the wafer 8 has a truncated triangle leg 9 as a partial edge profile.
  • FIG. 5 shows a further preferred embodiment for the edge profile.
  • the edge profile 2 is partially formed m circle shape 2 plus a cutting area 3.
  • the legend 4 separates the wafer 8 from the ingot 1 in step 7, which indicates the effective direction of the legend 4.
  • the wafer 8 has a partial circular profile as a partial edge profile.
  • FIG. 6 shows a further preferred embodiment for the edge profile.
  • the edge profile 2 is formed in trough shape.
  • the legend 4 separates the wafer 8 from the ingot 1 in step 7, which indicates the effective direction of the legend 4.
  • the wafer 8 has, as a partial edge profile, the trough shape around the part (9) reduced by the saw 4.
  • FIG. 7 is analogous to FIG. 6. The only difference is that the trough mold 2 is more pronounced. In this embodiment, too, there is no smooth transition of the partial edge profile 9 to the cutting surface 10, but this embodiment is likewise covered erfmdungsgelois.

Abstract

La présente invention concerne un outil, un lingot et une tranche et un procédé d'arrondissement de tranches, en particulier de pastilles de silicium pour le domaine photovoltaïque, un profilé d'arête étant marqué sur le lingot. Ce n'est qu'après le marquage du profilé d'arête qu'une tranche est séparée du lingot. La tranche séparée présente un profilé d'arête partiel défini.
PCT/EP2007/011107 2006-12-18 2007-12-18 Arrondissement d'arête de tranches WO2008074464A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE200610060195 DE102006060195A1 (de) 2006-12-18 2006-12-18 Kantenverrundung von Wafern
DE102006060195.5 2006-12-18

Publications (1)

Publication Number Publication Date
WO2008074464A1 true WO2008074464A1 (fr) 2008-06-26

Family

ID=39272124

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2007/011107 WO2008074464A1 (fr) 2006-12-18 2007-12-18 Arrondissement d'arête de tranches

Country Status (2)

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DE (1) DE102006060195A1 (fr)
WO (1) WO2008074464A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008037051A1 (de) 2008-08-09 2010-02-11 Jacobs University Bremen Ggmbh Verfahren zur Selbstjustage von Sägedrähten in vorgefertigten Rillen eines quaderförmigen Ingots
DE102013113030A1 (de) * 2013-03-28 2014-10-02 Freiberger Compound Materials Gmbh Verfahren zur Kantenverrundung von Halbleiter-Wafern

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3716943A1 (de) * 1987-05-20 1988-12-08 Hans J Scheel Verfahren und vorrichtung zum trennen von insbesondere stabfoermigem material
JPH02155231A (ja) * 1988-12-08 1990-06-14 Fujitsu Ltd ウェーハの製造方法
JPH07232319A (ja) * 1994-02-24 1995-09-05 M Setetsuku Kk インゴットのスライス方法
DE19514350A1 (de) * 1994-06-02 1995-12-07 Tokyo Seimitsu Co Ltd Vorrichtung und Verfahren zur Waferherstellung
EP0729815A1 (fr) * 1995-02-28 1996-09-04 Shin-Etsu Handotai Co., Ltd. Procédé pour la production de tranches
US5845630A (en) * 1996-04-25 1998-12-08 Komatsu Electronic Metals Co., Ltd. Process and apparatus for fabricating a semiconductor wafer
JPH11348031A (ja) * 1998-06-09 1999-12-21 Sumitomo Metal Ind Ltd 半導体基板の製造方法、外面加工装置及び単結晶インゴット

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS495265A (fr) * 1972-04-28 1974-01-17
US4344260A (en) * 1979-07-13 1982-08-17 Nagano Electronics Industrial Co., Ltd. Method for precision shaping of wafer materials
JP3649393B2 (ja) * 2000-09-28 2005-05-18 シャープ株式会社 シリコンウエハの加工方法、シリコンウエハおよびシリコンブロック

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3716943A1 (de) * 1987-05-20 1988-12-08 Hans J Scheel Verfahren und vorrichtung zum trennen von insbesondere stabfoermigem material
JPH02155231A (ja) * 1988-12-08 1990-06-14 Fujitsu Ltd ウェーハの製造方法
JPH07232319A (ja) * 1994-02-24 1995-09-05 M Setetsuku Kk インゴットのスライス方法
DE19514350A1 (de) * 1994-06-02 1995-12-07 Tokyo Seimitsu Co Ltd Vorrichtung und Verfahren zur Waferherstellung
EP0729815A1 (fr) * 1995-02-28 1996-09-04 Shin-Etsu Handotai Co., Ltd. Procédé pour la production de tranches
US5845630A (en) * 1996-04-25 1998-12-08 Komatsu Electronic Metals Co., Ltd. Process and apparatus for fabricating a semiconductor wafer
JPH11348031A (ja) * 1998-06-09 1999-12-21 Sumitomo Metal Ind Ltd 半導体基板の製造方法、外面加工装置及び単結晶インゴット

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