WO2008062571A1 - Appareil de test de circuit pour circuit intégré semi-conducteur - Google Patents

Appareil de test de circuit pour circuit intégré semi-conducteur Download PDF

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Publication number
WO2008062571A1
WO2008062571A1 PCT/JP2007/057569 JP2007057569W WO2008062571A1 WO 2008062571 A1 WO2008062571 A1 WO 2008062571A1 JP 2007057569 W JP2007057569 W JP 2007057569W WO 2008062571 A1 WO2008062571 A1 WO 2008062571A1
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WO
WIPO (PCT)
Prior art keywords
circuit
semiconductor integrated
unit
constraint
integrated circuit
Prior art date
Application number
PCT/JP2007/057569
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English (en)
Japanese (ja)
Inventor
Hirokuni Taketazu
Yoshihito Nishida
Hirofumi Taguchi
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Publication of WO2008062571A1 publication Critical patent/WO2008062571A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Definitions

  • the present invention relates to a circuit verification device for a semiconductor integrated circuit, and more particularly to a device for verifying a circuit structure violation that causes a circuit operation abnormality occurring between asynchronous clock domains.
  • Patent Document 1 Japanese Patent Laid-Open No. 2003-216672
  • the present invention solves the above-described problems, and an object of the present invention is to provide a circuit verification device that outputs a verification result with higher accuracy, and reduces extra result output and result analysis man-hours.
  • a circuit verification device receives circuit connection information of a semiconductor integrated circuit and clock information for operating the semiconductor integrated circuit as inputs, and circuit structure of the semiconductor integrated circuit
  • a circuit analysis unit that analyzes the circuit structure, a constraint proposal unit that proposes circuit operation constraints estimated by the circuit analysis unit, and a circuit structure that may cause abnormal circuit operation between different clock domains depending on the circuit analysis unit
  • the inter-clock domain violation discriminating unit for discriminating violations and the inter-clock domain violation discriminating unit.
  • a violation report output unit for reporting violations, and the circuit operation constraint proposed by the constraint proposal unit is added as input information to be given to the circuit analysis unit.
  • the constraint proposal unit uses the presented constraint as a circuit operation constraint and adds it as input information for circuit analysis, and a new semiconductor integrated circuit based on the added constraint.
  • a circuit analysis unit for analyzing the circuit structure.
  • the constraint proposal unit proposes signal operation specifications between single or multiple signals.
  • the constraint proposal unit classifies the types of signals to be propagated and proposes a classification system.
  • the constraint proposal unit analyzes an operation mode for selecting a plurality of clocks and proposes the operation mode.
  • the constraint proposal unit has a constraint comparison unit that compares the circuit operation constraint given as input information with the proposed circuit operation constraint and confirms the validity of the circuit operation constraint. .
  • the circuit operation constraint addition unit has an operation constraint selection unit that selects operation constraints uniquely determined from the circuit structure, and the circuit structure force selected by the operation constraint selection unit is automatically determined. To be added to the circuit.
  • the circuit verification apparatus receives circuit connection information of a semiconductor integrated circuit and clock information for operating the semiconductor integrated circuit as inputs, and analyzes a circuit structure for analyzing the circuit structure of the semiconductor integrated circuit And a clock domain violation discriminating unit for discriminating a circuit structure violation that may cause a circuit operation abnormality that may occur between different clock domains by the circuit analyzing unit, and a violation report discriminated by the clock domain violation discriminating unit And a violation report output section that outputs the report while sorting the report according to certain conditions.
  • the invention's effect [0014]
  • the operation constraints for performing verification closer to the actual operation are derived and added as circuit analysis information.
  • the report output takes into account the powerful circuit operation that has not been considered before, and the result can be obtained with higher accuracy than the conventional violation report.
  • the report output method needs to be analyzed by configuring the violation report so that it can be classified into violations that may be violations between clock domains and violations that are not violations. You can reduce reports. As a result, in the past, it was necessary to perform anomaly analysis in which parts that did not require analysis were output as reports.
  • FIG. 1 is a flowchart of a circuit verification device according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of a circuit verification device according to another embodiment of the present invention.
  • FIG. 3 is a flowchart of a circuit verification apparatus according to still another embodiment of the present invention.
  • FIG. 4 is a diagram showing an example of a circuit structure that may cause a problem in CDC verification.
  • FIG. 5 is a timing chart of an example that may cause a problem in CDC verification.
  • FIG. 6 is a circuit configuration diagram for explaining another example of information proposed by the constraint proposal unit of the circuit verification device according to the embodiment of the present invention.
  • FIG. 7 is a diagram showing an example of operation specifications in the circuit configuration of FIG.
  • FIG. 1 is a flowchart of a circuit verification device for a semiconductor integrated circuit.
  • 101 is circuit connection information of a semiconductor integrated circuit described in a hardware description language such as VerilogHDL or a programming language such as C
  • 102 is a clock cycle or clock for operating the semiconductor integrated circuit.
  • Circuit operation clock information such as name.
  • the circuit verification apparatus in FIG. 1 receives as input the semiconductor circuit connection information 101 and the circuit operation clock information 102, and analyzes the circuit structure of the semiconductor integrated circuit, and the circuit estimated by the circuit analysis unit 103. Between the clock domains (CDC: clock domain) that determines the structural violations in the circuit structure that cause abnormal circuit operation between different clock domains.
  • CDC clock domain
  • a violation discriminating unit 105 and a violation report output unit 106 for reporting the violation discriminated by the CDC violation discriminating unit 105, and circuit operation constraint information for limiting the circuit operation obtained by the constraint proposing unit 104 107,
  • the report obtained by the violation report output unit 106 becomes the CD C violation report 108.
  • the semiconductor circuit connection information 101 and the circuit operation clock information 102 are given to the circuit analysis unit 103, so that the estimated / proposed circuit operation constraint information 107 and the circuit structure violation report are output.
  • the CDC circuit structure violation report is a report of a violation that has a possibility of being a violation in many cases. However, this includes violations that may not be violated by restricting circuit operation. Therefore, it may be possible to divide the report output by setting certain conditions to identify violations that may not be violations.
  • FIG. 2 is a circuit operation constraint information 107 obtained from the constraint proposal unit 104 in the violation report output unit 106 that reports the violation determined by the CDC violation determination unit 105 in the configuration shown in FIG. Shows a configuration having a violation report selection unit 203 for selecting a violation report 201 that may be a CDC violation and a violation report 202 that is not a violation.
  • reports 201 and 202 can be output separately for violations that may be circuit structure violations and violations that are not violations due to circuit operation restrictions.
  • the portions that do not violate due to the circuit operation restrictions that have been made are not output as the report 201, and the content of the report 201 can be reduced.
  • the analysis man-hour can be reduced accordingly.
  • Metastable is that the receiving side FF output is unstable when the sending side signal changes during the set-up time or hold time of the receiving flip-flop (FF) between different clock domains. To become.
  • the sending side data is received by the receiving side clock with a two-stage FF, or a signal for controlling the data is separately provided on the receiving side. Try not to cause a condition.
  • a signal for controlling the data is separately provided on the receiving side.
  • the signal controls the timing at which the receiver's signal is sent. In such a situation, it can be considered a violation.
  • designating a control signal is a circuit operation restriction.
  • FIG. 3 shows a circuit operation constraint addition unit 301 for recognizing the circuit operation constraint information 107 output by the constraint proposal unit 104 that proposes an estimated constraint in the configuration shown in FIG. Therefore, the analysis unit 302 newly analyzes the circuit based on the added circuit operation restriction.
  • FIG. 4 shows an example of a circuit structure that can cause a problem in CDC.
  • 401 to 404 are Fs constituting path 1
  • 405 to 408 are FFs constituting path 2.
  • 409 is a logic circuit composing path 1
  • 410 is a logic circuit composing path 2.
  • Reference numeral 411 denotes combinational logic in which path 1 and path 2 merge
  • reference numeral 412 denotes FF that latches an output signal from 411.
  • 401 and 405 operate in the same clock domain (for example, clkB), but otherwise operate in the same clock domain (for example, clkA), but different from 401 and 405.
  • a signal different from the expected signal may be received after 411 depending on the timing of reaching the signal strengths 402 and 406 transmitted in 401 and 405.
  • This example is shown as a timing chart in FIG. In 401 and 405, the signal is transmitted by clkB with a force of “1”.
  • a skew error occurs in the path from 401 to 402 and the path from 405 to 406, and the rising timing of clkA occurs between these errors If there is, 402 outputs “1” and 406 outputs “0”, which is different from the value that should be propagated. Therefore, this is an error structure in CDC verification.
  • the constraint proposing unit 104 indicates the condition.
  • a signal operation specification between multiple signals such as ⁇ the signal change between D001 and D005 does not always occur at the same time, and it opens and changes for a period longer than one cycle of clkA '', the skew Even if this occurs, the intended signal is propagated, and the circuit structure shown in Fig. 4 is not a problem.
  • the constraint proposal unit 104 outputs information that prompts the user to check what kind of operation specifications may exist at which point in the circuit. For example, in the example of FIG.
  • FF412 is a circuit structure error: is there no operation restriction between 401 and 405” t.
  • the operation specification created based on the output information is given to the input information as the operation constraint of the circuit, and the CDC violation report 303 can eliminate the output related to this part. Therefore, it can be expected that the content of the CDC violation report 303 is reduced and the result analysis man-hours are reduced.
  • FIG. 6 shows another example of information proposed by the constraint proposing unit 104.
  • reference numerals 601 to 603 indicate circuit information having different functions, and data transmission / reception occurs in each circuit.
  • Reference numeral 604 denotes a selector for selecting a plurality of clocks (here, CLK1, CLK2, CLK3).
  • the selector 604 receives a mode signal indicating which clock is selected.
  • 601 to 603 have different input clocks depending on the state of the mode signal of the selector 604.
  • Model in the case of mode signal power, semiconductor circuit information A, B is CLK1, semiconductor circuit information C It is assumed that there is a specification related to operating at CLK3.
  • the above-described constraint proposal unit 104 outputs the circuit operation constraint, but this information is compared with the circuit operation constraint given to the circuit analysis unit 103 by the user, and the given circuit operation constraint is determined. It is possible to confirm the validity. For example, when the constraint that “signal A and signal B are open for a certain period of time” is given as an input, the constraint suggestion unit 104 shows the relationship between signal A and signal B. If there is something that shows the relationship between signal A and signal C, the input information may be incorrect. The effect of improving the accuracy of the report can be expected by detecting such information by comparing the circuit operation constraints and avoiding erroneous report reduction.
  • the semiconductor integrated circuit circuit verification apparatus can obtain a report output that takes into account the powerful circuit operation that has not been considered in the past, and in particular, an abnormal circuit operation occurring between asynchronous clock domains. It is useful as a device for verifying the cause of circuit structure violations.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Dans un appareil pour tester le CDC (croisement de domaines d'horloge) dans une conception de circuit intégré semi-conducteur, afin de réduire ou cribler les contenus de rapports de violation de CDC, des informations qui amènent à vérifier une restriction de fonctionnement de circuit sont produites et la structure de circuit est analysée sur la base de la restriction de fonctionnement de circuit.
PCT/JP2007/057569 2006-11-21 2007-04-04 Appareil de test de circuit pour circuit intégré semi-conducteur WO2008062571A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006-314173 2006-11-21
JP2006314173 2006-11-21

Publications (1)

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WO2008062571A1 true WO2008062571A1 (fr) 2008-05-29

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010049385A (ja) * 2008-08-20 2010-03-04 Renesas Technology Corp クロックドメインチェック方法及びクロックドメインチェック用プログラム並びに記録媒体
JP2012168718A (ja) * 2011-02-14 2012-09-06 Nec Corp 半導体設計支援装置、タイミング制約生成方法、およびプログラム

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0660143A (ja) * 1992-05-21 1994-03-04 Nec Corp 論理回路の遅延解析システム
JPH06176103A (ja) * 1992-12-02 1994-06-24 Matsushita Electric Ind Co Ltd 設計検証方法
JP2002117093A (ja) * 2000-10-12 2002-04-19 Ricoh Co Ltd タイミング解析装置および方法
JP2006252438A (ja) * 2005-03-14 2006-09-21 Fujitsu Ltd 検証支援装置、検証支援方法、検証支援プログラム、および記録媒体
JP2006260492A (ja) * 2005-03-18 2006-09-28 Fujitsu Ltd 検証支援装置、検証支援方法、検証支援プログラム、および記録媒体

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0660143A (ja) * 1992-05-21 1994-03-04 Nec Corp 論理回路の遅延解析システム
JPH06176103A (ja) * 1992-12-02 1994-06-24 Matsushita Electric Ind Co Ltd 設計検証方法
JP2002117093A (ja) * 2000-10-12 2002-04-19 Ricoh Co Ltd タイミング解析装置および方法
JP2006252438A (ja) * 2005-03-14 2006-09-21 Fujitsu Ltd 検証支援装置、検証支援方法、検証支援プログラム、および記録媒体
JP2006260492A (ja) * 2005-03-18 2006-09-28 Fujitsu Ltd 検証支援装置、検証支援方法、検証支援プログラム、および記録媒体

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010049385A (ja) * 2008-08-20 2010-03-04 Renesas Technology Corp クロックドメインチェック方法及びクロックドメインチェック用プログラム並びに記録媒体
JP2012168718A (ja) * 2011-02-14 2012-09-06 Nec Corp 半導体設計支援装置、タイミング制約生成方法、およびプログラム

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