Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
  • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
  • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
  • B23K1/00—Soldering, e.g. brazing, or unsoldering
  • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
  • B23K1/0016—Soldering of electronic components
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
  • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
  • B23K1/00—Soldering, e.g. brazing, or unsoldering
  • B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
  • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
  • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
  • B23K20/002—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
  • B23K20/004—Wire welding
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/019—Manufacture or treatment of bond pads
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
  • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
  • B23K2101/00—Articles made by soldering, welding or cutting
  • B23K2101/36—Electric or electronic devices
  • B23K2101/40—Semiconductor devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/015—Manufacture or treatment of bond wires
  • H10W72/01571—Cleaning, e.g. oxide removal or de-smearing
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/075—Connecting or disconnecting of bond wires
  • H10W72/07511—Treating the bonding area before connecting, e.g. by applying flux or cleaning
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/251—Materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/251—Materials
  • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/29—Bond pads specially adapted therefor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/531—Shapes of wire connectors
  • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/551—Materials of bond wires
  • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/551—Materials of bond wires
  • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
  • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/551—Materials of bond wires
  • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
  • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/59—Bond pads specially adapted therefor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/951—Materials of bond pads
  • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/981—Auxiliary members, e.g. spacers
  • H10W72/983—Reinforcing structures, e.g. collars
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Definitions

• the invention relates generally to semiconductor device packaging, and more particularly, to methods of forming wire and solder bonds.
• wire and solder bonds are advantageous for use in multi-part wafers (MPWs), which are currently increasing in popularity.
• MPWs multi-part wafers
• Some of these MPWs include chips that require both wire bonds and solder bonds designed into a common reticle, i.e., they are fabricated together.
• a solder bond a solder joint flip chip connection to a substrate is made where the surface tension forces of the molten solder controls the height of the joint and supports the weight of the chip.
• the solder bond is oftentimes referred to as a controlled collapse chip connection (C 4).
• C 4 controlled collapse chip connection
• a wire bond a wire is joined to an opening in the chip. Where both types of bonds are used, the fabrication process must be capable of opening both wire bond and solder bond final via structures in parallel.
• FEOL front-end-of-line
• BEOL back-end-of-line
• a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond, both regions covered by a silicon nitride layer over a silicon oxide layer; forming in a material a first opening to the silicon oxide layer over the wire bond metal region and a second opening exposing the solder bond metal region; forming the solder bond to the solder bond metal region while the wire bond metal region is covered; exposing the wire bond metal region including removing the silicon oxide layer to the wire bond metal region; and forming the wire bond to the wire bond metal region.
• Wire bonds and solder bonds can be made accessible on a single multi-part wafer (MPW) or on a single chip, if necessary, and can be formed substantially simultaneously.
• MPW multi-part wafer
• a first aspect of the invention provides a method of forming a wire bond and a solder bond, the method comprising: providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond, both regions covered by a silicon nitride layer over a silicon oxide layer; forming in a material a first opening to the silicon oxide layer over the wire bond metal region and a second opening exposing the solder bond metal region; forming the solder bond to the solder bond metal region while the wire bond metal region is covered; exposing the wire bond metal region including removing the silicon oxide layer to the wire bond metal region; and forming the wire bond to the wire bond metal region.
• a second aspect of the invention provides a method of forming a wire bond and a solder bond, the method comprising: providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond, both regions covered by a silicon nitride layer over a silicon oxide layer; forming in a material a first opening to the silicon oxide layer over the wire bond metal region and a second opening exposing the solder bond metal region by: forming a first photoresist over the silicon nitride layer over the solder bond metal region and the wire bond metal region, forming an intermediate opening over only the solder bond metal region through the first photoresist, removing the silicon nitride layer over only the solder bond metal region using the intermediate opening, removing the first photoresist, depositing an uncured photosensitive polyimide (PSPI) layer as the material, forming the first opening through the PSPI layer over the wire bond metal region and the second opening through the PSPI layer over the solder bond metal region, and curing
• a third aspect of the invention provides a method of forming a wire bond and a solder bond, the method comprising: providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond, both regions covered by a silicon nitride layer over a silicon oxide layer; forming in a material a first opening to the silicon oxide layer over the wire bond metal region and a second opening exposing the solder bond metal region by: forming an uncured polyimide layer as the material over the silicon nitride layer over the solder bond metal region and the wire bond metal region, forming the first opening through the uncured polyimide layer to the silicon oxide layer over only the wire bond metal region using a first photoresist that covers the solder bond metal region, removing the first photoresist, forming the second opening through the uncured polyimide layer to only the solder bond metal region using a second photoresist that covers the wire bond metal region, removing the second photoresist, and curing the polyimide layer
• FIG. 1 shows a preliminary structure according to one embodiment of the invention.
• FIG. 2 shows a result of one portion of a method according to one embodiment of the invention.
• FIGS. 3A-B show one embodiment of forming the structure of FIG. 2.
• FIGS. 4A-C show another embodiment of forming the structure of FIG. 2.
• FIGS. 5-7 show one embodiment of a method of completing forming of a solder bond and a wire bond according to the invention.
• FIG. 1 shows a preliminary structure 100 that is provided and includes a wire bond metal region 102 for a wire bond 190 (FIG. 7) and a solder bond metal region 104 for a solder bond 180 (FIGS. 6-7).
• regions 102, 104 may be included in a single chip or be provided in a multi-part wafer. Hence, the separation indicated in the figures is meant to illustrate potential distance between regions 102, 104, not necessarily total separation.
• both regions 102, 104 are covered by a silicon nitride (Si N ) layer 106 over a silicon oxide (SiO ) layer 108.
• Si N silicon nitride
• SiO silicon oxide
• Silicon nitride layer 106 may have a thickness of, for example, approximately 0.4 ⁇ m, and silicon oxide layer 108 may have a thickness of, for example, approximately 0.45 ⁇ m. However, the invention is not limited to those dimensions.
• Other structure provided may include substrate 110 (e.g., a dielectric) including a wire 112 (e.g., copper or aluminum) and barrier layers 114, 116, 118 (e.g., silicon nitride, silicon oxide and silicon nitride, respectively).
• wire 112 e.g., copper or aluminum
• barrier layers 114, 116, 118 e.g., silicon nitride, silicon oxide and silicon nitride, respectively.
• Each of metal region 102, 104 may include, for example, aluminum or copper.
• FIG. 2 shows forming, in a material 130, a first opening 132 to silicon oxide layer 108 over wire bond metal region 102 and a second opening 134 exposing solder bond metal region
• material 130 may take the form of a photoresist or a polyimide. This step may occur in a number of ways, as shown in FIGS. 3A-3B and FIGS. 4A-4C. Referring to FIGS. 3A-3B, in one embodiment, this process may begin, as shown in FIG. 3 A, by forming a first photoresist 140 over silicon nitride layer 106 over solder bond metal region 104 and wire bond metal region 102. Photoresists described herein may include any now known or later developed photoresist material (typically a positive resist, for example, JSR M20 or Shipley UV2HS), except where expressly denoted.
• a positive resist for example, JSR M20 or Shipley UV2HS
• An intermediate opening 142 may be formed through first photoresist 140 over only solder bond metal region 104 in any now known or later developed manner, e.g., patterning and etching.
• An etching 144 e.g., a reactive ion etch (RIE), is performed to remove silicon nitride layer
• First photoresist 140 is then removed using any now known or later developed stripping process.
• FIG. 3B shows depositing an uncured photosensitive polyimide (PSPI) layer 150.
• PSPI photosensitive polyimide
• Depositing may include any now known or later developed deposition technique appropriate for the materials being deposited.
• deposition may include but is not limited to spin application of organic materials like photoresist and polyimide, in addition to inorganic films deposited by chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD
• CVD chemical vapor deposition
• LPCVD low-pressure CVD
• PECVD plasma-enhanced CVD
• PSPI layer 150 ultimately acts as material 130 (FIG. 2) in this embodiment.
• PSPI layer 150 may include, for example, HD4000 series photosensitive polyimide materials from HD Microsystems, etc.
• First opening 132 and second opening 134 are then begun, e.g., by imaging PSPI layer 150 with a photoresist 136 (shown in phantom) that opens both openings 132, 134.
• First opening 132 is initially formed through uncured PSPI layer 150 over wire bond metal region 102 and second opening 134 is initially formed through uncured PSPI layer 150 over solder bond metal region 104.
• PSPI layer 150 is cured 152, e.g., by a thermal process.
• a non-selective etching 154 (e.g., RIE) is performed next to expose solder bond metal region 104 and remove silicon nitride layer 106 to silicon oxide layer 108 over wire bond metal region 102, resulting in the structure shown in FIG. 2. That is, etching 154 removes silicon oxide layer 108 over solder bond metal region 104 and simultaneously removes only silicon nitride layer 106 over wire bond metal region 102, thus maintaining a protective layer over wire bond metal region 102.
• etching 154 removes silicon oxide layer 108 over solder bond metal region 104 and simultaneously removes only silicon nitride layer 106 over wire bond metal region 102, thus maintaining a protective layer over wire bond metal region 102.
• FIGS. 4A-C an alternative embodiment is shown for forming, in material 130 (FIG. 2), first opening 132 (FIG. 2) to silicon oxide layer 108 over wire bond metal region 102 and second opening 134 (FIG. 2) exposing solder bond metal region 104.
• This embodiment also is initiated with structure 100 of FIG. 1.
• FIG. 4A shows forming an uncured polyimide layer 160 over silicon nitride layer 106 over both solder bond metal region 104 and wire bond metal region 102.
• Uncured polyimide layer 160 may include, for example, PI5878 formulation from HD Microsystems.
• polyimide layer 160 acts as material 130 (FIG. 2), as will be described below, and is non-photosensitive.
• first opening 132 is formed through uncured polyimide layer 160 to only wire bond metal region 102 (i.e., solder bond metal region 104 remains covered) using a photoresist 162.
• First opening 132 is extended to silicon oxide layer 108 over only wire bond metal region 102 using photoresist 162 and etching 164 (e.g. RIE). That is, etching 164 removes silicon nitride layer 106 over wire bond metal region 102, but leaves silicon oxide layer 108.
• photoresist 162 is removed using any now known or later developed stripping process.
• second opening 134 is formed through uncured polyimide layer 160 to solder bond metal region 104 only using another photoresist 166 that covers wire bond metal region 102. That is, photoresist 166 is deposited in any manner over solder bond metal region 104 and wire bond metal region 102, and is patterned and etched over solder bond metal region 104. Etching 168 (e.g., RIE) is then used to form second opening 134 to expose solder bond metal region 104, i.e., remove both silicon nitride layer 106 and silicon oxide layer 108 over solder bond metal region 104. Wire bond metal region 102 remains protected by photoresist 166. As shown in FIG. 4C, photoresist 166 (FIG. 4B) is removed using any now known or later developed stripping process, and polyimide layer 160 is cured 170, e.g., by a thermal process, resulting in the structure of FIG. 2.
• FIG. 5 shows forming a solder bond 180 to solder bond metal region 104 while wire bond metal region 102 is covered.
• This process may include depositing a ball limiting metallurgy (BLM) layer 182, e.g., by PVD.
• BLM layer 182 includes any solder wettable terminal metallurgy (e.g., tin (Sn) alloy), which defines the size and area of solder bond 180 when completed.
• BLM layer 182 limits the flow of the solder ball to the desired area, and provides adhesion and contact to the chip wiring.
• photoresist 184 also shows depositing a photoresist 184 and forming an opening 186 in photoresist 184 over only solder bond metal region 104 (i.e., no opening over wire bond metal region 102) to BLM layer 182.
• photoresist 184 may include a photosensitive dry polymer resist such as RISTON® available from DuPont. However, other photoresist material may also be employed.
• Solder for solder bond 180 is formed (deposited) in photoresist opening 186.
• Solder bond 180 may include any now known or later developed solder materials, e.g., including typically any alloy of lead-tin (PbSn) or tin (Sn)(Pb-free). As noted above, wire bond metal region 102 remains covered during this process by photoresist 184.
• FIG. 6 shows exposing wire bond metal region 102 including removing silicon oxide layer 108 to wire bond metal region 102.
• This process includes removing photoresist 184 (FIG. 5) and BLM layer 182 (FIG. 5) except BLM layer 182S under solder bond 180 to expose silicon oxide layer 108 (FIG. 8) over wire bond metal region 102, e.g., by etching 192.
• This process may include performing an etch 194 (FIG. 6), e.g., RIE, to remove silicon oxide layer 108 over wire bond metal region 102 using material 130 as a mask.
• FIGS. 6-7 show forming wire bond 190 (FIG. 7) to wire bond metal region 102.
• This process may optionally include performing a wet clean 196 (FIG. 7) using, for example, hydrofluoric acid of wire bond metal region 102 subsequent to silicon oxide layer 108 removal.
• this process may include cleaning and reflowing solder bond 180.
• Wire bond 190 may then be formed to wire bond metal region 102 using any now known or later developed techniques.

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• Engineering & Computer Science (AREA)
• Mechanical Engineering (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Wire Bonding (AREA)

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Publications (1)

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• 2006
  • 2006-11-20 US US11/561,437 patent/US7601628B2/en not_active Expired - Fee Related
• 2007
  • 2007-10-31 JP JP2009536693A patent/JP4659120B2/ja not_active Expired - Fee Related
  • 2007-10-31 AT AT07822110T patent/ATE490552T1/de not_active IP Right Cessation
  • 2007-10-31 KR KR1020097009876A patent/KR20090074801A/ko not_active Abandoned
  • 2007-10-31 WO PCT/EP2007/061763 patent/WO2008061864A1/en not_active Ceased
  • 2007-10-31 DE DE602007010978T patent/DE602007010978D1/de active Active
  • 2007-10-31 EP EP07822110A patent/EP2095418B1/en not_active Not-in-force

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