WO2008050476A1 - Procédé de fabrication d'une plaquette de silicium épitaxiale et plaquette de silicium épitaxiale - Google Patents

Procédé de fabrication d'une plaquette de silicium épitaxiale et plaquette de silicium épitaxiale Download PDF

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Publication number
WO2008050476A1
WO2008050476A1 PCT/JP2007/001143 JP2007001143W WO2008050476A1 WO 2008050476 A1 WO2008050476 A1 WO 2008050476A1 JP 2007001143 W JP2007001143 W JP 2007001143W WO 2008050476 A1 WO2008050476 A1 WO 2008050476A1
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WO
WIPO (PCT)
Prior art keywords
silicon wafer
susceptor
main surface
flow rate
epitaxial silicon
Prior art date
Application number
PCT/JP2007/001143
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English (en)
Japanese (ja)
Inventor
Masato Ohnishi
Takeshi Arai
Original Assignee
Shin-Etsu Handotai Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co., Ltd. filed Critical Shin-Etsu Handotai Co., Ltd.
Publication of WO2008050476A1 publication Critical patent/WO2008050476A1/fr

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/12—Substrate holders or susceptors
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/16—Controlling or regulating
    • C30B25/165—Controlling or regulating the flow of the reactive gases
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon

Definitions

  • the present invention relates to a method for manufacturing an epitaxial silicon wafer, in which an epitaxial silicon layer is grown on the silicon wafer.
  • an epitaxial silicon wafer in which an epitaxial silicon layer is formed on the silicon wafer may be used.
  • a general method for manufacturing an epitaxial silicon wafer is as follows. First, a mirror-polished silicon wafer (silicon single crystal wafer) is prepared and cleaned by RCA cleaning or the like. A natural oxide film is formed on the entire surface of the silicon wafer by the SC_1 cleaning and SC-2 cleaning during the RCA cleaning process. Next, a silicon wafer is placed on the susceptor in the chamber. Next, by supplying a reducing gas such as hydrogen gas into the chamber, an oxide film (including a natural oxide film) covering the surface on which epitaxial growth is performed (hereinafter sometimes referred to as the first main surface) Is removed.
  • a reducing gas such as hydrogen gas
  • a source gas containing silicon (monosilane, trichlorosilane, silicon tetrachloride, etc.) and hydrogen gas as a carrier gas are introduced into the chamber, and the first silicon single crystal wafer heated to high temperature is introduced.
  • a silicon single crystal layer (epitaxial silicon layer) is grown on the main surface (hereinafter, sometimes simply referred to as “epitaxial growth”).
  • a susceptor having a large number of through holes in a portion on which a wafer is placed is used as a susceptor.
  • a method is disclosed in which epitaxial growth is performed after the natural oxide film on the second main surface is completely removed by sufficiently supplying a reducing gas to the second main surface side of the wafer. This method prevents deterioration of the in-plane resistivity distribution of the epitaxial silicon layer due to auto-doping, reduces halo generated on the second main surface, and enables stable particle measurement on the second main surface. I can do it now.
  • the present invention has been made in view of such a problem, and when a susceptor having a large number of through-holes is used in manufacturing an epitaxial silicon wafer, the nano-particle generated on the second main surface is produced. Reduces the occurrence of topology irregularities It is an object of the present invention to provide a method for manufacturing an epitaxial silicon wafer that can be manufactured.
  • a susceptor in which a number of through holes are formed in a counterbore portion of the susceptor is used, and the susceptor is placed on the susceptor.
  • the second main surface side of the silicon wafer is subjected to hydrogen treatment so that the entire surface of the silicon wafer is in contact with the hydrogen gas during the hydrogen treatment, and the flow rate of hydrogen gas flowing in the epitaxial growth step
  • the ratio of the flow rate of the hydrogen gas and the flow rate of the source gas in the epitaxial growth process is set to the hydrogen flow rate.
  • (Slm) / Raw material gas flow rate (sI m) ⁇ 4 the epitaxial silicon layer manufacturing method that grows the epitaxial silicon layer has a good in-plane resistance distribution of the epitaxial silicon layer.
  • the present invention also relates to an epitaxial silicon wafer manufactured by the above method, wherein the nanotopology on the second main surface is 12 nm or less. Provide silicon wafers.
  • a good in-plane resistivity distribution of the epitaxial silicon layer can be obtained, and stable particle measurement can be performed on the second main surface. Even if a susceptor having a large number of through-holes is used as a susceptor for the purpose of obtaining an epitaxial silicon wafer that can be performed, the unevenness of the nanotopology on the second main surface is reduced. Epitaxial silicon wafers can be manufactured with reduced. As a result, the in-plane resistance distribution of the epitaxial silicon layer is good, stable particle measurement can be performed on the second main surface, and high-quality unevenness of the nanotopology on the second main surface is reduced. Epitaxial silicon can be manufactured.
  • FIG. 2 is a schematic sectional view of an epitaxy growth apparatus used in the present invention.
  • FIG. 4 is a schematic sectional view showing another example of a susceptor used in the present invention.
  • FIG. 5 is a flowchart showing a process flow of a manufacturing method of an epitaxial silicon wafer to which the present invention is applied.
  • the present inventors have repeatedly studied a method for suppressing the occurrence of such unevenness of nanotopology when a susceptor having a large number of through-holes is used as a susceptor. It has been found that by increasing the flow rate of the hydrogen gas that serves as the carrier gas in the growth process, the source gas can be diluted to reduce the flow of the source gas toward the second main surface.
  • the inventors of the present invention when performing epitaxial growth after performing hydrogen treatment using a susceptor having a large number of through holes, if the ratio of the hydrogen gas flow rate to the raw material gas flow rate exceeds a predetermined value, The present invention has been completed by conceiving that an epitaxial silicon wafer can be manufactured while suppressing the formation of irregularities of nanotopology locally on the second main surface. [001 7]
  • the present invention will be described more specifically with reference to the drawings, but the present invention is not limited thereto.
  • FIG. 1 An outline of the procedure of the manufacturing method of the epitaxial silicon wafer to which the present invention is applied is shown in FIG.
  • a silicon wafer for growing an epitaxial silicon layer is prepared.
  • a silicon mirror wafer having a predetermined diameter, conductivity type, resistivity, and plane orientation may be prepared.
  • step (b) the silicon wafer is appropriately subjected to cleaning such as R CA cleaning.
  • the cleaning method in this cleaning step may be one in which the concentration and type of the chemical solution are changed within a normal range in addition to typical R CA cleaning.
  • cleaning with ozone water may be used.
  • the cleaning in the step (b) often keeps the surface of the silicon wafer hydrophilic in order to prevent adhesion of particles, but is not limited to this.
  • RCA cleaning or cleaning with ozone water can keep the surface of the silicon wafer hydrophilic, and a natural oxide film is formed on the surface of the silicon wafer. After washing with such a chemical solution, washing with pure water or drying may be performed.
  • step (c) the silicon wafer is transferred to the epitaxial growth apparatus for processing.
  • a schematic diagram of an example of an epitaxial growth apparatus used in step (c) and subsequent steps is shown in FIG.
  • the epitaxy growth apparatus 51 includes a chamber 52, a susceptor 71 disposed inside the chamber 1, a susceptor support means 5 3 that supports the susceptor from below, and can freely rotate up and down, and the chamber 52.
  • Wafer transfer port for loading and unloading wafers to the outside, 5 4
  • Gas supply pipes for supplying various gases into the chamber 5 5
  • Gas supply pipes 5 5 A hydrogen gas supply means (not shown) for supplying hydrogen gas into the chamber, a raw material gas supply means (not shown) for supplying a raw material gas such as silane, and a gas exhaust pipe for discharging various gases from the chamber 1 5 7
  • the heating means 5 8 provided outside the chamber 52, the silicon wafer is transferred into the chamber 1, and the silicon wafer is transferred from the chamber 52. It is composed of wafer transfer means (not shown) for transferring c.
  • FIG. 3 shows an enlarged schematic view of the susceptor 71 used in the present invention.
  • FIG. 3 (b) is a cross-sectional view.
  • the susceptor 71 may have a left pin through hole 73 formed therein.
  • the lift pin 75 is passed through the lift pin through hole 73.
  • a counterbore 7 2 for positioning a silicon wafer to be placed is formed in the susceptor 71, and a large number of through holes 74 are formed on substantially the entire surface of the counterbore 72.
  • the through-hole 74 may have any size and shape that allows gas to flow smoothly.
  • the through-hole 74 may be cylindrical and have a diameter of 1 mm.
  • the number of through holes is not particularly limited. For example, if the opening density is 0.1 openings / cm 2 or more, the gas is on the second main surface side of the wafer. It is preferable because it can be supplied more uniformly.
  • the through holes of the susceptor 71 are preferably formed so as to be evenly arranged so that the opening density thereof is substantially uniform at the spot facing portion 72.
  • the susceptor 71 has a space between the silicon wafer W to be placed as shown in FIG.
  • a large number of through holes 74 are formed in the countersink of a susceptor having a known shape. If so, the present invention can be applied.
  • an epitaxial silicon layer is grown on the first main surface of the silicon wafer as follows.
  • the silicon wafer is transferred into the chamber 52 using a wafer transfer means (not shown) and the second main surface is opposed to the susceptor. 7 Place on the counterbore part 7 of 1.
  • a commonly used placement method can be applied in addition to the method using the lift pins 75.
  • a large amount of hydrogen gas is supplied to the first main surface side of the silicon wafer, and the oxide film on the first main surface is removed by heating.
  • the hydrogen gas is sufficiently supplied also to the second main surface side of the silicon wafer by the large number of through holes 74 formed in the susceptor 71, and the natural oxide film is almost uniformly removed.
  • a region that is locally unevenly removed remains.
  • the hydrogen gas can be more reliably brought into contact with the second main surface.
  • the natural oxide film on the second main surface side can be removed more uniformly.
  • the heating temperature and heating time during the hydrogen treatment may be set in any way as long as the natural oxide film on the silicon wafer surface, particularly the natural oxide film on the second main surface, can be efficiently removed. 80 ° C or higher, 1 minute or longer
  • an epitaxial silicon layer is grown on the first main surface of the silicon wafer.
  • This epitaxial growth is performed by introducing a source gas such as monosilane, trichlorosilane, or silicon tetrachloride and a hydrogen gas as a carrier gas into the chamber 52 and heating.
  • the flow rate of the carrier hydrogen gas is set to a predetermined value or more. Since the desired carrier hydrogen gas flow rate depends on the concentration of the raw material gas, it is specified by the ratio of the hydrogen gas flow rate and the raw material gas flow rate.
  • Carrier hydrogen By increasing the gas flow rate, the source gas is sufficiently diluted, and the amount of the source gas supplied around the second main surface side of the silicon wafer is reduced. For this reason, local nanotopology irregularities on the second main surface are suppressed.
  • an epitaxial silicon wafer in which an epitaxial silicon layer is formed on the first main surface of the silicon wafer can be manufactured.
  • This epitaxial silicon wafer has a good in-plane resistivity distribution of the epitaxial silicon layer, can perform stable particle measurement on the second main surface, and The unevenness of the nanotopology on the second main surface is reduced.
  • an epitaxial silicon wafer is actually manufactured as follows. The experiment was conducted.
  • An epitaxial silicon wafer was manufactured according to the procedure shown in FIG.
  • a p-type silicon single crystal wafer having a diameter of 30 Om m and a plane orientation (1 0 0) was prepared (a) and cleaned with ozone water (b).
  • the silicon wafer was loaded into an epitaxial growth apparatus having a susceptor having a large number of through holes as shown in FIG. 3 (c).
  • the volume of the chamber is about 3.5 I.
  • the temperature at the time of carry-in was 700 ° C.
  • hydrogen gas was introduced into the chamber at a flow rate of 60 s I m, the temperature was raised to 1 130 ° C for 45 seconds, and then hydrogen treatment was performed at 1 130 ° C for 1 minute ( d).
  • trichlorosilane was introduced into the chamber as a source gas containing silicon while flowing carrier hydrogen gas at a predetermined flow rate, and epitaxial growth was performed for 120 seconds while maintaining 1130 ° C. (E).
  • the flow rate of trichlorosilane was constant at 16 s I m and the flow rate of the carrier hydrogen gas was changed to manufacture an epitaxial silicon wafer.
  • the carrier hydrogen gas flow rate and the corresponding carrier hydrogen flow rate to the trichlorosilane flow rate are listed in Table 1. .
  • epitaxial silicon wafers were manufactured as described above.
  • TCS is an abbreviation for trichlorosilane.
  • the nanotopology measurement method in this specification is as follows. First, the irregularities with a wavelength of 2 Omm or less are extracted using the principle of optical interference. Next, on the other hand, the entire surface of the wafer is scanned in an area of 2 mm X 2 mm (this is called the window 1), and the height difference is obtained. This difference in height is given to the center of the window. Next, the horizontal axis represents the threshold value (threshold value), and the vertical axis represents the area ratio of the portion having the height difference exceeding the threshold value in the window. In this threshold curve, the threshold value at which the vertical axis is 0.05% is taken as the value of nanotopology.
  • Fig. 1 shows the relationship between the nanotopology of the second main surface obtained in this way and the hydrogen flow rate (sIm) / source gas flow rate (slm).
  • the curve in the graph is an approximate curve.
  • the ratio between the hydrogen gas flow rate and the raw material gas flow rate and the value of the nanotopology have a very strong correlation.
  • the ratio between the hydrogen gas flow rate and the raw material gas flow rate If hydrogen flow rate (slm) / source gas flow rate (slm) ⁇ 4, it can be seen that the nanotopology of the second major surface can be about 12 nm or less.
  • Such a nanotopology level is a high-quality epitaxial silicon wafer that cannot be visually confirmed and has few adverse effects in later processes.
  • the unevenness of the nanotopology can be sufficiently reduced. Further, in order to reduce the unevenness of the nanotopology, it is preferable to set the hydrogen flow rate (s l m) / source gas flow rate (s I m) to 5 or more. In this case, the nanotopology of the second main surface can be about 10 nm or less.
  • the upper limit value of the ratio of the hydrogen gas flow rate to the raw material gas flow rate is not particularly limited, but the upper limit value is limited depending on the specifications of the apparatus, for example, the hydrogen flow rate (slm) / the raw material gas flow rate. (Slm) should be 9 or less.
  • the ratio of the hydrogen gas flow rate to the raw material gas flow rate according to the present invention can be applied as it is.
  • a silicon wafer As a silicon wafer, a p-type silicon single crystal wafer having a diameter of 300 mm and a plane orientation (100) was prepared (a) and subjected to RCA cleaning (b).
  • the silicon wafer was loaded into an epitaxial growth apparatus having a susceptor having a large number of through holes as shown in Fig. 3 (c).
  • the temperature at loading was 700 ° C.
  • hydrogen gas was introduced into the chamber at a flow rate of 60 s I m, the temperature was raised to 1 1300 ° C for 45 seconds, and then hydrogen treatment was performed at 1 1300 ° C for 1 minute (d).
  • trichlorosilane was introduced into the chamber at a flow rate of 16 s I m and maintained at 1 1 30 ° C for 120 seconds for epitaxial growth. Went (e).
  • the hydrogen flow rate (sI m) / source gas flow rate (slm) is approximately 5.
  • Example 2 As in Example 1, however, an epitaxial silicon wafer was manufactured with a carrier hydrogen gas flow rate of 70 s I m in the epitaxial growth process. At this time, the hydrogen flow rate (s l m) / source gas flow rate (s l m) is approximately 4.38.
  • Example 2 As in Example 1, however, an epitaxial silicon wafer was manufactured with a carrier hydrogen gas flow rate of 60 s I m in the epitaxial growth process. At this time, the hydrogen flow rate (s l m) / source gas flow rate (s l m) is approximately 3.75.
  • Example 2 As in Example 1, however, an epitaxial silicon wafer was manufactured with a carrier hydrogen gas flow rate of 40 s I m in the epitaxial growth step. At this time, the hydrogen flow rate (s l m) / source gas flow rate (s l m) becomes approximately 2.5.
  • the area measured as nanotopology on the periphery of the second main surface is larger than that of Comparative Example 1.
  • a slight unevenness was observed in many places corresponding to the through holes of the susceptor on the periphery of the second main surface by visual inspection.

Abstract

Procédé de fabrication de plaquettes de silicium épitaxiales comprenant une étape consistant à éliminer une couche d'oxyde naturel et une étape de croissance épitaxiale. Dans ce procédé, une couche de silicium épitaxiale est cultivée au moyen d'un suscepteur à travers lequel sont percés de nombreux orifices, le rapport entre le débit d'hydrogène gazeux et le débit de gaz lors de l'étape de croissance épitaxiale satisfaisant à l'inégalité : débit d'hydrogène (slm)/débit de gaz (slm) ≥ 4. Ainsi, lorsque le suscepteur percé de nombreux orifices est utilisé pour la fabrication de la plaquette de silicium épitaxiale, l'irrégularité nanotopologique générée sur une seconde surface principale peut être réduite.
PCT/JP2007/001143 2006-10-27 2007-10-19 Procédé de fabrication d'une plaquette de silicium épitaxiale et plaquette de silicium épitaxiale WO2008050476A1 (fr)

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JP2006292577A JP5140990B2 (ja) 2006-10-27 2006-10-27 エピタキシャルシリコンウエーハの製造方法
JP2006-292577 2006-10-27

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KR101339591B1 (ko) * 2012-01-13 2013-12-10 주식회사 엘지실트론 서셉터
SE536605C2 (sv) * 2012-01-30 2014-03-25 Odling av kiselkarbidkristall i en CVD-reaktor vid användning av klorineringskemi

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04324625A (ja) * 1991-04-24 1992-11-13 Toshiba Mach Co Ltd 気相成長装置
JP2003229370A (ja) * 2001-11-30 2003-08-15 Shin Etsu Handotai Co Ltd サセプタ、気相成長装置、エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ
JP2003532612A (ja) * 2000-11-29 2003-11-05 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド オートドーピングおよび後面ハローがないエピタキシャルシリコンウエハ
JP2005020000A (ja) * 2003-06-26 2005-01-20 Siltronic Ag 半導体ウェハを搭載するためのサセプタ及び半導体ウェハを製造する方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04324625A (ja) * 1991-04-24 1992-11-13 Toshiba Mach Co Ltd 気相成長装置
JP2003532612A (ja) * 2000-11-29 2003-11-05 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド オートドーピングおよび後面ハローがないエピタキシャルシリコンウエハ
JP2003229370A (ja) * 2001-11-30 2003-08-15 Shin Etsu Handotai Co Ltd サセプタ、気相成長装置、エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ
JP2005020000A (ja) * 2003-06-26 2005-01-20 Siltronic Ag 半導体ウェハを搭載するためのサセプタ及び半導体ウェハを製造する方法

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