WO2008049290A1 - Équipement de traitement de semi-conducteurs - Google Patents

Équipement de traitement de semi-conducteurs Download PDF

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Publication number
WO2008049290A1
WO2008049290A1 PCT/CN2007/000543 CN2007000543W WO2008049290A1 WO 2008049290 A1 WO2008049290 A1 WO 2008049290A1 CN 2007000543 W CN2007000543 W CN 2007000543W WO 2008049290 A1 WO2008049290 A1 WO 2008049290A1
Authority
WO
WIPO (PCT)
Prior art keywords
length
angle
semiconductor processing
processing apparatus
shield plate
Prior art date
Application number
PCT/CN2007/000543
Other languages
English (en)
Chinese (zh)
Inventor
Sheng Lin
Original Assignee
Beijing Nmc Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Nmc Co., Ltd. filed Critical Beijing Nmc Co., Ltd.
Publication of WO2008049290A1 publication Critical patent/WO2008049290A1/fr

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor

Definitions

  • the present invention relates to a semiconductor wafer processing apparatus, and more particularly to a semiconductor processing apparatus having a lining structure. Background technique
  • Plasma etching techniques are widely used in etching processes for semiconductor fabrication such as gate etching, dielectric etching, and metal etching.
  • a typical semiconductor processing chamber includes a chamber, a plasma generation and control device, a process gas delivery device, a silicon chuck for wafer mounting, and process components (for controlling and defining gas flow and plasma presence regions, and The etching product is prevented from being adsorbed and deposited on the inner wall of the chamber which is difficult to be disassembled and cleaned, and the like.
  • the reaction gas is excited by RF power to generate ionization to form a plasma.
  • the plasma is composed of charged electrons and ions.
  • the gas in the reaction chamber can be absorbed in addition to ions. Energy and form a large number of reactive groups.
  • the reactive group forms a chemical reaction with the surface of the material to be etched and forms a volatile reactive product.
  • the reaction product is separated from the surface of the material to be etched and is evacuated from the cavity by a vacuum system.
  • the process gas entering the reaction chamber is activated by the plasma to etch the material of the wafer surface.
  • the non-uniform gas distribution within the reaction chamber will result in a large change in etch rate and uniformity across the wafer surface inside the chamber.
  • the current wafer size has increased from 100 mm to 300 mm, and the volume of the reaction chamber has increased correspondingly, making it more difficult to provide a more uniform gas distribution. Therefore, the reason for the large change in the etching rate and uniformity from the center to the periphery of the wafer is the non-uniformity of the gas distribution.
  • Another problem with plasma etching in semiconductor fabrication is that when many wafers are processed indoors, a film is formed on the walls of the processing chamber over time. This film buildup can cause any of the following two problems: First, the film can peel off the walls and infiltrate the particles into the processing chamber. As the device size of integrated circuit devices continues to decrease, the extent to which the particles are allowed to exist during processing drops dramatically, so it becomes more important to address the problem of particle formation on the walls during processing. Second, the film can change the RF ground path and thus affect the quality of the wafer obtained. Since it is undesirable to have any of the above, the process chamber must be subjected to a wet cleaning operation in which the walls of the process chamber are physically wiped to remove film buildup.
  • the wet cleaning of the process chamber is not preferred because it requires an off-line processing mode and thus reduces throughput.
  • some chambers have a lining structure to protect the walls of the process chamber. The application of the lining allows the film buildup to be easily replaced and cleaned with minimal downtime when it appears on the wall, thereby ensuring continuous and efficient production of the process chamber.
  • the semiconductor processing chamber liner shown in Fig. 1 is a schematic structural view of Chinese patent application CN1152414C, which includes a plasma confinement screen 116c having a plurality of apertures 128 extending upwardly from the plasma confinement screen 116c.
  • the outer flange 116a extends outwardly from the outer side wall 116b such that the outer flange extends to the outside and projects into the space under atmospheric pressure.
  • the interior liner further includes an inner sidewall 116d extending upwardly from the plasma confinement screen.
  • the lining patent effectively protects the interior walls of the treatment, reduces the formation of film buildup, and thereby reduces particulate contamination
  • the patent has at least the following drawbacks. That is, the range protected by the lining structure is too narrow, and the adjustment bracket below the quartz window and the pumping chamber below the constraining screen cannot be effectively protected, and the generation of particles cannot be avoided to the greatest extent, thereby causing contamination of the wafer;
  • the flow field in the reaction chamber provided by the structure especially the uniformity of the flow field on the surface of the silicon wafer, also has certain limitations, thereby limiting the further improvement of the flow field uniformity on the surface of the silicon wafer.
  • U.S. Patent 6,821,378 discloses a shield plate design using an asymmetric shield screen as shown in Figure 2 to slow the flow of process gases in the side draw etch chamber, thereby increasing silicon.
  • the shielding plate is designed for the side extraction type etching chamber, and the shielding screen is designed by using a circular hole, a square hole, a slot hole, etc., and when the slot type hole is designed, the shielding screen porosity (porosity is defined as the shielding mesh hole)
  • the ratio of the area to the screen area rather than the entire screen area is up to 90%.
  • the smaller the porosity of the shielding screen the lower the passing rate of the gas through the shielding screen and the slower the gas flow rate, and conversely, the airflow uniformity on the surface of the silicon wafer can be improved, and the etching result can be improved.
  • the shielding sieve porosity is 57% ⁇ 76%
  • the etching uniformity is obviously improved.
  • the porosity is 57%
  • the etching uniformity is most obviously improved, which can be increased by 50%.
  • a semiconductor processing apparatus comprising a cylindrical inner side wall and an outer side wall, a flange extending outward from the outer side wall, and a space between the inner side wall and the outer side wall a shielding plate, wherein the outer side wall extends upwardly from the upper surface of the flange upwardly or at an angle to a first length and extends downwardly from the shielding plate or downwardly at a certain angle to a second length; the inner side The wall extends a third length upwardly from the shield plate upwardly or at an angle and extends a fourth length downwardly from the shield plate downwardly or at an angle.
  • the shielding plate is stepped, and the upper and lower step surfaces of the shielding plate are provided with one or more rows of small holes uniformly distributed.
  • the inner and outer sidewalls of the semiconductor processing apparatus provided by the present invention are improved over the prior art: the outer sidewall extends vertically upward from the upper surface of the flange or upwardly at an angle and vertically downward from the shield Or extending a second length down a certain angle; the inner side wall is from the screen
  • the shield extends vertically upward or at an angle a third length and extends downwardly or downwardly from the shield panel a fourth length. Therefore, the semiconductor processing apparatus provided by the present invention can not only increase the protection area of the processing chamber, but also slow down the generation of the film product, thereby reducing the generation of particles.
  • the shield plate of the inner liner of the semiconductor processing apparatus provided by the invention can adopt various structures such as a stepped structure, which can not only improve the uniformity of the flow field, but also improve the velocity field of the flow field of the chamber, especially the surface of the silicon wafer, so that More even.
  • Figure 1 is a perspective view showing a prior art lining structure
  • Figure 2 shows a perspective view of a processing chamber including a shield according to the prior art
  • Figure 3 is a schematic perspective view showing a lining structure of a semiconductor processing apparatus according to the present invention.
  • Figure 4 is a side sectional view showing the lining structure according to the present invention;
  • Figure 5 is a partial enlarged view of the A area of Figure 4. detailed description
  • the lining structure 116 of the semiconductor processing apparatus of the present invention has an annular structure constituting an inner circumference and an outer circumference portion, i.e., the outer side wall 116b and the inner side wall 116d are both cylindrical and outer.
  • the wall 116b has a wafer access opening and several small viewing ports.
  • the lining shield plate 116c (116cl-116c3) is located in the annular columnar space formed by the outer side wall 116b and the inner side wall 116d.
  • the inner lining shielding plate 116c adopts a stepped structure, and the basic shape and the first step Similarly, the upper step 116cl and the lower step 116c2 and the side step (connection face) 116c3 connecting the two are specifically included.
  • the three step faces 116cl-116c3 are all limited to the annular columnar space formed by the inner side wall 116d and the outer side wall 116b of the inner liner, and the plurality of rows of small holes 170 which are uniformly arranged on the three step faces may be provided. In order to increase the passage area of the reaction gas, that is, to increase the porosity of the screen, thereby improving the uniformity.
  • the stepped structure of the lining shielding plate 116c is not limited to the first step shape shown in the embodiment, and may be a multi-stage step shape.
  • the upper step surface refers to the uppermost level.
  • the upper step of the step the lower step refers to the lower step of the lowermost step.
  • the side step height is in the range of 0 - 40mm. Different side-surface heights have different effects on the flow field uniformity of the reaction gas on the surface of the silicon wafer. The optimum surface uniformity of the wafer surface is obtained by selecting the appropriate side-surface height.
  • the connection between the side step surface and the upper and lower step surfaces is not limited to the vertical connection.
  • the outer side wall 116b extends upwardly from the upper surface of the outer flange 116a upwardly or at an angle upwardly a first length 116g, and from the lining shield plate 116c (i.e., from the junction of the inner shield plate 116c and the outer side wall 116b, in other words,
  • the inner wall 116d of the second length 116f 0 extends downwardly or at an angle downward from the upper step 116cl) from the inner shield shield 116c (ie, from the junction of the inner shield shield 116c and the inner sidewall 116d, in other words, Extending from the lower step 116c2) vertically upward or at an angle to the third length, and from the lining shield 116c (ie, from the junction of the lining shield 116c and the inner sidewall 116d, in other words, from the lower step 116c2
  • the fourth length 116e extends vertically downward or at an angle to achieve a greater range of protection for the adjustment bracket and the extraction chamber.
  • the shielding plate used in the semiconductor processing apparatus of the present invention is not limited to the stepped shape shown in the embodiment, and may be a diagonally placed straight or curved panel-shaped shielding plate, or may be a cross section thereof.
  • the shielding plate can improve the uniformity of the flow field, improve the velocity field of the flow field of the chamber, especially the surface of the silicon wafer, and satisfy the processing process.
  • the embodiments of the present invention have been disclosed in the drawings and the specification of the invention, and are in the Described in the book.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Analytical Chemistry (AREA)
  • Chemical Vapour Deposition (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Drying Of Semiconductors (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

L'invention concerne un équipement de traitement de semi-conducteurs (116) comprenant une paroi latérale interne (116d) et une paroi latérale externe (116b) colonnaires, une bride (116a) s'étendant vers l'extérieur depuis la paroi latérale externe, et une plaque de blindage (116c) entre la paroi latérale interne et la paroi latérale externe, la paroi latérale externe s'étendant vers le haut perpendiculairement ou selon un certain angle par rapport à la surface supérieure de la bride sur une première longueur (116g) et la paroi latérale externe s'étendant vers le bas perpendiculairement ou selon un certain angle par rapport à la plaque de blindage sur une deuxième longueur (116f) ; la paroi latérale interne s'étendant vers le haut perpendiculairement ou selon un certain angle par rapport à la plaque de blindage sur une troisième longueur et vers le bas perpendiculairement ou selon un certain angle par rapport à la plaque de blindage sur une quatrième longueur (116e) ; la plaque de blindage étant en forme de marches, et la surface de la marche supérieure et la surface de la marche inférieure étant pourvues de rangées d'ouvertures (170) distribuées uniformément.
PCT/CN2007/000543 2006-10-20 2007-02-14 Équipement de traitement de semi-conducteurs WO2008049290A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN200610113918.2 2006-10-20
CN200610113918A CN101165868B (zh) 2006-10-20 2006-10-20 晶片处理室的内衬及包含该内衬的晶片处理室

Publications (1)

Publication Number Publication Date
WO2008049290A1 true WO2008049290A1 (fr) 2008-05-02

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2007/000543 WO2008049290A1 (fr) 2006-10-20 2007-02-14 Équipement de traitement de semi-conducteurs

Country Status (3)

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CN (1) CN101165868B (fr)
SG (1) SG160413A1 (fr)
WO (1) WO2008049290A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104916564B (zh) * 2014-03-13 2018-01-09 北京北方华创微电子装备有限公司 反应腔室以及等离子体加工设备
CN105097607B (zh) * 2014-05-22 2019-02-19 北京北方华创微电子装备有限公司 一种反应腔室及其清洗方法
CN108899295A (zh) * 2018-07-06 2018-11-27 宁波江丰电子材料股份有限公司 蚀刻腔室以及蚀刻腔室加工方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5788799A (en) * 1996-06-11 1998-08-04 Applied Materials, Inc. Apparatus and method for cleaning of semiconductor process chamber surfaces
CN1327612A (zh) * 1999-09-23 2001-12-19 兰姆研究公司 具有平铺式瓷衬的半导体加工设备
CN1333917A (zh) * 1998-09-30 2002-01-30 拉姆研究公司 用于半导体处理室的室衬
US20050109276A1 (en) * 2003-11-25 2005-05-26 Applied Materials, Inc. Thermal chemical vapor deposition of silicon nitride using BTBAS bis(tertiary-butylamino silane) in a single wafer chamber

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5589737A (en) * 1994-12-06 1996-12-31 Lam Research Corporation Plasma processor for large workpieces
US6227140B1 (en) * 1999-09-23 2001-05-08 Lam Research Corporation Semiconductor processing equipment having radiant heated ceramic liner
US7147749B2 (en) * 2002-09-30 2006-12-12 Tokyo Electron Limited Method and apparatus for an improved upper electrode plate with deposition shield in a plasma processing system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5788799A (en) * 1996-06-11 1998-08-04 Applied Materials, Inc. Apparatus and method for cleaning of semiconductor process chamber surfaces
CN1333917A (zh) * 1998-09-30 2002-01-30 拉姆研究公司 用于半导体处理室的室衬
CN1327612A (zh) * 1999-09-23 2001-12-19 兰姆研究公司 具有平铺式瓷衬的半导体加工设备
US20050109276A1 (en) * 2003-11-25 2005-05-26 Applied Materials, Inc. Thermal chemical vapor deposition of silicon nitride using BTBAS bis(tertiary-butylamino silane) in a single wafer chamber

Also Published As

Publication number Publication date
CN101165868A (zh) 2008-04-23
SG160413A1 (en) 2010-04-29
CN101165868B (zh) 2010-05-12

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