WO2008035698A1 - Circuit à atténuation variable - Google Patents

Circuit à atténuation variable Download PDF

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Publication number
WO2008035698A1
WO2008035698A1 PCT/JP2007/068152 JP2007068152W WO2008035698A1 WO 2008035698 A1 WO2008035698 A1 WO 2008035698A1 JP 2007068152 W JP2007068152 W JP 2007068152W WO 2008035698 A1 WO2008035698 A1 WO 2008035698A1
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WO
WIPO (PCT)
Prior art keywords
signal
attenuation
fet
circuit
bias
Prior art date
Application number
PCT/JP2007/068152
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English (en)
Japanese (ja)
Inventor
Takahito Miyazaki
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Panasonic Corporation
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Publication of WO2008035698A1 publication Critical patent/WO2008035698A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0035—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements
    • H03G1/007—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements using FET type devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/24—Frequency-independent attenuators
    • H03H11/245—Frequency-independent attenuators using field-effect transistor

Definitions

  • the present invention relates to a variable attenuation circuit and a high-frequency wireless circuit system using the same.
  • the variable attenuation circuit of the present invention is used for attenuation of high-frequency signals in various wireless communication devices. It realizes linear attenuation control characteristics, improves noise characteristics, and electrical characteristics of elements depending on the manufacturing process and temperature. This is intended to compensate for variations in the quality.
  • FIG. 2 is a circuit diagram showing a configuration of a conventional variable attenuation circuit using a GaAsFET (see JP 2005-27062 A).
  • the conventional variable attenuating circuit is attenuated by a signal attenuating unit 260 including a signal attenuating GaAs FET 240 in which a high frequency signal inputted from a signal input terminal (IN) 231 is inserted in series. Output from the signal output terminal (OUT) 232.
  • the high frequency signal input from the signal input terminal 231 includes a signal attenuation GaAsFET 245 inserted between the signal input terminal 231 and the ground terminal (GND) 236.
  • the signal attenuation unit 261, the signal output terminal 232, and the ground terminal The signal is attenuated by a signal attenuating unit 262 including a signal attenuating GaAsFET 251 inserted between the signal output terminal 232 and the signal attenuating unit 237.
  • the attenuation amount of the signal attenuation GaAsFETs 240, 245, and 251 can be controlled by the attenuation amount control signal input from the attenuation amount control terminal (Vc) 233.
  • a resistor 255 for supplying a gate bias is provided between the attenuation control terminal 233 and the gate of the GaAsFET 240 for signal attenuation
  • a resistor 222 for supplying a drain bias is provided between the attenuation control terminal 233 and the source of the GaAsFET 245 for signal attenuation 259.
  • a drain bias supply resistor 256 is provided between the attenuation control terminal 233 and the source of the signal attenuation GaAsFET 251.
  • a source bias supply resistor 239 is provided between the source bias supply terminal (Vref 1) 234 of the signal attenuation GaAsFET 240 and the source of the signal attenuation GaAsFET 240, and the gate bias of the signal attenuation GaAsFETs 245 and 251.
  • Gate bias supply resistors 257 and 258 are provided between the supply terminal (Vref2) 235 and the gates of the signal attenuation Ga AsFETs 245 and 251, respectively.
  • a drain bias supply resistor 241 is provided between the source and drain of the signal attenuation GaAsFET 240, 245, 251 respectively.
  • a source potential supply resistor 246 and a source potential supply resistor 252 are provided.
  • Reference numerals 238, 242, 243, 248, 249, and 254 denote DC blocking capacities
  • reference numerals 244, 247, 250, and 253 denote input / output matching resistors, respectively.
  • This variable attenuation circuit uses the attenuation control signal supplied from the attenuation control terminal 233, the signal attenuation GaAsFET 240 inserted in series, the signal attenuation GaAsFET 245 inserted in the shunt, By connecting to the 251 source terminal, it is possible to control three attenuation GaAsFETs 240, 245, 251 with one type of attenuation control signal.
  • a variable attenuation circuit has a signal attenuation GaAsFET 240 that is controlled by continuously changing the voltage at the attenuation control terminal 233, the force that requires linearity of its control characteristics from a high attenuation state to a low attenuation state.
  • Low resistance, GaAsFET 245 and 251 for signal attenuation can be controlled to the desired attenuation from low attenuation state with high resistance to GaAsFET 240 for signal attenuation and high resistance to GaAsFET 245 and 251 for signal attenuation with low resistance.
  • the high-frequency variable attenuation circuit configured on a single substrate such as a GaAs substrate has also been fabricated on the same Si semiconductor substrate as other semiconductor circuits such as oscillators and mixers. As a result, it has become necessary to fabricate a high-frequency variable attenuation circuit on a Si substrate that has a lower substrate resistance than GaAs processes.
  • the second problem is that noise characteristics deteriorate due to noise generated in the control circuit mixed into the high-frequency circuit.
  • the noise generated in the control circuit is mixed into the high-frequency signal line via the gate of the signal attenuation MOSFET, and the recent severe resolution characteristics corresponding to the multi-communication system are not satisfied! Power S can be raised.
  • the fourth point is the influence of variations due to manufacturing processes and temperature fluctuations.
  • variable attenuation circuits more stringent linearity is required, and there is a problem that the desired linearity is not satisfied with respect to attenuation control characteristics due to variations in threshold voltage of MOSFET for signal attenuation due to manufacturing process and temperature fluctuation. is there.
  • the fifth point is that when a high-frequency circuit is fabricated on a Si semiconductor substrate, the signal of Leakage is a problem.
  • the variable attenuation circuit it is necessary to add a resistor between the source and the drain in order to supply the source bias and drain bias and to improve the frequency characteristics. There is a problem if the attenuation control characteristics deteriorate!
  • an object of the present invention is to provide a variable attenuation circuit that has linear attenuation control characteristics and excellent noise characteristics, and is resistant to variations in MOSFET thresholds due to the manufacturing process and temperature, and a high-frequency radio circuit system using the same Is to provide.
  • a variable attenuation circuit is a variable attenuation circuit in which the first, second, third, and fourth points of the above-mentioned problem have been solved.
  • the variable attenuation circuit includes a signal attenuating unit having a signal attenuating element inserted in series in a signal path between the signal input unit and the signal output unit, an attenuation control circuit unit for controlling the signal attenuating element, And a bias circuit section that provides a bias that compensates for variations in the manufacturing process of the signal attenuating element and temperature variation, and has a capacitance between the connection between the signal attenuating element and the attenuation control circuit and the ground terminal.
  • the signal attenuating element has a configuration for attenuating the high-frequency signal with an attenuation amount corresponding to the attenuation amount control signal generated by the attenuation amount control circuit unit.
  • the signal attenuating element is generally preferably an FET, particularly a MOSFET.
  • the attenuation control circuit section for controlling the signal attenuating element is connected to the gate terminal of the signal attenuating FET that is the signal attenuating element.
  • the noise circuit section is made up of FETs that have the same manufacturing process as the signal attenuating FETs, with variations in temperature fluctuations, and the source terminals and drains of the signal attenuating FETs are connected via source bias resistors and drain bias resistors. Connected to the terminal. Capacitance is inserted between the gate terminal and ground terminal of the signal attenuation FET.
  • the signal attenuating FET well has a triple well structure, and a resistor having a high resistance value is inserted between the back gate and the substrate.
  • the capacitance is provided between the gate terminal and the ground terminal of the signal attenuation FET, the capacitance between the drain and the gate of the signal attenuation FET and the capacitance between the gate and the source are increased. Therefore, it is possible to block the signal leakage path and improve the attenuation characteristics during high isolation.
  • the attenuation control circuit unit composed of resistors, etc. Noise generated can be prevented from entering the high-frequency signal line via the gate of the signal attenuation FET, and noise characteristics can be improved. As a result, the first and second issues can be solved.
  • the signal attenuating FET has a triple-well structure, and a high resistance is inserted between the back gate and the substrate, so that the back gate of the signal attenuating FET is Thus, the path through which the signal leaks to the substrate can be blocked, and the attenuation control characteristic can be improved. As a result, the third problem can be solved.
  • the same manufacturing process as the signal attenuating FET 'For signal attenuating by applying a source bias to the signal attenuating FET in the bias circuit configured using FET that has a threshold variation of temperature fluctuation The FET threshold manufacturing process and temperature variations can be corrected.
  • the bias value generated by the (source) bias circuit section decreases when the threshold voltage of the signal attenuation FET increases due to the manufacturing process' temperature fluctuation, and conversely the threshold voltage of the signal attenuation FET. It is preferably controlled so that it increases when the value decreases.
  • a variable attenuation circuit is a variable attenuation circuit that solves the second, third, and fourth points of the above problems.
  • the variable attenuation circuit includes a signal attenuation unit having a signal attenuation element inserted into a ground terminal from a signal path between a signal input unit and a signal output unit, and an attenuation amount control circuit for controlling the signal attenuation element. And a bias circuit section that provides a bias that compensates for the manufacturing process and temperature variation of the signal attenuating element, and a capacitance is provided between the connection between the signal attenuating element and the attenuation control circuit section and the ground terminal.
  • the signal attenuating element has a configuration for attenuating the high-frequency signal with an attenuation amount corresponding to the attenuation amount control signal generated by the attenuation amount control circuit unit.
  • the signal attenuating element is generally preferably an FET.
  • the attenuation control circuit unit for controlling the signal is connected to the source terminal of the signal attenuating FET which is a signal attenuating element.
  • the noise circuit section is configured using a FET that has the same manufacturing process as the signal attenuating FET and temperature variation variation, and is connected to the gate terminal of the signal attenuating FET.
  • the capacitor is inserted between the gate terminal and the ground terminal of the signal attenuation FET.
  • the signal attenuating FET has a triple-well structure, and a high resistance is inserted between the back gate and the substrate.
  • the signal attenuating FET has a triple-well structure, and a resistor having a high resistance is inserted between the back gate and the substrate.
  • a resistor having a high resistance is inserted between the back gate and the substrate.
  • the same manufacturing process as the signal attenuating FET 'For signal attenuating by applying a gate bias to the signal attenuating FET in the bias circuit configured using FET with a threshold variation of temperature fluctuation The FET threshold manufacturing process and temperature variations can be corrected.
  • the bias value generated in the (gate) bias circuit section increases when the threshold voltage of the signal attenuation FET increases due to temperature fluctuations in the manufacturing process, and conversely the threshold voltage of the signal attenuation FET. It is preferable to control to decrease when the value decreases.
  • a variable attenuation circuit is a variable attenuation circuit that solves the first, second, third, fourth, and fifth points of the above-described problem.
  • This variable attenuation circuit has signal input and signal output A signal attenuating unit having a signal attenuating element inserted in series in the signal path between the signal attenuating unit, an attenuation control circuit unit for controlling the signal attenuating element, and correcting the manufacturing process and temperature variation of the signal attenuating element A bias circuit section for applying a bias, a capacitance between a connection section between the signal attenuation element and the attenuation control circuit and the ground terminal, and a signal attenuation element and a noise circuit section.
  • the signal attenuating element attenuates the high-frequency signal with an attenuation corresponding to the attenuation control signal generated by the attenuation control circuit. Have the configuration to do! /
  • the signal attenuating element is generally preferably an FET.
  • the attenuation control circuit that controls the signal attenuating element is connected to the gate terminal of the signal attenuating FET that is the signal attenuating element, and the bias circuit is the same manufacturing process as the signal attenuating FET. It is configured using a FET that has a signal bias, and is connected to the source and drain terminals of the signal attenuating FET via a source bias resistor and drain bias resistor.
  • the capacitance added to the connection between the signal attenuating element and the attenuation control circuit is inserted between the gate terminal of the signal attenuating FET and the ground terminal, and the connection between the signal attenuating element and the bias circuit section
  • the capacitance added to the block is inserted between the connection between the source bias resistor and drain bias resistor of the signal attenuating FET and the ground terminal.
  • the signal attenuating FET has a triple-well structure, and a resistor having a high resistance value is inserted between the back gate and the substrate.
  • the capacitance between the gate terminal and the ground terminal of the signal attenuating FET increases the capacitance between the drain and the gate of the signal attenuating FET and the capacitance between the gate and the source. Therefore, it is possible to block the signal leakage path and improve the attenuation characteristics during high isolation.
  • the signal attenuating FET has a triple-well structure, and a resistor having a high resistance value is inserted between the back gate of the signal attenuating FET and the substrate. A path through which a signal leaks to the substrate is blocked, and the attenuation control characteristic can be improved. As a result, the third problem can be solved.
  • the same manufacturing process as the signal attenuating FET ⁇ By providing a source bias for the signal attenuating FET in the bias circuit configured using a FET that has a threshold variation due to temperature fluctuations, the signal attenuating FET The threshold manufacturing process and temperature variations can be corrected. As a result, the fourth problem can be solved.
  • the bias value generated by the (source) bias circuit decreases when the threshold voltage of the signal attenuation FET increases due to temperature fluctuations in the manufacturing process, and conversely the threshold value of the signal attenuation FET. It is preferable that the voltage is controlled so as to increase when the voltage decreases.
  • the signal leakage path can be cut off more than the variable attenuation circuit of the first invention, and the noise leakage path equivalent to the circuit of the first invention can be cut off.
  • the stabilization of the threshold voltage can be achieved, and the original performance of the transistor, such as attenuation characteristics and noise characteristics, can be maximized.
  • a linear attenuation control characteristic can be realized in any attenuation state that changes continuously, and a variable attenuation circuit that has excellent noise characteristics and is resistant to variations can be realized.
  • a high-frequency radio circuit system includes at least one first, second, or second
  • a wireless transmission device including the variable attenuation circuit according to the third aspect of the invention, at least one oscillator, and at least one high-frequency amplifier, and at least one antenna connected to the wireless transmission device for transmitting and receiving a radio frequency.
  • a first variable attenuation circuit of the present invention includes a signal attenuator having a signal attenuating element inserted in series in a signal path between a signal input unit and a signal output unit, and a signal attenuating element.
  • Attenuation control circuit section for supplying an attenuation control signal, bias circuit section for applying a bias to the signal attenuation element, and a connection between the signal attenuation element and the attenuation control circuit section and the ground terminal.
  • the signal attenuating element is an FET
  • the attenuation control circuit section applies an attenuation control signal to the gate terminal of the FET to control the ON resistance of the FET.
  • the bias circuit section applies a bias to the source terminal of the FET, and the capacitance is connected between the gate terminal of the FET and the ground terminal.
  • the second variable attenuation circuit of the present invention includes a signal attenuator having a signal attenuating FET inserted in series in a signal path between the signal input unit and the signal output unit, and a signal attenuating FET.
  • An attenuation control circuit that controls the ON resistance of the signal attenuating FET by giving an attenuation control signal to the gate terminal, and a bias circuit that applies a bias to the source terminal of the signal attenuating FET.
  • the circuit section has a bias FET that compensates for variations in the threshold voltage of the signal attenuating FET.
  • the third variable attenuation circuit of the present invention includes a signal attenuator having a signal attenuating FET inserted in series in a signal path between the signal input unit and the signal output unit, and a signal attenuating FET. Attenuation control circuit that controls the ON resistance of the signal attenuation FET by applying an attenuation control signal to the gout terminal, a bias circuit that applies a bias to the source terminal of the signal attenuation FET, and a signal attenuation FET And a resistor connected between the back gate portion and the substrate.
  • a fourth variable attenuation circuit of the present invention includes a signal attenuation unit having a signal attenuation FET inserted in series in a signal path between a signal input unit and a signal output unit, and a signal attenuation FET.
  • Attenuation control circuit that controls the ON resistance of the signal attenuation FET by applying an attenuation control signal to the gate terminal, a bias circuit that applies a bias to the source terminal of the signal attenuation FET, and a bias circuit
  • a capacitor or a capacitor and a switch connected to the ground terminal are provided.
  • FET is inserted into the signal path between the signal input unit and the signal output unit, and the signal applied to the gate terminal of this FET is applied to the signal input unit.
  • a signal attenuator that controls and outputs the attenuation of a given signal
  • an attenuation control circuit that applies a signal to the gate terminal to vary the ON resistance value of the FET, and a terminal connected to the source terminal of the FET
  • a first capacitive element is connected between the other end of the resistive element and the ground terminal, and a bias circuit section that applies a DC voltage via the resistive element is connected between the back gate section of the FET and the ground terminal.
  • a second capacitor element between the gate terminal and the ground terminal. Is connected.
  • a sixth variable attenuation circuit of the present invention includes a signal attenuation unit having a signal attenuation element inserted between a signal path between the signal input unit and the signal output unit and the ground terminal,
  • An attenuation control circuit unit for providing an attenuation control signal to the signal attenuation element
  • a bias circuit section for applying a bias to the signal attenuating element
  • the signal attenuating element comprises a FET
  • the attenuation control circuit unit applies an attenuation control signal to the drain terminal of the FET to control the ON resistance of the FET
  • the bias circuit section applies a bias to the gate terminal of the FET
  • the capacitance is connected between the gate terminal of the FET and the ground terminal.
  • a seventh variable attenuation circuit of the present invention includes a signal attenuation unit including a signal attenuation FET inserted between a signal path between the signal input unit and the signal output unit and a ground terminal, and a signal Provided with an attenuation control circuit that controls the ON resistance of the signal attenuation FET by giving an attenuation control signal to the drain terminal of the attenuation FET and a bias circuit that applies a bias to the gate terminal of the signal attenuation FET
  • the bias circuit section has a bias FET that compensates for variations in the threshold voltage of the signal attenuating FET.
  • An eighth variable attenuation circuit of the present invention includes a signal attenuation unit having a signal attenuation FET inserted between a signal path between a signal input unit and a signal output unit and a ground terminal, and a signal Attenuation control circuit that controls the ON resistance of the signal attenuation FET by applying an attenuation control signal to the drain terminal of the attenuation FET, a bias circuit that applies a bias to the gate terminal of the signal attenuation FET, and a signal Provided with a resistor connected between the back gate of the attenuating FET and the substrate
  • the first capacitive element and the FET current path terminal pair are connected in series between the signal path between the signal input section and the signal output section and the AC ground.
  • a signal attenuator that controls the amount of attenuation of the signal applied to the signal input by the signal applied to the connection between the first capacitor element and one end of the current path of the FET that is inserted and connected, and the FET Attenuation control circuit that applies a signal to one end to vary the ON resistance of the FET, and the gate of the FET
  • a bias circuit section for applying a DC voltage to the terminal via a resistance element; a resistor connected between the back gate section of the FET and the ground terminal; and a second capacitive element between the gate terminal and the ground terminal. Is connected.
  • a tenth variable attenuation circuit includes a first signal attenuation unit having a first signal attenuation element inserted in series in a signal path between a signal input unit and a signal output unit; A first attenuation control circuit for supplying an attenuation control signal to the first signal attenuation element, a first bias circuit for applying a bias to the first signal attenuation element, and a first signal attenuation Between the first capacitor connected between the connection between the element and the first attenuation control circuit section and the ground terminal, and between the signal path between the signal input section and the signal output section and the ground terminal.
  • a second signal attenuating unit having a second signal attenuating element inserted; a second attenuation control circuit for supplying an attenuation control signal to the second signal attenuating element; and a second signal attenuating unit.
  • a second noise circuit section for applying a bias to the device, a connection between the second signal attenuating element and the second bias circuit section, and grounding And a second capacitor connected between the child.
  • the first signal attenuating element is composed of the first FET force, and the first attenuation control circuit unit is attenuated to the gate terminal of the first FET.
  • the first bias circuit block applies a bias to the source terminal of the first FET, and the first capacitor is grounded with the gate terminal of the first FET.
  • the second signal attenuating element is composed of the second FET, and the second attenuation control circuit section applies the attenuation control signal to the drain terminal of the second FET to provide the second FET.
  • the ON resistance of the FET is controlled, the second bias circuit section applies a bias to the gate terminal of the second FET, and the second capacitor is connected between the gate terminal of the second FET and the ground terminal.
  • it is.
  • An eleventh variable attenuation circuit of the present invention includes a first signal attenuation unit having a first signal attenuation FET inserted in series in a signal path between a signal input unit and a signal output unit.
  • the first attenuation control circuit that controls the ON resistance of the first signal attenuation FET by applying an attenuation control signal to the gate terminal of the first signal attenuation FET, and the first signal attenuation FET
  • a second bias circuit section having a first bias circuit section for applying noise to the source terminal, and a second signal attenuating FET inserted between the signal path between the signal input section and the signal output section and the ground terminal.
  • Attenuation control signals are applied to the signal attenuator and the drain terminal of the second signal attenuating FET to reduce the second signal.
  • the first bias circuit includes a second attenuation control circuit that controls the ON resistance of the attenuation FET, and a second bias circuit that applies a bias to the gate terminal of the second signal attenuation FET.
  • Part has a first bias FET that compensates for variations in threshold voltage of the first signal attenuating FET,
  • the second bias circuit section includes a second bias FET that compensates for variations in threshold voltage of the second signal attenuating FET.
  • a twelfth variable attenuation circuit includes a first signal attenuation unit having a first signal attenuation FET inserted in series in a signal path between a signal input unit and a signal output unit.
  • the first attenuation control circuit that controls the ON resistance of the first signal attenuation FET by applying an attenuation control signal to the gate terminal of the first signal attenuation FET, and the first signal attenuation FET
  • a second bias circuit section having a first bias circuit section for applying noise to the source terminal, and a second signal attenuating FET inserted between the signal path between the signal input section and the signal output section and the ground terminal.
  • a second attenuation control circuit for controlling the ON resistance of the second signal attenuation FET by supplying an attenuation control signal to the drain terminal of the second signal attenuation FET,
  • a second bias circuit for applying a bias to the gate terminal of the signal attenuating FET, and a back gate for the first signal attenuating FET.
  • a thirteenth variable attenuation circuit of the present invention includes a first signal attenuation unit having a first signal attenuation FET inserted in series in a signal path between a signal input unit and a signal output unit.
  • the first attenuation control circuit that controls the ON resistance of the first signal attenuation FET by applying an attenuation control signal to the gate terminal of the first signal attenuation FET, and the first signal attenuation FET
  • a second bias circuit section having a first bias circuit section for applying noise to the source terminal, and a second signal attenuating FET inserted between the signal path between the signal input section and the signal output section and the ground terminal.
  • a second attenuation control circuit for controlling the ON resistance of the second signal attenuation FET by supplying an attenuation control signal to the drain terminal of the second signal attenuation FET,
  • the second bias circuit section that applies a bias to the gate terminal of the signal attenuation FET, and the first bias circuit section and the ground terminal It has a connected capacity or capacity and switch.
  • the back gate of the first signal attenuation FET Preferably, a first resistor is connected between the first terminal and the ground terminal, and a second resistor is connected between the back gate section of the second signal attenuating FET and the ground terminal.
  • a high frequency radio circuit system includes a radio including at least one variable attenuation circuit including at least one of the variable attenuation circuits according to the present invention, at least one high frequency amplification circuit, and at least one oscillator.
  • the transmitter includes a transmitter and an antenna that is connected to the radio transmitter and transmits a radio frequency.
  • the path for signal leakage through the parasitic capacitance generated between the drain gate and the gate source of the signal attenuation FET is interrupted.
  • the isolation characteristic at the time of attenuation can be improved.
  • a resistor with a high resistance between the back gate of the signal attenuation FET and the substrate the path through which the signal leaks to the substrate through the back gate is blocked to improve the attenuation control characteristics. be able to.
  • FIG. 1 is a circuit diagram showing a circuit configuration of a variable attenuation circuit according to Embodiment 1 of the present invention.
  • Figure 2 shows a conventional example of a variable attenuation circuit fabricated using the GaAs process.
  • FIG. 3 is a circuit diagram showing a circuit configuration of a variable attenuation circuit according to Embodiment 2 of the present invention.
  • FIG. 4 is a circuit diagram showing a circuit configuration of the variable attenuation circuit according to the third embodiment of the present invention.
  • FIG. 5 is a block diagram showing a circuit configuration of the variable attenuation circuit according to the fourth embodiment of the present invention.
  • FIG. 6 is a circuit diagram showing a circuit configuration of the variable attenuation circuit according to the fourth embodiment of the present invention.
  • FIG. 7 is a block diagram showing an example of a high-frequency wireless transmission circuit system to which the present invention is applied.
  • FIG. 8 is a schematic diagram showing fluctuation of each bias value of the MOSFET with respect to temperature in the conventional variable attenuation circuit as shown in FIG.
  • FIG. 9 is a schematic diagram showing the attenuation amount of the variable attenuation circuit with respect to the control voltage in the conventional variable attenuation circuit as shown in FIG.
  • FIG. 10 is a schematic diagram showing fluctuations of each bias value of the MOSFET with respect to temperature in the variable attenuation circuit of FIGS. 1 and 4 in Example 1 and Example 3 of the present invention.
  • FIG. 11 is a schematic diagram showing the attenuation amount of the variable attenuation circuit with respect to the control voltage in the variable attenuation circuit of FIGS. 1 and 4 in Example 1 and Example 3 of the present invention.
  • FIG. 12 is a schematic diagram showing fluctuation of each bias value of the MOSFET with respect to temperature in the variable attenuation circuit of FIG. 3 in Example 2 of the present invention.
  • FIG. 13 is a schematic diagram showing the attenuation amount of the variable attenuation circuit with respect to the control voltage in the variable attenuation circuit of FIG. 3 in Example 2 of the present invention.
  • FIG. 14A is a diagram showing a simulation result of the attenuation with respect to the control voltage in the variable attenuation circuit of FIG. 4 and the conventional variable attenuation circuit in Example 3 of the present invention.
  • FIG. 14B shows a variable attenuation circuit of FIG. 4 in Example 3 of the present invention and a conventional variable attenuation circuit. It is a figure which shows the simulation result of the noise characteristic with respect to control voltage in an attenuation circuit.
  • FIG. 15A is a diagram showing a simulation result of attenuation with respect to control voltage in the variable attenuation circuit of FIG. 6 and the conventional variable attenuation circuit in Example 4 of the present invention.
  • FIG. 15B is a diagram showing simulation results of noise characteristics with respect to control voltage in the variable attenuation circuit in FIG. 6 and the conventional variable attenuation circuit in Example 4 of the present invention.
  • FIG. 16 is a block diagram showing a circuit configuration of a conventional variable attenuation circuit.
  • Embodiment 1 of the present invention is a variable attenuation circuit (integrated circuit) corresponding to the first, second, third, and fourth points of the problem. This will be described below with reference to FIG.
  • the variable attenuation circuit according to the first embodiment of the present invention shown in FIG. 1 is an attenuation circuit that attenuates a high frequency signal input from the signal input terminal 104 and outputs the attenuated signal from the signal output terminal 105.
  • a variable attenuation circuit that can be controlled from the attenuation control terminal 106 is assumed.
  • this variable attenuation circuit is assumed to be fabricated on, for example, a Si semiconductor substrate.
  • the variable attenuation circuit according to the present invention includes a signal attenuation MOSFET (signal attenuation element) 111 inserted in series between the signal input terminal 104 and the signal output terminal 105.
  • MOSFET signal attenuation element
  • the signal attenuation MOSFET 111 includes an attenuation unit 100, an attenuation amount control circuit unit 101 that controls the ON resistance of the signal attenuation MOSFET 111, and a source bias circuit unit 102 that applies a bias to the source of the signal attenuation MOSFET 111.
  • the high frequency signal is attenuated by an attenuation amount corresponding to the attenuation amount control signal generated by the amount control circuit unit 101.
  • First point force Attenuation control circuit unit 101 prevents noise component force S from entering the high-frequency signal line (the line from signal input terminal 104 to signal output terminal 105) via the gate of MOSFET 111 for signal attenuation. It is. Prevents leakage of high-frequency signals between the signal input terminal 104 and the signal output terminal 105 in the high attenuation state due to the influence of parasitic capacitance generated between the drain gate of the second-point force S and the MOSFET 111 for signal attenuation and between the gate and source. That is.
  • the source bias circuit unit 102 of this variable attenuation circuit generates the bias voltage using the source bias generation MOSFET 117 having the same threshold voltage / variation (temperature characteristic) as the signal attenuation MOSFET 111!
  • the manufacturing process of the signal attenuating MOSFET 111 has an effect of correcting variations in threshold voltage due to temperature fluctuations.
  • the signal attenuating MOSFET 111 of this variable attenuating circuit has a triple-well structure, and a resistor 124 having a high resistance value is additionally provided between the back gate portion and the substrate. The effect of the resistor 124 having this high resistance value is to prevent a signal from leaking to the substrate through the back gate.
  • the signal attenuating element for example, an N-channel MOS FET having a triple-well structure is suitable.
  • the signal attenuating MOSFET 111 is inserted in series in the signal path between the signal input terminal 104 and the signal output terminal 105 of the high frequency variable attenuating circuit, and between the signal input terminal 104 and the signal attenuating MOSFET 111.
  • the DC component is cut off and the high frequency
  • a DC blocking capacitor 112 that passes only the component is inserted, and a DC blocking capacitor 113 is inserted between the signal attenuation MOSFET 111 and the signal output terminal 105.
  • a resistor 124 having a high resistance value is inserted to block signal leakage.
  • the attenuation control circuit unit 101 is connected to the gate of the signal attenuation MOSFET 111.
  • the configuration of the attenuation control circuit unit 101 will be described.
  • the attenuation control resistor 115 and the attenuation control resistor 116 are connected in series.
  • the other end of the attenuation control resistor 115 is connected to the attenuation control terminal (Vc) 106, and the other end of the resistor 116 is connected.
  • One terminal is connected to the ground terminal.
  • a resistor 114 having a high resistance value that cuts off high frequency and allows only DC to pass. It is connected.
  • a capacitor 103 is added between the gate of the signal attenuating MOSFET 111 and the ground terminal.
  • the source bias circuit section 102 connected to the source terminal of the signal attenuating MOSFET 111 will be described.
  • the resistor 120 and the resistor 121 are connected in series, the other terminal of the resistor 120 is connected to the power supply voltage terminal (Vdd) 107, and the other terminal of the resistor 121 is connected to the ground terminal.
  • the gate of the source bias generating MOSFET 117 is connected to the connection portion between the resistor 120 and the resistor 121, and the source bias generating MOSFET 117 has the same manufacturing process and temperature variation variation as the signal attenuating MOSFET 111.
  • a resistor 118 is connected between the drain of the source bias generating MOSFET 117 and the power supply voltage terminal 107, and a resistor 119 is connected between the source of the source bias generating MOSFET 117 and the ground terminal. Also, a resistor 122 having a high resistance value that cuts off the high frequency and passes only DC is connected between the source of the source bias generating MOSFET 117 and the source of the signal attenuating MOSFET 111. A resistor 123 having a resistance value is connected between the drain of the MOSFET 111 for attenuating and high so that only a DC is allowed to pass through the high frequency!
  • wireless communication systems have become multiband and multicommunication systems!
  • multi-communication systems such as UMTS communication system and GSM communication system.
  • the UMTS communication system requires a transmission power variable range of 80 dB or more in the transmission circuit. Highly accurate transmission power control linearity is required.
  • the GSM communication system requires high noise characteristics.
  • the variable attenuation circuit used in the high-frequency radio transmission circuit block must satisfy the characteristics of these two communication methods. In that case, process variations and high linearity and noise characteristics are required regardless of temperature fluctuations. Explain how to satisfy each requirement!
  • FIG. 8 (A) and (B) are diagrams showing fluctuations of each voltage value with respect to the temperature of the variable attenuation circuit as shown in FIG. 2, and FIG. 9 is a diagram showing gain characteristics with respect to the control voltage.
  • the horizontal axis represents temperature and the vertical axis represents voltage.
  • the horizontal axis represents the attenuation control voltage Vc, and the vertical axis represents the gain of the variable attenuation circuit. It shows three control characteristics at normal temperature (for example, 25 ° C), low temperature lower than normal temperature, and high temperature higher than normal temperature.
  • Vg represents the gate potential of the signal attenuating GaAsFET 240 in FIG. 2
  • Vref is the potential applied to the source bias supply terminal 234 in FIG. 2, ie, the signal attenuating GaAsFET 240.
  • This represents the source potential
  • Vth represents the threshold voltage Vth of the signal attenuating GaAsFET 240 in FIG.
  • Vg – Vref – Vth in Fig. 8 (B) is the calculation result calculated using Vg, V ref and Vth shown in Fig. 8 (A).
  • the signal attenuation GaAsFET240 begins to operate at a small Vg, and the V force decreases to V. That
  • control characteristics have a large difference depending on the temperature as shown in Fig. 9, and the linearity deteriorates.
  • FIGS. 10A and 10B are diagrams showing the variation of each voltage value with respect to the temperature of the variable attenuation circuit when the source bias circuit unit 102 as shown in FIG. 1 is used
  • FIG. FIG. 6 is a diagram showing a gain characteristic with respect to a control voltage at that time. 10 and 11, the vertical axis and The horizontal axis is the same as in Fig. 8 and Fig. 9, respectively.
  • the source bias voltage Vref is reduced as the temperature rises.
  • Vg—Vref—Vth is always constant and the temperature Regardless of the fluctuation (low temperature, normal temperature, high temperature), the same control characteristics can be drawn as shown in Fig. 11.
  • Vg is the gate voltage of the MOSFET 111 for signal attenuation.
  • the gate potential of the source bias generating MOSFET 117 of the source bias circuit unit 102 in FIG. 1 is determined by resistance division between the resistor 120 and the resistor 121.
  • the source bias generation MOSFET 117 has the characteristic that the threshold voltage increases as the temperature rises.Therefore, the threshold voltage increases as the temperature rises, while the gate potential increases. Since it is constant, the source potential decreases and the current flowing through the source bias generating MOSFET 117 decreases. As a result, the source bias potential Vref of the signal attenuating MOSFET 111 is decreased, and the threshold voltage fluctuation can be corrected.
  • a continuous control voltage from 0 V to the power supply voltage potential is input to the attenuation control terminal (Vc) 106 of the attenuation control circuit unit 101 in FIG.
  • This control voltage is divided by the attenuation control resistor 115 and the attenuation control resistor 116 and input to the gate of the signal attenuation MOSFET 111.
  • the signal attenuating MOSFET 111 is used with a drain-source bias of 0 V.
  • the attenuation of the pass characteristic from the signal input terminal 104 to the signal output terminal 105 also varies. Further, by dividing the voltage of the attenuation control terminal 106 by the attenuation control resistor 115 and the attenuation control resistor 116, an arbitrary control characteristic can be realized.
  • the capacitor 103 is inserted between the gate of the signal attenuating MOSFET 111 and the ground terminal. By inserting the capacitor 103, the signal leakage path between the drain gate and the gate source of the MOSFET 111 for signal attenuation is cut off to ensure linearity.
  • variable attenuation circuit When the variable attenuation circuit is realized with the same Si substrate as described above, for example, the impedance between the back gate of the signal attenuating MOSFET 111 and the substrate is lowered due to the low substrate resistance. Through this part, the signal leaks to the board, and the attenuation determined by the ON resistance of the MOSF ET111 for signal attenuation cannot be obtained, and linearity cannot be ensured.
  • the signal attenuation MOSFET 111 is manufactured in a triple-well structure, and a resistor 124 having a high resistance value is inserted between the back gate of the signal attenuation MOSFET 111 and the substrate. Thus, the path through which the signal leaks is blocked to ensure linearity.
  • this variable attenuation circuit has improved noise characteristics due to the addition of the capacitor 103.
  • the attenuation amount control circuit unit 101 is usually composed of a resistor. Therefore, the noise generated by this resistor enters through the gate of the signal attenuating MOSFET 111 and is applied to the high-frequency signal coming from the signal input terminal 104, deteriorating the noise characteristics, for example, GSM communication system reception band noise, etc. No longer meet the requirements.
  • the addition of the capacitor 103 reduces the noise generated in the attenuation control circuit unit 101 to the capacitor.
  • the noise characteristics can be improved in any state of the variable attenuation circuit which is cut off by the filter effect of 103 and resistor 114 and continuously changes.
  • the manufacturing process is performed. 'It is possible to correct the threshold variation of the signal attenuating MOSFET 111 due to variations in temperature fluctuations, eliminate the signal leakage in the signal attenuating MOSFET 111 in any attenuation state, and improve the linearity. Came. Furthermore, the noise generated in the attenuation control circuit unit 101 can be reduced, and the noise characteristics can be improved.
  • variable attenuation circuit compatible with the multi-band 'multi-communication system can be realized by the Si process, and it can be made into a single chip with other wireless circuit blocks.
  • the source bias circuit unit 102, the capacitor 103, and the resistor 124, or only two of them may be connected.
  • the MOSFET may be a P-channel MOSFET.
  • any structure that can achieve the same effect without using a triple-well structure is acceptable.
  • the second embodiment of the present invention is a variable attenuation circuit (integrated circuit) corresponding to the first, second, third, and fourth points of the problem. This will be described below with reference to FIG.
  • the variable attenuation circuit according to the second embodiment of the present invention shown in FIG. 3 is an attenuation circuit that attenuates a high-frequency signal input from the signal input terminal 304 and outputs the attenuated signal from the signal output terminal 305, and the attenuation amount is external.
  • a variable attenuation circuit that can be controlled by the attenuation control terminal 306, which is a terminal.
  • this variable attenuation circuit is assumed to be fabricated on, for example, a Si semiconductor substrate.
  • variable attenuation circuit is a signal attenuation MOSFET (signal attenuation) inserted between the signal path between the signal input terminal 304 and the signal output terminal 305 and the ground terminal.
  • Element) 311 a signal attenuation unit 311 that controls the ON resistance of the signal attenuation MOSFET 311, and a gate bias circuit unit 302 that applies bias to the gate of the signal attenuation MOSFET 311.
  • the signal attenuation MOSFET 311 attenuates the high-frequency signal with an attenuation amount corresponding to the attenuation amount control signal generated by the attenuation amount control circuit unit 301.
  • a capacitor 303 is added between the gate of the signal attenuation MOSFET 311 and the ground terminal. The effect of the capacitor 303 is to prevent the noise component force S generated in the gate bias circuit section 302 from entering the high-frequency signal line via the gate of the MOSFET 311 for signal attenuation.
  • the gate bias circuit section 302 of this variable attenuation circuit creates a bias by using a gate bias generation MOSFET 318 having the same threshold voltage fluctuation as the signal attenuation MOSFET 311, thereby reducing the signal attenuation. This has the effect of correcting the threshold voltage due to the manufacturing process and temperature fluctuation of the MOSFET 311 and correcting the variation of the value voltage.
  • the signal attenuating MOSFET 311 of this variable attenuating circuit has a triple wel A resistor 325 having a high resistance value is added between the back gate portion and the substrate. The effect of the resistor 325 having this high resistance value is to prevent a signal from leaking to the substrate through the back gate.
  • variable attenuation circuit the circuit connection of the variable attenuation circuit will be specifically described.
  • the signal attenuating element is preferably an N-channel MOSFET having a triple-well structure, for example.
  • the MOSFET 311 for signal attenuation is inserted between the signal path between the signal input terminal 304 and the signal output terminal 305 of the high-frequency variable attenuation circuit and the ground terminal, and the signal attenuation terminal 300 and the signal attenuation unit 300 are connected to each other. Between them, a DC blocking capacitor 312 that blocks the DC component and passes only the high frequency component is inserted, and a DC blocking capacitor 313 is also inserted between the signal attenuating unit 300 and the signal output terminal 305.
  • Reference numeral 314 indicates an impedance adjusting resistor, and reference numerals 315 and 316 indicate DC breaking capacities.
  • Reference numeral 324 denotes a source bias generating resistor. Between the back gate portion of the signal attenuating MOSFET 311 and the substrate, a resistor 325 having a high resistance value is inserted to block signal leakage!
  • an attenuation amount control circuit unit 301 is connected to the drain of the signal attenuation MOSFET 311.
  • the attenuation control circuit unit 301 is connected to a resistor 317 having a high resistance value that cuts high frequency and allows only DC to pass between the attenuation control terminal (Vc) 306 and the drain of the signal attenuation MOS FET 311! / Has a structure to speak! /
  • the gate bias circuit unit 302 connected to the gate of the signal attenuating MOSFET 311 will be described.
  • Resistor 319 and resistor 320 are connected in series, the other terminal of resistor 319 is connected to power supply voltage terminal (Vdd) 307, and the other terminal of resistor 320 is connected to the ground terminal.
  • the gate of the gate bias generating MOSFET 318 is connected to the connection between the resistor 319 and the resistor 320, and this gate bias generating MOSFET 318 has the same manufacturing process as the signal attenuating MOSFET 311 'temperature variation variation.
  • a resistor 321 is connected between the drain of the MOSFET 318 for generating the gate bias and the power supply voltage terminal (Vdd) 307, and a resistor 322 is connected between the source of the MOSFET 318 for generating the gate bias and the ground terminal.
  • a resistor 323 having a high resistance value that cuts off high frequency and allows only DC to pass is connected between the drain of the gate bias generating MOSFET 318 and the gate of the signal attenuating MOSFET 311.
  • signal attenuation A capacitor 303 is added between the gate of the MOSFET 311 and the ground terminal.
  • Fig. 3 A method for realizing highly accurate linearity regardless of process variations and temperature fluctuations in the second embodiment will be described.
  • the difference between Fig. 3 and Fig. 1 is whether the attenuation control circuit is connected to the gate or the drain.In Fig. 3, the attenuation control circuit is connected to the drain.
  • the bias circuit unit is connected to the gate.
  • FIGS. 12 (A) and 12 (B) are graphs showing changes in each voltage value with respect to the temperature of the variable attenuation circuit as shown in FIG. 3, and FIG. 13 is a gain with respect to the control voltage at that time. It is a diagram showing the characteristics.
  • Vref represents the gate potential of the signal attenuating MOSFET 311 in FIG. 3
  • Vc represents the drain potential of the signal attenuating MOSFET 311
  • Vth is the threshold voltage of the signal attenuating MOSFET 311! /
  • Vref—Vc—Vth in FIG. 12B is a calculation result calculated using Vref, Vc, and Vth shown in FIG.
  • Vref—Vc—Vth>0 the FET starts to operate, the ON resistance begins to decrease gradually, and the attenuation decreases gradually.
  • Vref is reduced as the temperature rises.
  • Vref—Vc—Vth is always constant, resulting in temperature fluctuations. Regardless, the same control characteristics can be drawn as shown in FIG.
  • the gate potential of the MOSFET 318 for generating the gate bias in the gate bias circuit section 302 in FIG. 3 is determined by resistance division between the resistor 319 and the resistor 320.
  • the MOSFET 318 for gate bias generation has the characteristic that the threshold voltage increases as the temperature rises, like the MOSFET 311 for signal attenuation. Therefore, the threshold voltage increases as the temperature rises, while the gate potential remains constant. Therefore, the source potential decreases and the current flowing through the MOS bias 318 for generating the gate bias occurs.
  • the voltage drop due to the bias resistor 321 also decreases, the drain potential of the gate bias generating MOSFET 318 increases, the gate bias potential of the signal attenuating MOSFET 311 increases, and threshold voltage fluctuation correction can be realized.
  • a continuous control voltage from 0 V to the power supply voltage potential is input to the attenuation control terminal (Vc) 306 of the attenuation control circuit unit 301 in FIG.
  • This control voltage is input to the drain potential of the MOSFET 311 for attenuation control.
  • the signal attenuating MOSFET 311 is used with a drain-source bias of 0 V.
  • the ON resistance is the largest, and as the drain potential decreases, the ON resistance gradually decreases and the drain potential force S0V minimizes ON resistance.
  • the ON resistance changes, the attenuation of the pass characteristic from the signal input terminal 304 to the signal output terminal 305 also changes.
  • the signal between the back gate of the MOSFET 111 for signal attenuation and the substrate is low due to the low substrate resistance. Leaks to the board and the attenuation determined by the ON resistance of MOSFET 311 for signal attenuation cannot be obtained, and linearity cannot be ensured.
  • the MOSFET 311 is manufactured in a triple-well structure, and a high-resistance resistor is inserted between the back gate of the MOSFET 311 and the substrate to block the signal leakage path. And the linearity is ensured.
  • this variable attenuation circuit has improved noise characteristics by adding a capacitor 303.
  • the gate bias circuit section 302 that performs value voltage compensation is generally composed of a resistor and a transistor. Therefore, noise generated by these resistors and transistors enters through the gate of the MOSFET 311 for signal attenuation, and is applied to the high-frequency signal that enters from the signal input terminal 304, deteriorating the noise characteristics. For example, the reception band of the GSM communication system The noise and other requirements are not met.
  • the noise generated in the gate bias circuit 302 can be cut off by the filter effect of the capacitor and the resistance, and the noise characteristics can be improved in any state of the continuously changing variable attenuation circuit.
  • the manufacturing process 'It is possible to correct the threshold variation of the signal attenuation MOSFET 311 due to variations in temperature, and to eliminate signal leakage in the signal attenuation MOSFET 311 in any attenuation state, improving the linearity. did it.
  • noise generated in the gate bias circuit section 302 that performs threshold voltage compensation can be reduced, and noise characteristics can be improved.
  • a variable attenuation circuit compatible with multi-band and multi-communication systems can be realized with the Si process, making it possible to make a single chip with other wireless circuit blocks.
  • the MOSFET may be a P-channel MOSFET. In addition, even if it is not a triple wel structure, it is sufficient if the same effect can be exhibited.
  • Example 3 of the present invention is a variable attenuation circuit (integrated circuit) corresponding to the first, second, third, fourth, and fifth points of the problem. This will be described below with reference to FIG.
  • the variable attenuation circuit according to the third embodiment of the present invention shown in FIG. 4 is an attenuation circuit that attenuates a high-frequency signal input from the signal input terminal 404 and outputs it from the signal output terminal 405, and the attenuation amount is external.
  • a variable attenuation circuit that can be controlled from an attenuation control terminal 406, which is a terminal, is assumed.
  • this variable attenuation circuit is assumed to be fabricated on, for example, a Si semiconductor substrate.
  • variable attenuation circuit in the present invention has a signal attenuation MOSFET (signal attenuation element) 411 inserted in series between the signal input terminal 404 and the signal output terminal 405. It has an attenuation unit 400, an attenuation amount control circuit unit 401 that controls the ON resistance of the signal attenuation MOSFET 411, and a source bias circuit unit 402 that applies a bias to the source of the signal attenuation MOSFET 411.
  • the high frequency signal is attenuated by an attenuation amount corresponding to the attenuation amount control signal generated by the amount control circuit unit 401.
  • a capacitor 403 is added between the gate of the signal attenuation MOSFET 411 and the ground terminal.
  • the effect of this capacity 403 can be broadly divided into two points.
  • First point Attenuation control circuit block Noise component force S generated in 401, prevention of mixing into high frequency signal line (line from signal input terminal 404 to signal output terminal 405) via gate of MOSFET 411 for signal attenuation It is.
  • Second-point force S high-attenuation state due to parasitic capacitance generated between drain gate and gate source of MOSFET411 for signal attenuation This is to prevent a high frequency signal from leaking between the signal input terminal 404 and the signal output terminal 405.
  • the source bias circuit section 402 of this variable attenuating circuit creates a bias voltage by using the source bias generating MOSFET 417 having the same threshold voltage fluctuation / temperature characteristics as the signal attenuating MOSFET 411! As a result, the manufacturing process of the signal attenuating MOSFET 411 has an effect of correcting variations in threshold voltage due to temperature fluctuations.
  • the signal attenuating MOSFET 411 of the variable attenuating circuit has a triple well structure, and a resistor 424 having a high resistance value is additionally provided between the back gate portion and the substrate.
  • the effect of the resistor 424 having the high resistance value is to prevent a signal from leaking to the substrate through the back gate.
  • This variable attenuation circuit includes a capacitor 425 and a switch 426 between the connection between the resistor 422 for supplying the source bias to the MOSFET 411 for signal attenuation and the resistor 423 for supplying the drain bias and the ground terminal. Naoki IJ circuit power S has been added.
  • the effect of the capacitor 425 and the switch 426 is that a high-frequency signal is supplied in the signal input terminal 404 in a high attenuation state via a resistor inserted between the drain and source of the signal attenuation MOSFET 411 to supply the source bias and the drain bias. Is to prevent leakage to the signal output terminal 405. In other words, signal leakage is prevented by dividing the resistor and grounding at high frequency. Insert a switch to eliminate the signal leakage in the low attenuation state where the signal passes, so that the capacity is not visible in the low attenuation state.
  • the switch 426 is an analog switch, mainly a MOSFET.
  • control circuit for the switch (MOSFET) 426 for example, the gate potential of the MOSFET is fixed and the source / drain terminal of the MOSFET is connected to the attenuation control terminal 406 through a resistor as described above. Performs continuous on / off operation.
  • MOSFET switch
  • the gate potential of the MOSFET is fixed and the source / drain terminal of the MOSFET is connected to the attenuation control terminal 406 through a resistor as described above. Performs continuous on / off operation.
  • the circuit connection of the variable attenuation circuit will be specifically described below.
  • a signal attenuating element for example, an N-channel MOS FET having a triple-well structure is suitable.
  • the signal attenuating MOSFET 411 is inserted in series in the signal path between the signal input terminal 404 and the signal output terminal 405 of the high-frequency variable attenuating circuit, and between the signal input terminal 404 and the signal attenuating MOSFET 411.
  • the DC blocking capacitor 412 that blocks the DC component and passes only the high frequency component is inserted, and the DC blocking capacitor 413 is also inserted between the signal attenuation MOSFET 411 and the signal output terminal 405. Yes.
  • a resistor 424 having a high resistance value for blocking signal leakage is inserted! /.
  • an attenuation control circuit unit 401 is connected to the gate of the signal attenuation MOSFET 411.
  • the configuration of the attenuation control circuit unit 401 will be described.
  • Attenuation control resistor 415 and attenuation control resistor 416 are connected in series, and the other terminal of attenuation control resistor 415 is connected to attenuation control terminal (Vc) 406 for attenuation control.
  • the other terminal of resistor 416 is connected to the ground terminal.
  • a resistor 414 having a high resistance value that blocks high frequency and allows only DC to pass.
  • a capacitor 403 is added between the gate of the signal attenuation MOSFET 411 and the ground terminal.
  • the source bias circuit portion 402 connected to the source terminal of the signal attenuating MOSFET 411 will be described.
  • the resistor 420 and the resistor 421 are connected in series, the other terminal of the resistor 420 is connected to the power supply voltage terminal (Vdd) 407, and the other terminal of the resistor 421 is connected to the ground terminal.
  • the gate of the source bias generating MOSFET 417 is connected to the connection portion between the resistor 420 and the resistor 421, and this source bias generating MOSFET 417 has the same manufacturing process as the signal attenuating MOSFET 411, “temperature variation variation.
  • a resistor 418 is connected between the drain of the source bias generating MOSFET 417 and the power supply voltage terminal 407, and a resistor 419 is connected between the source of the source bias generating MOSFET 417 and the ground terminal.
  • a resistor 422 having a high resistance value that cuts off the high frequency and passes only DC is connected between the source of the source bias generating MOSFET 417 and the source of the signal attenuating MOSFET 411.
  • a resistor 423 having a resistance value is connected between the source of the signal and the drain of the MOSFET 411 for signal attenuation.
  • a series circuit of a capacitor 425 and a switch 426 is added between the connection between the resistor 422 that supplies the source bias to the MOSFE T411 for signal attenuation and the resistor 423 that supplies the drain bias and the ground terminal.
  • Fig. 10 is a diagram showing the variation of each voltage value with respect to the temperature of the variable attenuation circuit when the source bias circuit unit 402 as shown in Fig. 1 is used, and Fig. 11 shows the control voltage at that time.
  • FIG. 6 is a diagram showing gain characteristics for the same.
  • Vref is reduced as the temperature rises.
  • Vg—Vref—Vth is always constant regardless of temperature fluctuations, whether the temperature increases and the threshold voltage Vth increases or the temperature decreases and the threshold voltage Vth decreases.
  • the same control characteristics can be drawn.
  • the circuit operation for realizing the variation correction as shown in Fig. 11 will be described using the variable attenuation circuit of Fig. 4 as V.
  • the gate potential of the source bias generating MOSFET 417 in the source bias circuit section 402 in FIG. 4 is determined by resistance division between the resistor 420 and the resistor 421. Since the source bias generation MOSFET 417 has the characteristic that the threshold voltage increases as the temperature rises the same as the signal attenuation MOSFET 411, the threshold voltage increases as the temperature rises, while the gate potential increases. Since it is constant, the source potential decreases and the current flowing through the source bias generating MOSFET 417 decreases. As a result, the source bias potential of the signal attenuating MOSFET 411 is reduced, and correction of the threshold voltage fluctuation can be realized.
  • a continuous control voltage from 0 V to the power supply voltage potential is input to the attenuation control terminal (Vc) 406 of the attenuation control circuit unit 401 in FIG.
  • This control voltage is divided by the attenuation control resistor 415 and the attenuation control resistor 416 and input to the gate of the signal attenuation MOSFET 411.
  • the signal attenuating MOSFET 411 is used with a drain-source bias of 0 V.
  • the ON resistance is the largest and the ON resistance gradually decreases as the gate potential increases.
  • the ON resistance is minimized.
  • any voltage can be controlled by dividing with resistors 415 and 416. Characteristics are feasible.
  • the impedance between the back gate of the signal attenuation MOSFET 411 and the substrate is lowered due to the low substrate resistance.
  • the signal leaks to the board, and the attenuation determined by the ON resistance of the signal attenuation MOSF ET411 cannot be obtained, and linearity cannot be ensured.
  • the signal attenuating MOSFET 411 is manufactured in a triple-well structure, and a resistor having a high resistance value is inserted between the back gate of the signal attenuating MOSFET 411 and the substrate. The path through which the signal leaks is blocked to ensure linearity.
  • the voltage generated by the source bias circuit 402 is supplied to the source via the source bias generating resistor 422 having a high resistance value, and is supplied to the drain via the drain bias generating resistor 423 having a high resistance value.
  • the method is generally used. In this case, in a high attenuation state, a signal leaks from the drain to the source via the resistor, and there is a problem that the attenuation amount cannot be as high as the attenuation characteristic when the MOSFE T411 for signal attenuation is cut off.
  • a series circuit of a capacitor 425 and a switch 426 is connected between the connection between the source bias generating resistor 422 and the drain bias generating resistor 423 of the signal attenuating MOSFET 411 and the ground terminal.
  • the switch 426 In the high isolation state, when the switch 426 is turned on, a signal leaks from the input terminal 404 to the output terminal 405 via the source bias generating resistor 422 and the drain bias generating resistor 423. It can cut off and improve the attenuation characteristics at the time of high isolation.
  • switch 426 In the passing state, switch 426 is set to OFF. This prevents the signal from leaking when passing due to the influence of the capacity 425.
  • FIG. 14A shows the results (attenuation control characteristics) of circuit simulation using the variable attenuation circuit of FIGS. 4 and 2.
  • symbol E1 indicates the characteristics of the conventional circuit (Fig. 2)
  • symbol E2 indicates the characteristics of the circuit of the present invention (Fig. 4).
  • Vc l.8V
  • the capacitor 403 added to the gate of the signal attenuating MOSFET 411, the resistor 424 added to the back gate of the signal attenuating MOSFET 411, and the source bias circuit 402 are added.
  • a series circuit consisting of a capacitance 425 and a switch 426 an attenuation close to the original performance of the signal attenuation MOSFET 411 was obtained, and the attenuation control characteristics were greatly improved.
  • variable attenuation circuit has improved noise characteristics due to the addition of the capacitor 403.
  • the attenuation amount control circuit unit 401 is usually composed of a resistor. Therefore, noise generated by this resistor enters through the gate of the MOSFET 411 for signal attenuation and is applied to the high-frequency signal that enters from the signal input terminal 404 to deteriorate the noise characteristics, for example, GSM communication system reception band noise, etc. No longer meet the requirements.
  • the noise generated in the attenuation control circuit unit 401 is reduced by adding the capacitor 403.
  • Fig. 14B shows the results (noise characteristics) of a circuit simulation using the variable attenuation circuit of Figs. 4 and 2.
  • symbol F1 indicates the characteristics of the conventional circuit (Fig. 2)
  • symbol F2 indicates the characteristics of the circuit of the present invention (Fig. 4).
  • Example 3 the addition of the capacitor 403 greatly improved the noise characteristics.
  • the variable bias circuit having the signal attenuating MOSFET 411 includes the source bias circuit 402, the capacitor 403, the resistor 424 added to the back gate, the capacitor 425 added to the source bias circuit, and the switch 426.
  • the source bias circuit 402 the capacitor 403, the resistor 424 added to the back gate
  • the capacitor 425 added to the source bias circuit
  • the switch 426 By adding a series circuit, it becomes possible to compensate for variations in the threshold value of the MOSFET 411 for signal attenuation due to variations in temperature variations, and the signal attenuation MOSFET 411 and other resistors can be compensated for in any attenuation state. Signal leakage could be eliminated and linearity could be improved.
  • the noise generated by the attenuation control circuit unit 401 can be reduced, and the noise characteristics can be improved.
  • a variable attenuation circuit compatible with multi-band and multi-communication systems can be realized by the Si process, and it can be integrated into a single chip with other radio circuit blocks.
  • the MOSFET may be a P-channel MOSFET. Moreover, it is sufficient that the same effect can be exhibited even if the triple-well structure is not used.
  • the source bias circuit additional capacitor 425 and the switch 425 in series may be provided with only the source bias circuit additional capacitor 425.
  • variable attenuation circuit integrated circuit
  • FIG. 6 shows a variable attenuation circuit using at least one of the variable attenuation circuit of FIG. 1, the variable attenuation circuit of FIG. 3, or the variable attenuation circuit of FIG.
  • the circuit configuration and operating principle will be described.
  • variable attenuation circuit using GaAs or the like is often fabricated independently on a substrate. In that case, both input and output must be terminated at 50 ⁇ at high frequencies.
  • reference numerals 1601 to 1604 denote variable resistors (variable attenuation circuits), respectively.
  • Vc is the attenuation control terminal, Vref;! To Vref4 is the bias terminal, IN is the input terminal, and OUT is the output terminal.
  • the variable resistance part inserted in parallel (shunt) is terminated at 50 ⁇ for both input and output from the high attenuation state to the low attenuation state.
  • both input and output need not be terminated at 50 ⁇ .
  • the input side is a digital circuit such as an inverter
  • the input impedance of the variable attenuation circuit is low.
  • the input impedance of the variable attenuation circuit is lowered, and a large driving force is required for the preceding circuit. In such a case, as shown in Figure 5.
  • a ladder-type variable attenuation circuit is desirable.
  • 501 and 502 are variable attenuation circuits as shown in FIG. 1 or FIG. 4
  • 503 and 504 are variable attenuation circuits as shown in FIG. 3
  • 505 is a signal input terminal
  • 506 is a signal output terminal
  • 507 Is an attenuation control terminal.
  • FIG. 6 shows a variable attenuation circuit using the variable attenuation circuit of FIGS. 4 and 3 in the circuit configuration of FIG.
  • the high-frequency signal that has entered from the signal input terminal 601 is attenuated by the attenuation operation units 611, 612, 613, and 614 and is output from the signal output terminal 602.
  • the attenuation operation units 611, 612, 613, and 614 are a combination of the signal attenuation unit and the attenuation amount control circuit unit in FIG. 4 or FIG.
  • a common source bias generation circuit 615 shown in FIG. 4 is added as a threshold voltage variation correction circuit for the MOSFET for signal attenuation of the attenuation operation unit 611 and the attenuation operation unit 613.
  • the gate bias generation circuit 616 shown in Fig. 3 was added as a correction circuit for the threshold voltage variation of the 612 signal attenuating MO SFET, and the variation of the threshold voltage of the signal attenuating MOSFET in the attenuation unit 614 was corrected.
  • Attenuation operation unit 611 and attenuation operation unit 613 signals A series circuit of a capacitor and a switch is inserted between the connection between the source bias generation resistor and drain bias generation resistor of the attenuation MOSFET and the ground terminal. Yes.
  • FIG. 15A and 15B are circuit simulations using the variable attenuation circuit of FIG. It is the result of having gone.
  • Fig. 15A shows the attenuation control characteristic
  • Fig. 15B shows the noise characteristic.
  • symbol G1 indicates the characteristics of the conventional circuit (for example, the circuit of FIG. 2)
  • symbol G2 indicates the characteristics of the circuit of the present invention (FIG. 4)
  • symbol HI indicates the characteristics of the conventional circuit (for example, the circuit of FIG. 2)
  • symbol H2 indicates the characteristics of the circuit of the present invention (FIG. 6).
  • At least one of the capacitances added between the gate of each signal attenuation MOSFET and the ground terminal, or a high between the back gate and the substrate. It is added to at least one of the resistors having the resistance value, at least one of the threshold voltage variation correction circuits of the signal attenuation MOSFET, or the source bias generating resistor and the drain bias generating resistor. As long as at least one of the capacities is added, all need not be connected. In addition, the connection of the parallel (shunt) signal attenuator and the series (series) signal attenuator does not have to be in this order, and any number of stages may be used.
  • the MOSFET may be a P-channel MOSFET. Moreover, it is sufficient that the same effect can be exhibited even if the triple-luel structure is not used.
  • FIG. 7 is a block diagram showing an example of a high-frequency radio transmission circuit system (apparatus) using the variable attenuation circuit of FIG. 1, FIG. 3, FIG. 4, or FIG. The circuit configuration and operating principle will be described.
  • this high-frequency wireless transmission circuit system divides the oscillation signal of an oscillator (VCO) 701 by a divider 702, and a buffer (Buffer) composed of an inverter or the like. ) After passing through 703, the gain is controlled by variable attenuation circuit (Variable Attenuator) 704 The signal is attenuated, amplified by a driver amplifier (Driver) 705, further amplified by a high frequency amplifier (PA) 706, and transmitted from an antenna 707.
  • VCO oscillator
  • Buffer buffer
  • Variable Attenuator variable attenuation circuit
  • variable attenuation circuit 704 of the high-frequency wireless transmission circuit system in FIG. 7 By applying the present invention to the variable attenuation circuit 704 of the high-frequency wireless transmission circuit system in FIG. 7, even when the variable attenuation circuit is constructed on the same Si semiconductor substrate as other circuit blocks, the variation characteristics A variable attenuation circuit with excellent linearity, isolation characteristics, and noise characteristics can be realized, and a system with good pass characteristics can be obtained.
  • the configuration example of the high-frequency wireless transmission circuit system is not limited to the above, and a wireless transmission device and a wireless transmission device each including at least one variable attenuation circuit, at least one oscillator, and at least one amplifier. Any wireless transmission circuit system having an antenna connected to and capable of transmitting and receiving at least one radio frequency may be used.
  • the present invention is useful for attenuation of high-frequency signals in various wireless communication devices.

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Abstract

L'invention concerne un circuit à atténuation variable, qui a des caractéristiques de commande d'atténuation linéaire et d'excellentes caractéristiques de bruit, et de résistance à l'encontre d'une variance sur un substrat Si. Le circuit à atténuation variable est doté d'une section (400) d'atténuation de signal ayant un MOSFET (411) à atténuation variable en série avec une ligne de signal qui connecte une borne (404) d'entrée de signal avec une borne (405) de sortie de signal; une section (401) de circuit de commande de quantité d'atténuation pour commander le potentiel de grille du MOSFET (411) à atténuation variable; et une section (402) de circuit de polarisation de source pour polariser le MOSFET (411) à atténuation variable. La section (402) de circuit de polarisation de source a un MOSFET (417), et le potentiel de source du MOSFET (417) est appliqué au potentiel de source du MOSFET (411) à atténuation variable. De plus, une résistance (424) est ajoutée entre la grille arrière et le substrat du MOSFET (411) à atténuation variable, un condensateur (403) est ajouté entre une grille et une borne de terre, et un circuit connectant le condensateur (425) et un commutateur (426) en série est ajouté entre la section (402) de circuit de polarisation de source et la borne de terre.
PCT/JP2007/068152 2006-09-20 2007-09-19 Circuit à atténuation variable WO2008035698A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006-254515 2006-09-20
JP2006254515A JP2008078898A (ja) 2006-09-20 2006-09-20 可変減衰回路

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WO2008035698A1 true WO2008035698A1 (fr) 2008-03-27

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5129092B2 (ja) * 2008-11-13 2013-01-23 旭化成エレクトロニクス株式会社 電圧制御発振器

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08130422A (ja) * 1994-06-24 1996-05-21 Sgs Thomson Microelettronica Spa 最大電圧スイングを有する交換演算増幅器を使用する低電圧交換キャパシタンス回路
JPH10261925A (ja) * 1997-03-17 1998-09-29 Toshiba Corp 高周波増幅器
JP2002368562A (ja) * 2001-06-06 2002-12-20 Matsushita Electric Ind Co Ltd 減衰器
JP2003046278A (ja) * 2001-05-24 2003-02-14 Matsushita Electric Ind Co Ltd 携帯用電力増幅器
JP2004207437A (ja) * 2002-12-25 2004-07-22 Nec Corp 接地スイッチ回路
JP2005027062A (ja) * 2003-07-03 2005-01-27 Matsushita Electric Ind Co Ltd 高周波増幅回路およびそれを用いた移動体通信端末
JP2006191277A (ja) * 2005-01-05 2006-07-20 Mitsubishi Electric Corp パルス変調回路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08130422A (ja) * 1994-06-24 1996-05-21 Sgs Thomson Microelettronica Spa 最大電圧スイングを有する交換演算増幅器を使用する低電圧交換キャパシタンス回路
JPH10261925A (ja) * 1997-03-17 1998-09-29 Toshiba Corp 高周波増幅器
JP2003046278A (ja) * 2001-05-24 2003-02-14 Matsushita Electric Ind Co Ltd 携帯用電力増幅器
JP2002368562A (ja) * 2001-06-06 2002-12-20 Matsushita Electric Ind Co Ltd 減衰器
JP2004207437A (ja) * 2002-12-25 2004-07-22 Nec Corp 接地スイッチ回路
JP2005027062A (ja) * 2003-07-03 2005-01-27 Matsushita Electric Ind Co Ltd 高周波増幅回路およびそれを用いた移動体通信端末
JP2006191277A (ja) * 2005-01-05 2006-07-20 Mitsubishi Electric Corp パルス変調回路

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