WO2008035698A1

WO2008035698A1 - Variable attenuation circuit

Info

Publication number: WO2008035698A1
Application number: PCT/JP2007/068152
Authority: WO
Inventors: Takahito Miyazaki
Original assignee: Panasonic Corporation
Priority date: 2006-09-20
Filing date: 2007-09-19
Publication date: 2008-03-27
Also published as: JP2008078898A

Abstract

Provided is a variable attenuation circuit, which has linear attenuation control characteristics and excellent noise characteristics and is strong against variance on a Si substrate. The variable attenuation circuit is provided with a signal attenuation section (400) having a variable attenuation MOSFET (411) in series with a signal line which connects a signal input terminal (404) with a signal output terminal (405); an attenuation quantity control circuit section (401) for controlling the gate potential of the variable attenuation MOSFET (411); and a source bias circuit section (402) for biasing the variable attenuation MOSFET (411). The source bias circuit section (402) has a MOSFET (417), and the source potential of the MOSFET (417) is applied to the source potential of the variable attenuation MOSFET (411). Furthermore, a resistor (424) is added between the back gate and the substrate of the variable attenuation MOSFET (411), a capacitor (403) is added between a gate and a grounding terminal, and a circuit connecting the capacitor (425) and a switch (426) in series is added between the source bias circuit section (402) and the grounding terminal.

Description

Specification

Variable attenuation circuit

Technical field

[0001] The present invention relates to a variable attenuation circuit and a high-frequency wireless circuit system using the same. In particular, the variable attenuation circuit of the present invention is used for attenuation of high-frequency signals in various wireless communication devices. It realizes linear attenuation control characteristics, improves noise characteristics, and electrical characteristics of elements depending on the manufacturing process and temperature. This is intended to compensate for variations in the quality.

Background art

In recent years, semiconductor integrated circuits using field effect transistors have been developed for high-frequency circuits in the communication field. One of these semiconductor integrated circuit blocks is an attenuation circuit that requires attenuation control, that is, gain control.

FIG. 2 is a circuit diagram showing a configuration of a conventional variable attenuation circuit using a GaAsFET (see JP 2005-27062 A). As shown in FIG. 2, the conventional variable attenuating circuit is attenuated by a signal attenuating unit 260 including a signal attenuating GaAs FET 240 in which a high frequency signal inputted from a signal input terminal (IN) 231 is inserted in series. Output from the signal output terminal (OUT) 232. The high frequency signal input from the signal input terminal 231 includes a signal attenuation GaAsFET 245 inserted between the signal input terminal 231 and the ground terminal (GND) 236. The signal attenuation unit 261, the signal output terminal 232, and the ground terminal The signal is attenuated by a signal attenuating unit 262 including a signal attenuating GaAsFET 251 inserted between the signal output terminal 232 and the signal attenuating unit 237.

At this time, the attenuation amount of the signal attenuation GaAsFETs 240, 245, and 251 can be controlled by the attenuation amount control signal input from the attenuation amount control terminal (Vc) 233. A resistor 255 for supplying a gate bias is provided between the attenuation control terminal 233 and the gate of the GaAsFET 240 for signal attenuation, and a resistor 222 for supplying a drain bias is provided between the attenuation control terminal 233 and the source of the GaAsFET 245 for signal attenuation 259. However, a drain bias supply resistor 256 is provided between the attenuation control terminal 233 and the source of the signal attenuation GaAsFET 251. [0005] In addition, a source bias supply resistor 239 is provided between the source bias supply terminal (Vref 1) 234 of the signal attenuation GaAsFET 240 and the source of the signal attenuation GaAsFET 240, and the gate bias of the signal attenuation GaAsFETs 245 and 251. Gate bias supply resistors 257 and 258 are provided between the supply terminal (Vref2) 235 and the gates of the signal attenuation Ga AsFETs 245 and 251, respectively.

[0006] In order to reduce the frequency dependence of the pass characteristic of the signal attenuation GaAsFET at the time of high attenuation, a drain bias supply resistor 241 is provided between the source and drain of the signal attenuation GaAsFET 240, 245, 251 respectively. A source potential supply resistor 246 and a source potential supply resistor 252 are provided.

Reference numerals 238, 242, 243, 248, 249, and 254 denote DC blocking capacities, and reference numerals 244, 247, 250, and 253 denote input / output matching resistors, respectively.

[0008] This variable attenuation circuit uses the attenuation control signal supplied from the attenuation control terminal 233, the signal attenuation GaAsFET 240 inserted in series, the signal attenuation GaAsFET 245 inserted in the shunt, By connecting to the 251 source terminal, it is possible to control three attenuation GaAsFETs 240, 245, 251 with one type of attenuation control signal.

[0009] In addition, as a state of the variable attenuation circuit, a low impedance state and a high impedance state

In addition to two states, it is possible to continuously change the impedance state from a low impedance state to a high impedance state. In general, a variable attenuation circuit has a signal attenuation GaAsFET 240 that is controlled by continuously changing the voltage at the attenuation control terminal 233, the force that requires linearity of its control characteristics from a high attenuation state to a low attenuation state. Low resistance, GaAsFET 245 and 251 for signal attenuation can be controlled to the desired attenuation from low attenuation state with high resistance to GaAsFET 240 for signal attenuation and high resistance to GaAsFET 245 and 251 for signal attenuation with low resistance. Realize linear control characteristics! Patent Document 1: Japanese Patent Laid-Open No. 2005-27062

Disclosure of the invention

Problems to be solved by the invention

[0010] However, in recent years, the scale of wireless circuit systems has been increasing. The high-frequency variable attenuation circuit configured on a single substrate such as a GaAs substrate has also been fabricated on the same Si semiconductor substrate as other semiconductor circuits such as oscillators and mixers. As a result, it has become necessary to fabricate a high-frequency variable attenuation circuit on a Si substrate that has a lower substrate resistance than GaAs processes.

[0011] In addition, with recent miniaturization and multi-functionalization of wireless circuit systems, the UMTS (Universal Mobile Telecommunication System) communication system with a wide output variable range and GSM (Global System for Mobile Communications), which requires strict noise characteristics, are required. ) It has become necessary to produce a wireless circuit that supports a multi-communication system.

[0012] There are the following five problems when a variable attenuation circuit corresponding to the wireless circuit system as described above is manufactured by a Si semiconductor process.

[0013] First, when a high-frequency circuit is manufactured using a Si semiconductor substrate, signal leakage due to the influence of parasitic capacitance is a problem. Also in the variable attenuation circuit, in the high attenuation state, the signal leaks from the drain to the source side through the parasitic capacitance generated between the drain and gate of the MOSFET for signal attenuation and between the gate and source, and the isolation in the high attenuation state Deteriorate the characteristics and deteriorate the damping control characteristics!

[0014] The second problem is that noise characteristics deteriorate due to noise generated in the control circuit mixed into the high-frequency circuit. Regarding the variable attenuation circuit, the noise generated in the control circuit is mixed into the high-frequency signal line via the gate of the signal attenuation MOSFET, and the recent severe resolution characteristics corresponding to the multi-communication system are not satisfied! Power S can be raised.

[0015] Third, in the case of manufacturing with a Si semiconductor substrate, there is a problem of signal leakage due to the low substrate resistance component. With regard to the variable attenuation circuit, in the high attenuation state, the signal leaks to the substrate through the back gate of the signal attenuation MOSFET, which deteriorates the attenuation control characteristics.

[0016] The fourth point is the influence of variations due to manufacturing processes and temperature fluctuations. As for variable attenuation circuits, more stringent linearity is required, and there is a problem that the desired linearity is not satisfied with respect to attenuation control characteristics due to variations in threshold voltage of MOSFET for signal attenuation due to manufacturing process and temperature fluctuation. is there.

[0017] The fifth point is that when a high-frequency circuit is fabricated on a Si semiconductor substrate, the signal of Leakage is a problem. As for the variable attenuation circuit, it is necessary to add a resistor between the source and the drain in order to supply the source bias and drain bias and to improve the frequency characteristics. There is a problem if the attenuation control characteristics deteriorate!

[0018] Accordingly, an object of the present invention is to provide a variable attenuation circuit that has linear attenuation control characteristics and excellent noise characteristics, and is resistant to variations in MOSFET thresholds due to the manufacturing process and temperature, and a high-frequency radio circuit system using the same Is to provide.

Means for solving the problem

[0019] A variable attenuation circuit according to a first aspect of the present invention is a variable attenuation circuit in which the first, second, third, and fourth points of the above-mentioned problem have been solved. The variable attenuation circuit includes a signal attenuating unit having a signal attenuating element inserted in series in a signal path between the signal input unit and the signal output unit, an attenuation control circuit unit for controlling the signal attenuating element, And a bias circuit section that provides a bias that compensates for variations in the manufacturing process of the signal attenuating element and temperature variation, and has a capacitance between the connection between the signal attenuating element and the attenuation control circuit and the ground terminal. The signal attenuating element has a configuration for attenuating the high-frequency signal with an attenuation amount corresponding to the attenuation amount control signal generated by the attenuation amount control circuit unit.

[0020] In the above configuration, the signal attenuating element is generally preferably an FET, particularly a MOSFET. The attenuation control circuit section for controlling the signal attenuating element is connected to the gate terminal of the signal attenuating FET that is the signal attenuating element. The noise circuit section is made up of FETs that have the same manufacturing process as the signal attenuating FETs, with variations in temperature fluctuations, and the source terminals and drains of the signal attenuating FETs are connected via source bias resistors and drain bias resistors. Connected to the terminal. Capacitance is inserted between the gate terminal and ground terminal of the signal attenuation FET. The signal attenuating FET well has a triple well structure, and a resistor having a high resistance value is inserted between the back gate and the substrate.

[0021] According to this configuration, since the capacitance is provided between the gate terminal and the ground terminal of the signal attenuation FET, the capacitance between the drain and the gate of the signal attenuation FET and the capacitance between the gate and the source are increased. Therefore, it is possible to block the signal leakage path and improve the attenuation characteristics during high isolation. In addition, by adopting the same configuration, the attenuation control circuit unit composed of resistors, etc. Noise generated can be prevented from entering the high-frequency signal line via the gate of the signal attenuation FET, and noise characteristics can be improved. As a result, the first and second issues can be solved.

[0022] In addition, the signal attenuating FET has a triple-well structure, and a high resistance is inserted between the back gate and the substrate, so that the back gate of the signal attenuating FET is Thus, the path through which the signal leaks to the substrate can be blocked, and the attenuation control characteristic can be improved. As a result, the third problem can be solved.

[0023] Furthermore, the same manufacturing process as the signal attenuating FET 'For signal attenuating by applying a source bias to the signal attenuating FET in the bias circuit configured using FET that has a threshold variation of temperature fluctuation The FET threshold manufacturing process and temperature variations can be corrected. As a result, the fourth problem can be solved. In this case, the bias value generated by the (source) bias circuit section decreases when the threshold voltage of the signal attenuation FET increases due to the manufacturing process' temperature fluctuation, and conversely the threshold voltage of the signal attenuation FET. It is preferably controlled so that it increases when the value decreases.

[0024] By combining the above four points of improvement effects, signal and noise leakage paths can be blocked, and threshold values can be stabilized, making it possible to take advantage of the original performance of the transistor. It becomes. As a result, a linear attenuation control characteristic can be realized in any attenuation state that changes continuously, and a variable attenuation circuit that has excellent noise characteristics and is resistant to variations can be realized.

[0025] A variable attenuation circuit according to a second aspect of the present invention is a variable attenuation circuit that solves the second, third, and fourth points of the above problems. The variable attenuation circuit includes a signal attenuation unit having a signal attenuation element inserted into a ground terminal from a signal path between a signal input unit and a signal output unit, and an attenuation amount control circuit for controlling the signal attenuation element. And a bias circuit section that provides a bias that compensates for the manufacturing process and temperature variation of the signal attenuating element, and a capacitance is provided between the connection between the signal attenuating element and the attenuation control circuit section and the ground terminal. The signal attenuating element has a configuration for attenuating the high-frequency signal with an attenuation amount corresponding to the attenuation amount control signal generated by the attenuation amount control circuit unit.

In the above configuration, the signal attenuating element is generally preferably an FET. Signal attenuation element The attenuation control circuit unit for controlling the signal is connected to the source terminal of the signal attenuating FET which is a signal attenuating element. The noise circuit section is configured using a FET that has the same manufacturing process as the signal attenuating FET and temperature variation variation, and is connected to the gate terminal of the signal attenuating FET. The capacitor is inserted between the gate terminal and the ground terminal of the signal attenuation FET. In addition, the signal attenuating FET has a triple-well structure, and a high resistance is inserted between the back gate and the substrate.

[0027] According to this configuration, since the capacitance is provided between the gate terminal and the ground terminal of the signal attenuating FET, noise generated in the gate bias circuit unit configured by a resistor or the like passes through the gate. It is possible to prevent mixing in the high frequency signal line and improve noise characteristics. As a result, the second problem can be solved.

[0028] In addition, the signal attenuating FET has a triple-well structure, and a resistor having a high resistance is inserted between the back gate and the substrate. Thus, the path through which the signal leaks to the substrate can be blocked, and the attenuation control characteristic can be improved. As a result, the third problem can be solved.

[0029] Furthermore, the same manufacturing process as the signal attenuating FET 'For signal attenuating by applying a gate bias to the signal attenuating FET in the bias circuit configured using FET with a threshold variation of temperature fluctuation The FET threshold manufacturing process and temperature variations can be corrected. As a result, the fourth problem can be solved. In this case, the bias value generated in the (gate) bias circuit section increases when the threshold voltage of the signal attenuation FET increases due to temperature fluctuations in the manufacturing process, and conversely the threshold voltage of the signal attenuation FET. It is preferable to control to decrease when the value decreases.

[0030] By combining the above three improvement effects, signal and noise leakage paths can be blocked, and threshold values can be stabilized, making it possible to take advantage of the original performance of the transistor. It becomes. As a result, a linear attenuation control characteristic can be realized in any attenuation state that changes continuously, and a variable attenuation circuit that has excellent noise characteristics and is resistant to variations can be realized.

[0031] A variable attenuation circuit according to a third aspect of the present invention is a variable attenuation circuit that solves the first, second, third, fourth, and fifth points of the above-described problem. This variable attenuation circuit has signal input and signal output A signal attenuating unit having a signal attenuating element inserted in series in the signal path between the signal attenuating unit, an attenuation control circuit unit for controlling the signal attenuating element, and correcting the manufacturing process and temperature variation of the signal attenuating element A bias circuit section for applying a bias, a capacitance between a connection section between the signal attenuation element and the attenuation control circuit and the ground terminal, and a signal attenuation element and a noise circuit section. The signal attenuating element attenuates the high-frequency signal with an attenuation corresponding to the attenuation control signal generated by the attenuation control circuit. Have the configuration to do! /

In the above configuration, the signal attenuating element is generally preferably an FET. The attenuation control circuit that controls the signal attenuating element is connected to the gate terminal of the signal attenuating FET that is the signal attenuating element, and the bias circuit is the same manufacturing process as the signal attenuating FET. It is configured using a FET that has a signal bias, and is connected to the source and drain terminals of the signal attenuating FET via a source bias resistor and drain bias resistor. The capacitance added to the connection between the signal attenuating element and the attenuation control circuit is inserted between the gate terminal of the signal attenuating FET and the ground terminal, and the connection between the signal attenuating element and the bias circuit section The capacitance added to the block is inserted between the connection between the source bias resistor and drain bias resistor of the signal attenuating FET and the ground terminal. The signal attenuating FET has a triple-well structure, and a resistor having a high resistance value is inserted between the back gate and the substrate.

[0033] According to this configuration, the capacitance between the gate terminal and the ground terminal of the signal attenuating FET increases the capacitance between the drain and the gate of the signal attenuating FET and the capacitance between the gate and the source. Therefore, it is possible to block the signal leakage path and improve the attenuation characteristics during high isolation. In addition, by adopting the same configuration, it is possible to prevent noise generated in the attenuation control circuit unit composed of resistors, etc., from entering the high-frequency signal line via the gate and improve the noise characteristics. As a result, the first and second problems can be solved.

[0034] In addition, the signal attenuating FET has a triple-well structure, and a resistor having a high resistance value is inserted between the back gate of the signal attenuating FET and the substrate. A path through which a signal leaks to the substrate is blocked, and the attenuation control characteristic can be improved. As a result, the third problem can be solved. In addition, the same manufacturing process as the signal attenuating FET · By providing a source bias for the signal attenuating FET in the bias circuit configured using a FET that has a threshold variation due to temperature fluctuations, the signal attenuating FET The threshold manufacturing process and temperature variations can be corrected. As a result, the fourth problem can be solved. In this case, the bias value generated by the (source) bias circuit decreases when the threshold voltage of the signal attenuation FET increases due to temperature fluctuations in the manufacturing process, and conversely the threshold value of the signal attenuation FET. It is preferable that the voltage is controlled so as to increase when the voltage decreases.

[0035] Furthermore, since a capacitor or a capacitor and a switch (a series circuit) are provided between the connection portion of the source bias resistor and the drain bias resistor of the signal attenuation FET and the ground terminal, the source bias resistor, the drain The path through which the signal leaks from the input terminal to the output terminal can be blocked via the bias resistor, and the attenuation characteristic at the time of high isolation can be improved. As a result, the fifth problem can be solved.

[0036] By combining the improvement effects of the above five points, the signal leakage path can be cut off more than the variable attenuation circuit of the first invention, and the noise leakage path equivalent to the circuit of the first invention can be cut off. The stabilization of the threshold voltage can be achieved, and the original performance of the transistor, such as attenuation characteristics and noise characteristics, can be maximized. As a result, a linear attenuation control characteristic can be realized in any attenuation state that changes continuously, and a variable attenuation circuit that has excellent noise characteristics and is resistant to variations can be realized.

[0037] A high-frequency radio circuit system according to a fourth aspect of the present invention includes at least one first, second, or second

A wireless transmission device including the variable attenuation circuit according to the third aspect of the invention, at least one oscillator, and at least one high-frequency amplifier, and at least one antenna connected to the wireless transmission device for transmitting and receiving a radio frequency.

[0038] According to this configuration, the same effects as those of the first, second or third invention can be obtained.

[0039] Each claim will be described below.

[0040] A first variable attenuation circuit of the present invention includes a signal attenuator having a signal attenuating element inserted in series in a signal path between a signal input unit and a signal output unit, and a signal attenuating element. Attenuation control circuit section for supplying an attenuation control signal, bias circuit section for applying a bias to the signal attenuation element, and a connection between the signal attenuation element and the attenuation control circuit section and the ground terminal. With connected capacity!

[0041] In the first variable attenuation circuit of the present invention, the signal attenuating element is an FET, and the attenuation control circuit section applies an attenuation control signal to the gate terminal of the FET to control the ON resistance of the FET. The bias circuit section applies a bias to the source terminal of the FET, and the capacitance is connected between the gate terminal of the FET and the ground terminal.

[0042] The second variable attenuation circuit of the present invention includes a signal attenuator having a signal attenuating FET inserted in series in a signal path between the signal input unit and the signal output unit, and a signal attenuating FET. An attenuation control circuit that controls the ON resistance of the signal attenuating FET by giving an attenuation control signal to the gate terminal, and a bias circuit that applies a bias to the source terminal of the signal attenuating FET. The circuit section has a bias FET that compensates for variations in the threshold voltage of the signal attenuating FET.

[0043] The third variable attenuation circuit of the present invention includes a signal attenuator having a signal attenuating FET inserted in series in a signal path between the signal input unit and the signal output unit, and a signal attenuating FET. Attenuation control circuit that controls the ON resistance of the signal attenuation FET by applying an attenuation control signal to the gout terminal, a bias circuit that applies a bias to the source terminal of the signal attenuation FET, and a signal attenuation FET And a resistor connected between the back gate portion and the substrate.

[0044] A fourth variable attenuation circuit of the present invention includes a signal attenuation unit having a signal attenuation FET inserted in series in a signal path between a signal input unit and a signal output unit, and a signal attenuation FET. Attenuation control circuit that controls the ON resistance of the signal attenuation FET by applying an attenuation control signal to the gate terminal, a bias circuit that applies a bias to the source terminal of the signal attenuation FET, and a bias circuit A capacitor or a capacitor and a switch connected to the ground terminal are provided.

[0045] In the fifth variable attenuation circuit of the present invention, FET is inserted into the signal path between the signal input unit and the signal output unit, and the signal applied to the gate terminal of this FET is applied to the signal input unit. A signal attenuator that controls and outputs the attenuation of a given signal, an attenuation control circuit that applies a signal to the gate terminal to vary the ON resistance value of the FET, and a terminal connected to the source terminal of the FET A first capacitive element is connected between the other end of the resistive element and the ground terminal, and a bias circuit section that applies a DC voltage via the resistive element is connected between the back gate section of the FET and the ground terminal. And a second capacitor element between the gate terminal and the ground terminal. Is connected.

[0046] A sixth variable attenuation circuit of the present invention includes a signal attenuation unit having a signal attenuation element inserted between a signal path between the signal input unit and the signal output unit and the ground terminal,

An attenuation control circuit unit for providing an attenuation control signal to the signal attenuation element;

A bias circuit section for applying a bias to the signal attenuating element;

And a capacitor connected between a connection portion between the signal attenuating element and the bias circuit portion and a ground terminal.

[0047] In the sixth variable attenuation circuit of the present invention, the signal attenuating element comprises a FET, and the attenuation control circuit unit applies an attenuation control signal to the drain terminal of the FET to control the ON resistance of the FET, The bias circuit section applies a bias to the gate terminal of the FET, and the capacitance is connected between the gate terminal of the FET and the ground terminal.

[0048] A seventh variable attenuation circuit of the present invention includes a signal attenuation unit including a signal attenuation FET inserted between a signal path between the signal input unit and the signal output unit and a ground terminal, and a signal Provided with an attenuation control circuit that controls the ON resistance of the signal attenuation FET by giving an attenuation control signal to the drain terminal of the attenuation FET and a bias circuit that applies a bias to the gate terminal of the signal attenuation FET The bias circuit section has a bias FET that compensates for variations in the threshold voltage of the signal attenuating FET.

[0049] An eighth variable attenuation circuit of the present invention includes a signal attenuation unit having a signal attenuation FET inserted between a signal path between a signal input unit and a signal output unit and a ground terminal, and a signal Attenuation control circuit that controls the ON resistance of the signal attenuation FET by applying an attenuation control signal to the drain terminal of the attenuation FET, a bias circuit that applies a bias to the gate terminal of the signal attenuation FET, and a signal Provided with a resistor connected between the back gate of the attenuating FET and the substrate

[0050] In the ninth variable attenuation circuit of the present invention, the first capacitive element and the FET current path terminal pair are connected in series between the signal path between the signal input section and the signal output section and the AC ground. A signal attenuator that controls the amount of attenuation of the signal applied to the signal input by the signal applied to the connection between the first capacitor element and one end of the current path of the FET that is inserted and connected, and the FET Attenuation control circuit that applies a signal to one end to vary the ON resistance of the FET, and the gate of the FET A bias circuit section for applying a DC voltage to the terminal via a resistance element; a resistor connected between the back gate section of the FET and the ground terminal; and a second capacitive element between the gate terminal and the ground terminal. Is connected.

[0051] A tenth variable attenuation circuit according to the present invention includes a first signal attenuation unit having a first signal attenuation element inserted in series in a signal path between a signal input unit and a signal output unit; A first attenuation control circuit for supplying an attenuation control signal to the first signal attenuation element, a first bias circuit for applying a bias to the first signal attenuation element, and a first signal attenuation Between the first capacitor connected between the connection between the element and the first attenuation control circuit section and the ground terminal, and between the signal path between the signal input section and the signal output section and the ground terminal. A second signal attenuating unit having a second signal attenuating element inserted; a second attenuation control circuit for supplying an attenuation control signal to the second signal attenuating element; and a second signal attenuating unit. A second noise circuit section for applying a bias to the device, a connection between the second signal attenuating element and the second bias circuit section, and grounding And a second capacitor connected between the child.

[0052] In the tenth variable attenuation circuit of the present invention, the first signal attenuating element is composed of the first FET force, and the first attenuation control circuit unit is attenuated to the gate terminal of the first FET. The first bias circuit block applies a bias to the source terminal of the first FET, and the first capacitor is grounded with the gate terminal of the first FET. The second signal attenuating element is composed of the second FET, and the second attenuation control circuit section applies the attenuation control signal to the drain terminal of the second FET to provide the second FET. The ON resistance of the FET is controlled, the second bias circuit section applies a bias to the gate terminal of the second FET, and the second capacitor is connected between the gate terminal of the second FET and the ground terminal. Preferably it is.

[0053] An eleventh variable attenuation circuit of the present invention includes a first signal attenuation unit having a first signal attenuation FET inserted in series in a signal path between a signal input unit and a signal output unit. The first attenuation control circuit that controls the ON resistance of the first signal attenuation FET by applying an attenuation control signal to the gate terminal of the first signal attenuation FET, and the first signal attenuation FET A second bias circuit section having a first bias circuit section for applying noise to the source terminal, and a second signal attenuating FET inserted between the signal path between the signal input section and the signal output section and the ground terminal. Attenuation control signals are applied to the signal attenuator and the drain terminal of the second signal attenuating FET to reduce the second signal. The first bias circuit includes a second attenuation control circuit that controls the ON resistance of the attenuation FET, and a second bias circuit that applies a bias to the gate terminal of the second signal attenuation FET. Part has a first bias FET that compensates for variations in threshold voltage of the first signal attenuating FET,

The second bias circuit section includes a second bias FET that compensates for variations in threshold voltage of the second signal attenuating FET.

[0054] A twelfth variable attenuation circuit according to the present invention includes a first signal attenuation unit having a first signal attenuation FET inserted in series in a signal path between a signal input unit and a signal output unit. The first attenuation control circuit that controls the ON resistance of the first signal attenuation FET by applying an attenuation control signal to the gate terminal of the first signal attenuation FET, and the first signal attenuation FET A second bias circuit section having a first bias circuit section for applying noise to the source terminal, and a second signal attenuating FET inserted between the signal path between the signal input section and the signal output section and the ground terminal. A second attenuation control circuit for controlling the ON resistance of the second signal attenuation FET by supplying an attenuation control signal to the drain terminal of the second signal attenuation FET, A second bias circuit for applying a bias to the gate terminal of the signal attenuating FET, and a back gate for the first signal attenuating FET. Comprising a first resistor connected between the plate and a second resistor connected between the Roh Kkugeto and the substrate of the second signal attenuating FET.

[0055] A thirteenth variable attenuation circuit of the present invention includes a first signal attenuation unit having a first signal attenuation FET inserted in series in a signal path between a signal input unit and a signal output unit. The first attenuation control circuit that controls the ON resistance of the first signal attenuation FET by applying an attenuation control signal to the gate terminal of the first signal attenuation FET, and the first signal attenuation FET A second bias circuit section having a first bias circuit section for applying noise to the source terminal, and a second signal attenuating FET inserted between the signal path between the signal input section and the signal output section and the ground terminal. A second attenuation control circuit for controlling the ON resistance of the second signal attenuation FET by supplying an attenuation control signal to the drain terminal of the second signal attenuation FET, The second bias circuit section that applies a bias to the gate terminal of the signal attenuation FET, and the first bias circuit section and the ground terminal It has a connected capacity or capacity and switch.

In the thirteenth variable attenuation circuit of the present invention, the back gate of the first signal attenuation FET Preferably, a first resistor is connected between the first terminal and the ground terminal, and a second resistor is connected between the back gate section of the second signal attenuating FET and the ground terminal.

[0057] A high frequency radio circuit system according to the present invention includes a radio including at least one variable attenuation circuit including at least one of the variable attenuation circuits according to the present invention, at least one high frequency amplification circuit, and at least one oscillator. The transmitter includes a transmitter and an antenna that is connected to the radio transmitter and transmits a radio frequency.

[0058] According to the configuration of the present invention, the same effect as the variable attenuation circuit of the present invention can be obtained.

The invention's effect

[0059] According to the variable attenuation circuit and the high-frequency radio circuit system of the present invention, the path for signal leakage through the parasitic capacitance generated between the drain gate and the gate source of the signal attenuation FET is interrupted. The isolation characteristic at the time of attenuation can be improved. At the same time, it is possible to prevent the noise generated in the attenuation control circuit unit from entering the signal line via the gate. In addition, by inserting a resistor with a high resistance between the back gate of the signal attenuation FET and the substrate, the path through which the signal leaks to the substrate through the back gate is blocked to improve the attenuation control characteristics. be able to. In addition, it can be affected by variations in the threshold value of the signal attenuation FET due to manufacturing processes and temperature fluctuations. In addition, since a capacitor or a capacitor and a switch are provided between the connection portion of the source bias resistor and the drain bias resistor and the ground terminal, the input terminal is connected to the output terminal via the source bias resistor and the drain bias resistor. It is possible to block the signal leakage path and improve the attenuation characteristics during high isolation. With all the above effects, linear attenuation control characteristics can be realized continuously over a wide range from a high attenuation state to a reduced attenuation state. As a result, it has become possible to fabricate a multi-band, multi-communication variable attenuation circuit that has been difficult due to signal leakage, noise, and process variations.

Brief Description of Drawings

FIG. 1 is a circuit diagram showing a circuit configuration of a variable attenuation circuit according to Embodiment 1 of the present invention.

[Figure 2] Figure 2 shows a conventional example of a variable attenuation circuit fabricated using the GaAs process. FIG.

FIG. 3 is a circuit diagram showing a circuit configuration of a variable attenuation circuit according to Embodiment 2 of the present invention.

4] FIG. 4 is a circuit diagram showing a circuit configuration of the variable attenuation circuit according to the third embodiment of the present invention.

5] FIG. 5 is a block diagram showing a circuit configuration of the variable attenuation circuit according to the fourth embodiment of the present invention.

6] FIG. 6 is a circuit diagram showing a circuit configuration of the variable attenuation circuit according to the fourth embodiment of the present invention.

7] FIG. 7 is a block diagram showing an example of a high-frequency wireless transmission circuit system to which the present invention is applied.

[FIG. 8] FIG. 8 is a schematic diagram showing fluctuation of each bias value of the MOSFET with respect to temperature in the conventional variable attenuation circuit as shown in FIG.

FIG. 9 is a schematic diagram showing the attenuation amount of the variable attenuation circuit with respect to the control voltage in the conventional variable attenuation circuit as shown in FIG.

[FIG. 10] FIG. 10 is a schematic diagram showing fluctuations of each bias value of the MOSFET with respect to temperature in the variable attenuation circuit of FIGS. 1 and 4 in Example 1 and Example 3 of the present invention.

FIG. 11 is a schematic diagram showing the attenuation amount of the variable attenuation circuit with respect to the control voltage in the variable attenuation circuit of FIGS. 1 and 4 in Example 1 and Example 3 of the present invention.

FIG. 12 is a schematic diagram showing fluctuation of each bias value of the MOSFET with respect to temperature in the variable attenuation circuit of FIG. 3 in Example 2 of the present invention.

FIG. 13 is a schematic diagram showing the attenuation amount of the variable attenuation circuit with respect to the control voltage in the variable attenuation circuit of FIG. 3 in Example 2 of the present invention.

FIG. 14A is a diagram showing a simulation result of the attenuation with respect to the control voltage in the variable attenuation circuit of FIG. 4 and the conventional variable attenuation circuit in Example 3 of the present invention.

[FIG. 14B] FIG. 14B shows a variable attenuation circuit of FIG. 4 in Example 3 of the present invention and a conventional variable attenuation circuit. It is a figure which shows the simulation result of the noise characteristic with respect to control voltage in an attenuation circuit.

FIG. 15A is a diagram showing a simulation result of attenuation with respect to control voltage in the variable attenuation circuit of FIG. 6 and the conventional variable attenuation circuit in Example 4 of the present invention.

FIG. 15B is a diagram showing simulation results of noise characteristics with respect to control voltage in the variable attenuation circuit in FIG. 6 and the conventional variable attenuation circuit in Example 4 of the present invention.

FIG. 16 is a block diagram showing a circuit configuration of a conventional variable attenuation circuit.

Explanation of symbols

100 Signal attenuation part

101 Attenuation control circuit

102 Source bias circuit with threshold bias correction function

103 Capacitance added to FET gate

104 Signal input terminal

105 Signal output terminal

106 Attenuation control terminal

107 Power supply voltage terminal

111 Signal attenuation MOSFET

112, 113 DC breaking capacity

114 Gate bias supply resistor

115, 116 Resistance for attenuation control

117 MOSFET for source bias generation

118, 119, 120, 121 Source noise generating resistor

122 Source bias generation resistor

123 Resistance for drain bias generation

124 Resistance added to the back gate of the FET

231 signal input terminal

232 signal output terminal 233 Attenuation control terminal

234 Source bias supply pin

235 Gate bias supply pin

236, 237 Ground terminal

238, 242 DC breaking capacity

239 Source bias supply resistor

240 Signal attenuation FET

241 Drain bias supply resistor

243, 248, 249, 254 DC breaking capacity

244, 247, 250, 253 I / O matching resistors

245, 251 Shunt side signal attenuating FET

246, 252 Source potential supply resistor

255, 257, 258 Gate bias resistor

256, 259 Drain bias supply resistors

260 Signal attenuator

261, 262 Shunt side signal attenuator

300 Shunt side signal attenuator

301 Attenuation control circuit

302 Shiki! /, Gate bias circuit with value bias correction function

303 Capacitance added to FET gate

304 signal input terminal

305 Signal output terminal

306 Attenuation control terminal

307 Power supply voltage terminal

311 MOSFET for signal attenuation

312, 313 DC breaking capacity

314 Impedance adjustment resistor

315, 316 DC breaking capacity 317 Drain bias supply resistor

318 MOSFET for generating gate bias

319, 320, 321, 322 Resistance for generating a gate noise

323 Gate bias generation resistor

324 Source bias generation resistor

Resistance added to the back gate of the 325 FET

400 Signal attenuator

401 Attenuation control circuit

402 Shiki! /, Source bias circuit with value bias correction function

403 Capacitance added to FET gate

404 signal input terminal

405 Signal output terminal

406 Attenuation control terminal

407 Power supply voltage terminal

411 Signal attenuation MOSFET

412, 413 DC breaking capacity

414 Gate bias supply resistor

415, 416 Resistance for attenuation control

417 MOSFET for source bias generation

418, 419, 420, 421 Source noise generating resistor

422 Source bias generation resistor

423 Resistor for drain bias generation

424 Resistor added to FET back gate

425 Capacitance added to the source bias circuit

426 Switch added to source bias circuit

501 and 502 Variable attenuation circuit shown in Fig. 4

503, 504 Variable attenuation circuit shown in Fig. 3

505 signal input terminal 506 Signal output terminal

507 Attenuation control terminal

601 signal input terminal

602 signal output terminal

603 Attenuation control terminal

611, 613 Variable attenuation circuit shown in Fig. 4

612, 614 Variable attenuation circuit shown in Fig. 3

615 Source bias generation circuit shown in Figure 4

616, 617 Gate bias generation circuit shown in Figure 3

701 oscillator

702 divider

703 buffer

704 Variable attenuation circuit

705 Driver amplifier

706 High frequency amplifier circuit

707 antenna

1601, 1602 Variable attenuator shown by reference numeral 260 in FIG.

1603 Variable attenuator indicated by reference numeral 261 in FIG.

1604 Variable attenuation section indicated by reference numeral 262 in FIG.

BEST MODE FOR CARRYING OUT THE INVENTION

[0062] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0063] (Example 1)

Embodiment 1 of the present invention is a variable attenuation circuit (integrated circuit) corresponding to the first, second, third, and fourth points of the problem. This will be described below with reference to FIG.

[0064] The variable attenuation circuit according to the first embodiment of the present invention shown in FIG. 1 is an attenuation circuit that attenuates a high frequency signal input from the signal input terminal 104 and outputs the attenuated signal from the signal output terminal 105. A variable attenuation circuit that can be controlled from the attenuation control terminal 106 is assumed. In addition, this variable attenuation circuit is assumed to be fabricated on, for example, a Si semiconductor substrate. [0065] Specifically, the variable attenuation circuit according to the present invention includes a signal attenuation MOSFET (signal attenuation element) 111 inserted in series between the signal input terminal 104 and the signal output terminal 105. The signal attenuation MOSFET 111 includes an attenuation unit 100, an attenuation amount control circuit unit 101 that controls the ON resistance of the signal attenuation MOSFET 111, and a source bias circuit unit 102 that applies a bias to the source of the signal attenuation MOSFET 111. The high frequency signal is attenuated by an attenuation amount corresponding to the attenuation amount control signal generated by the amount control circuit unit 101.

In this variable attenuation circuit, a capacitor 103 is added between the gate of the signal attenuation MOSFET 111 and the ground terminal. The effect of the capacity 103 is roughly divided into two points. First point force Attenuation control circuit unit 101 prevents noise component force S from entering the high-frequency signal line (the line from signal input terminal 104 to signal output terminal 105) via the gate of MOSFET 111 for signal attenuation. It is. Prevents leakage of high-frequency signals between the signal input terminal 104 and the signal output terminal 105 in the high attenuation state due to the influence of parasitic capacitance generated between the drain gate of the second-point force S and the MOSFET 111 for signal attenuation and between the gate and source. That is.

[0067] Further, the source bias circuit unit 102 of this variable attenuation circuit generates the bias voltage using the source bias generation MOSFET 117 having the same threshold voltage / variation (temperature characteristic) as the signal attenuation MOSFET 111! As a result, the manufacturing process of the signal attenuating MOSFET 111 has an effect of correcting variations in threshold voltage due to temperature fluctuations.

In addition, the signal attenuating MOSFET 111 of this variable attenuating circuit has a triple-well structure, and a resistor 124 having a high resistance value is additionally provided between the back gate portion and the substrate. The effect of the resistor 124 having this high resistance value is to prevent a signal from leaking to the substrate through the back gate.

[0069] Hereinafter, the circuit connection of the variable attenuation circuit will be specifically described.

First, as the signal attenuating element, for example, an N-channel MOS FET having a triple-well structure is suitable. The signal attenuating MOSFET 111 is inserted in series in the signal path between the signal input terminal 104 and the signal output terminal 105 of the high frequency variable attenuating circuit, and between the signal input terminal 104 and the signal attenuating MOSFET 111. The DC component is cut off and the high frequency A DC blocking capacitor 112 that passes only the component is inserted, and a DC blocking capacitor 113 is inserted between the signal attenuation MOSFET 111 and the signal output terminal 105. Between the back gate portion of the signal attenuation MOSFET 111 and the substrate, a resistor 124 having a high resistance value is inserted to block signal leakage.

Next, the attenuation control circuit unit 101 is connected to the gate of the signal attenuation MOSFET 111. The configuration of the attenuation control circuit unit 101 will be described. The attenuation control resistor 115 and the attenuation control resistor 116 are connected in series. The other end of the attenuation control resistor 115 is connected to the attenuation control terminal (Vc) 106, and the other end of the resistor 116 is connected. One terminal is connected to the ground terminal. Between the connection between the attenuation control resistor 115 and the attenuation control resistor 116 and the gate of the signal attenuation MOSFET 111, there is a resistor 114 having a high resistance value that cuts off high frequency and allows only DC to pass. It is connected. Further, a capacitor 103 is added between the gate of the signal attenuating MOSFET 111 and the ground terminal.

The source bias circuit section 102 connected to the source terminal of the signal attenuating MOSFET 111 will be described. The resistor 120 and the resistor 121 are connected in series, the other terminal of the resistor 120 is connected to the power supply voltage terminal (Vdd) 107, and the other terminal of the resistor 121 is connected to the ground terminal. The gate of the source bias generating MOSFET 117 is connected to the connection portion between the resistor 120 and the resistor 121, and the source bias generating MOSFET 117 has the same manufacturing process and temperature variation variation as the signal attenuating MOSFET 111. A resistor 118 is connected between the drain of the source bias generating MOSFET 117 and the power supply voltage terminal 107, and a resistor 119 is connected between the source of the source bias generating MOSFET 117 and the ground terminal. Also, a resistor 122 having a high resistance value that cuts off the high frequency and passes only DC is connected between the source of the source bias generating MOSFET 117 and the source of the signal attenuating MOSFET 111. A resistor 123 having a resistance value is connected between the drain of the MOSFET 111 for attenuating and high so that only a DC is allowed to pass through the high frequency!

[0073] In recent years, wireless communication systems have become multiband and multicommunication systems! Among them, for example, there are multi-communication systems such as UMTS communication system and GSM communication system. The UMTS communication system requires a transmission power variable range of 80 dB or more in the transmission circuit. Highly accurate transmission power control linearity is required. The GSM communication system requires high noise characteristics. The variable attenuation circuit used in the high-frequency radio transmission circuit block must satisfy the characteristics of these two communication methods. In that case, process variations and high linearity and noise characteristics are required regardless of temperature fluctuations. Explain how to satisfy each requirement!

First, a method for realizing highly accurate linearity regardless of process variations and temperature variations will be described. 8 (A) and (B) are diagrams showing fluctuations of each voltage value with respect to the temperature of the variable attenuation circuit as shown in FIG. 2, and FIG. 9 is a diagram showing gain characteristics with respect to the control voltage. . In Fig. 8, the horizontal axis represents temperature and the vertical axis represents voltage. In Fig. 9, the horizontal axis represents the attenuation control voltage Vc, and the vertical axis represents the gain of the variable attenuation circuit. It shows three control characteristics at normal temperature (for example, 25 ° C), low temperature lower than normal temperature, and high temperature higher than normal temperature.

In FIG. 8A, Vg represents the gate potential of the signal attenuating GaAsFET 240 in FIG. 2, and Vref is the potential applied to the source bias supply terminal 234 in FIG. 2, ie, the signal attenuating GaAsFET 240. This represents the source potential, and Vth represents the threshold voltage Vth of the signal attenuating GaAsFET 240 in FIG. Vg – Vref – Vth in Fig. 8 (B) is the calculation result calculated using Vg, V ref and Vth shown in Fig. 8 (A). When Vg−Vref−Vth> 0, the GaAsFET 240 for signal attenuation starts to operate, the ON resistance begins to decrease gradually, and the attenuation decreases gradually. This point is point A in Fig. 9, and the voltage at this time is V. here

X

When the temperature rises, the threshold voltage Vth of the signal attenuating GaAsFET 240 increases as the temperature rises. Therefore, in order to set Vg−Vref−Vth = 0, a larger gate potential Vg is required than at normal temperature, and the voltage value at which the signal attenuating GaAsFET 240 starts to operate increases and increases to V force V. Conversely, if the temperature drops,

X Y

The signal attenuation GaAsFET240 begins to operate at a small Vg, and the V force decreases to V. That

X Z

As a result, the control characteristics have a large difference depending on the temperature as shown in Fig. 9, and the linearity deteriorates.

FIGS. 10A and 10B are diagrams showing the variation of each voltage value with respect to the temperature of the variable attenuation circuit when the source bias circuit unit 102 as shown in FIG. 1 is used, and FIG. FIG. 6 is a diagram showing a gain characteristic with respect to a control voltage at that time. 10 and 11, the vertical axis and The horizontal axis is the same as in Fig. 8 and Fig. 9, respectively. In Fig. 10, unlike Fig. 8, the source bias voltage Vref is reduced as the temperature rises. As a result, when the temperature increases and / or when the value voltage Vth increases and when the temperature decreases and when the value voltage Vth decreases, Vg—Vref—Vth is always constant and the temperature Regardless of the fluctuation (low temperature, normal temperature, high temperature), the same control characteristics can be drawn as shown in Fig. 11. Vg is the gate voltage of the MOSFET 111 for signal attenuation.

A circuit operation for realizing the variation correction as shown in FIG. 11 will be described using the variable attenuation circuit of FIG. The gate potential of the source bias generating MOSFET 117 of the source bias circuit unit 102 in FIG. 1 is determined by resistance division between the resistor 120 and the resistor 121. Like the signal attenuation MOSFET 111, the source bias generation MOSFET 117 has the characteristic that the threshold voltage increases as the temperature rises.Therefore, the threshold voltage increases as the temperature rises, while the gate potential increases. Since it is constant, the source potential decreases and the current flowing through the source bias generating MOSFET 117 decreases. As a result, the source bias potential Vref of the signal attenuating MOSFET 111 is decreased, and the threshold voltage fluctuation can be corrected.

Next, a circuit operation for realizing a linear control characteristic will be described using the variable attenuation circuit in FIG. A continuous control voltage from 0 V to the power supply voltage potential is input to the attenuation control terminal (Vc) 106 of the attenuation control circuit unit 101 in FIG. This control voltage is divided by the attenuation control resistor 115 and the attenuation control resistor 116 and input to the gate of the signal attenuation MOSFET 111. The signal attenuating MOSFET 111 is used with a drain-source bias of 0 V. When the gate potential is 0 V, the ON resistance gradually increases as the gate resistance increases, and the gate potential decreases. When becomes the power supply voltage, the ON resistance is minimized. As the ON resistance changes, the attenuation of the pass characteristic from the signal input terminal 104 to the signal output terminal 105 also varies. Further, by dividing the voltage of the attenuation control terminal 106 by the attenuation control resistor 115 and the attenuation control resistor 116, an arbitrary control characteristic can be realized.

[0079] However, when a variable attenuation circuit is realized on a Si substrate, for example, the signal leaks due to the parasitic capacitance generated between the drain gate and the gate source of the signal attenuation MOSF ET 111, and the signal attenuation MOSFET 111 The attenuation determined by the ON resistance cannot be obtained, and is linear Sex cannot be secured. In order to eliminate the influence, the capacitor 103 is inserted between the gate of the signal attenuating MOSFET 111 and the ground terminal. By inserting the capacitor 103, the signal leakage path between the drain gate and the gate source of the MOSFET 111 for signal attenuation is cut off to ensure linearity.

[0080] When the variable attenuation circuit is realized with the same Si substrate as described above, for example, the impedance between the back gate of the signal attenuating MOSFET 111 and the substrate is lowered due to the low substrate resistance. Through this part, the signal leaks to the board, and the attenuation determined by the ON resistance of the MOSF ET111 for signal attenuation cannot be obtained, and linearity cannot be ensured. In order to eliminate the influence, for example, the signal attenuation MOSFET 111 is manufactured in a triple-well structure, and a resistor 124 having a high resistance value is inserted between the back gate of the signal attenuation MOSFET 111 and the substrate. Thus, the path through which the signal leaks is blocked to ensure linearity.

In addition, this variable attenuation circuit has improved noise characteristics due to the addition of the capacitor 103. The attenuation amount control circuit unit 101 is usually composed of a resistor. Therefore, the noise generated by this resistor enters through the gate of the signal attenuating MOSFET 111 and is applied to the high-frequency signal coming from the signal input terminal 104, deteriorating the noise characteristics, for example, GSM communication system reception band noise, etc. No longer meet the requirements.

However, the addition of the capacitor 103 reduces the noise generated in the attenuation control circuit unit 101 to the capacitor.

The noise characteristics can be improved in any state of the variable attenuation circuit which is cut off by the filter effect of 103 and resistor 114 and continuously changes.

[0083] As described above, by adding the source bias circuit unit 102, the capacitor 103, and the resistor 124 having a high resistance value added to the back gate to the variable attenuation circuit having the signal attenuation MOSFET 111, the manufacturing process is performed. 'It is possible to correct the threshold variation of the signal attenuating MOSFET 111 due to variations in temperature fluctuations, eliminate the signal leakage in the signal attenuating MOSFET 111 in any attenuation state, and improve the linearity. Came. Furthermore, the noise generated in the attenuation control circuit unit 101 can be reduced, and the noise characteristics can be improved. As a result, a variable attenuation circuit compatible with the multi-band 'multi-communication system can be realized by the Si process, and it can be made into a single chip with other wireless circuit blocks. [0084] Note that the source bias circuit unit 102, the capacitor 103, and the resistor 124, or only two of them may be connected. The MOSFET may be a P-channel MOSFET. In addition, any structure that can achieve the same effect without using a triple-well structure is acceptable.

[0085] (Example 2)

The second embodiment of the present invention is a variable attenuation circuit (integrated circuit) corresponding to the first, second, third, and fourth points of the problem. This will be described below with reference to FIG.

The variable attenuation circuit according to the second embodiment of the present invention shown in FIG. 3 is an attenuation circuit that attenuates a high-frequency signal input from the signal input terminal 304 and outputs the attenuated signal from the signal output terminal 305, and the attenuation amount is external. Assume a variable attenuation circuit that can be controlled by the attenuation control terminal 306, which is a terminal. In addition, this variable attenuation circuit is assumed to be fabricated on, for example, a Si semiconductor substrate.

Specifically, the variable attenuation circuit according to the present invention is a signal attenuation MOSFET (signal attenuation) inserted between the signal path between the signal input terminal 304 and the signal output terminal 305 and the ground terminal. Element) 311, a signal attenuation unit 311 that controls the ON resistance of the signal attenuation MOSFET 311, and a gate bias circuit unit 302 that applies bias to the gate of the signal attenuation MOSFET 311. The signal attenuation MOSFET 311 attenuates the high-frequency signal with an attenuation amount corresponding to the attenuation amount control signal generated by the attenuation amount control circuit unit 301.

In this variable attenuation circuit, a capacitor 303 is added between the gate of the signal attenuation MOSFET 311 and the ground terminal. The effect of the capacitor 303 is to prevent the noise component force S generated in the gate bias circuit section 302 from entering the high-frequency signal line via the gate of the MOSFET 311 for signal attenuation.

Further, the gate bias circuit section 302 of this variable attenuation circuit creates a bias by using a gate bias generation MOSFET 318 having the same threshold voltage fluctuation as the signal attenuation MOSFET 311, thereby reducing the signal attenuation. This has the effect of correcting the threshold voltage due to the manufacturing process and temperature fluctuation of the MOSFET 311 and correcting the variation of the value voltage.

[0090] In addition, the signal attenuating MOSFET 311 of this variable attenuating circuit has a triple wel A resistor 325 having a high resistance value is added between the back gate portion and the substrate. The effect of the resistor 325 having this high resistance value is to prevent a signal from leaking to the substrate through the back gate.

Hereinafter, the circuit connection of the variable attenuation circuit will be specifically described.

First, the signal attenuating element is preferably an N-channel MOSFET having a triple-well structure, for example. The MOSFET 311 for signal attenuation is inserted between the signal path between the signal input terminal 304 and the signal output terminal 305 of the high-frequency variable attenuation circuit and the ground terminal, and the signal attenuation terminal 300 and the signal attenuation unit 300 are connected to each other. Between them, a DC blocking capacitor 312 that blocks the DC component and passes only the high frequency component is inserted, and a DC blocking capacitor 313 is also inserted between the signal attenuating unit 300 and the signal output terminal 305. Has been. Reference numeral 314 indicates an impedance adjusting resistor, and reference numerals 315 and 316 indicate DC breaking capacities. Reference numeral 324 denotes a source bias generating resistor. Between the back gate portion of the signal attenuating MOSFET 311 and the substrate, a resistor 325 having a high resistance value is inserted to block signal leakage!

Next, an attenuation amount control circuit unit 301 is connected to the drain of the signal attenuation MOSFET 311. The attenuation control circuit unit 301 is connected to a resistor 317 having a high resistance value that cuts high frequency and allows only DC to pass between the attenuation control terminal (Vc) 306 and the drain of the signal attenuation MOS FET 311! / Has a structure to speak! /

Next, the gate bias circuit unit 302 connected to the gate of the signal attenuating MOSFET 311 will be described. Resistor 319 and resistor 320 are connected in series, the other terminal of resistor 319 is connected to power supply voltage terminal (Vdd) 307, and the other terminal of resistor 320 is connected to the ground terminal. The gate of the gate bias generating MOSFET 318 is connected to the connection between the resistor 319 and the resistor 320, and this gate bias generating MOSFET 318 has the same manufacturing process as the signal attenuating MOSFET 311 'temperature variation variation. A resistor 321 is connected between the drain of the MOSFET 318 for generating the gate bias and the power supply voltage terminal (Vdd) 307, and a resistor 322 is connected between the source of the MOSFET 318 for generating the gate bias and the ground terminal. Yes. Further, a resistor 323 having a high resistance value that cuts off high frequency and allows only DC to pass is connected between the drain of the gate bias generating MOSFET 318 and the gate of the signal attenuating MOSFET 311. In addition, signal attenuation A capacitor 303 is added between the gate of the MOSFET 311 and the ground terminal.

A method for realizing highly accurate linearity regardless of process variations and temperature fluctuations in the second embodiment will be described. The difference between Fig. 3 and Fig. 1 is whether the attenuation control circuit is connected to the gate or the drain.In Fig. 3, the attenuation control circuit is connected to the drain. The bias circuit unit is connected to the gate.

FIGS. 12 (A) and 12 (B) are graphs showing changes in each voltage value with respect to the temperature of the variable attenuation circuit as shown in FIG. 3, and FIG. 13 is a gain with respect to the control voltage at that time. It is a diagram showing the characteristics. In FIG. 12A, Vref represents the gate potential of the signal attenuating MOSFET 311 in FIG. 3, Vc represents the drain potential of the signal attenuating MOSFET 311, and Vth is the threshold voltage of the signal attenuating MOSFET 311! /, The value voltage Represents! /

[0097] Vref—Vc—Vth in FIG. 12B is a calculation result calculated using Vref, Vc, and Vth shown in FIG. When Vref—Vc—Vth> 0, the FET starts to operate, the ON resistance begins to decrease gradually, and the attenuation decreases gradually. In Fig. 12, Vref is reduced as the temperature rises. As a result, even if the temperature increases and the threshold voltage Vth increases, the temperature also decreases! / Even if the value voltage Vth decreases, Vref—Vc—Vth is always constant, resulting in temperature fluctuations. Regardless, the same control characteristics can be drawn as shown in FIG.

The circuit operation for realizing the variation correction as shown in FIG. 13 will be described using the variable attenuation circuit of FIG. The gate potential of the MOSFET 318 for generating the gate bias in the gate bias circuit section 302 in FIG. 3 is determined by resistance division between the resistor 319 and the resistor 320. The MOSFET 318 for gate bias generation has the characteristic that the threshold voltage increases as the temperature rises, like the MOSFET 311 for signal attenuation. Therefore, the threshold voltage increases as the temperature rises, while the gate potential remains constant. Therefore, the source potential decreases and the current flowing through the MOS bias 318 for generating the gate bias occurs. As a result, the voltage drop due to the bias resistor 321 also decreases, the drain potential of the gate bias generating MOSFET 318 increases, the gate bias potential of the signal attenuating MOSFET 311 increases, and threshold voltage fluctuation correction can be realized.

[0099] Next, the circuit operation for realizing the linear control characteristics will be described using the variable attenuation circuit in FIG. explain. A continuous control voltage from 0 V to the power supply voltage potential is input to the attenuation control terminal (Vc) 306 of the attenuation control circuit unit 301 in FIG. This control voltage is input to the drain potential of the MOSFET 311 for attenuation control. The signal attenuating MOSFET 311 is used with a drain-source bias of 0 V. When the drain potential is at the power supply voltage, the ON resistance is the largest, and as the drain potential decreases, the ON resistance gradually decreases and the drain potential force S0V minimizes ON resistance. As the ON resistance changes, the attenuation of the pass characteristic from the signal input terminal 304 to the signal output terminal 305 also changes.

[0100] However, when a variable attenuation circuit is realized with, for example, a Si substrate here, the signal between the back gate of the MOSFET 111 for signal attenuation and the substrate is low due to the low substrate resistance. Leaks to the board and the attenuation determined by the ON resistance of MOSFET 311 for signal attenuation cannot be obtained, and linearity cannot be ensured. In order to eliminate this effect, for example, the MOSFET 311 is manufactured in a triple-well structure, and a high-resistance resistor is inserted between the back gate of the MOSFET 311 and the substrate to block the signal leakage path. And the linearity is ensured.

[0101] In addition, this variable attenuation circuit has improved noise characteristics by adding a capacitor 303.

[0102] Threshold! /, And the gate bias circuit section 302 that performs value voltage compensation is generally composed of a resistor and a transistor. Therefore, noise generated by these resistors and transistors enters through the gate of the MOSFET 311 for signal attenuation, and is applied to the high-frequency signal that enters from the signal input terminal 304, deteriorating the noise characteristics. For example, the reception band of the GSM communication system The noise and other requirements are not met. By adding the capacitor 303, the noise generated in the gate bias circuit 302 can be cut off by the filter effect of the capacitor and the resistance, and the noise characteristics can be improved in any state of the continuously changing variable attenuation circuit.

[0103] As described above, by adding the threshold voltage compensation gate bias circuit section 302, the capacitor 303, and the resistor 325 added to the back gate to the variable attenuation circuit having the MOSFET 311 for attenuation control, the manufacturing process 'It is possible to correct the threshold variation of the signal attenuation MOSFET 311 due to variations in temperature, and to eliminate signal leakage in the signal attenuation MOSFET 311 in any attenuation state, improving the linearity. did it. Furthermore, noise generated in the gate bias circuit section 302 that performs threshold voltage compensation can be reduced, and noise characteristics can be improved. As a result, a variable attenuation circuit compatible with multi-band and multi-communication systems can be realized with the Si process, making it possible to make a single chip with other wireless circuit blocks.

Note that only one of or two of the gate bias circuit 302, the capacitor 303, and the resistor 325 may be connected. The MOSFET may be a P-channel MOSFET. In addition, even if it is not a triple wel structure, it is sufficient if the same effect can be exhibited.

[0105] (Example 3)

Example 3 of the present invention is a variable attenuation circuit (integrated circuit) corresponding to the first, second, third, fourth, and fifth points of the problem. This will be described below with reference to FIG.

The variable attenuation circuit according to the third embodiment of the present invention shown in FIG. 4 is an attenuation circuit that attenuates a high-frequency signal input from the signal input terminal 404 and outputs it from the signal output terminal 405, and the attenuation amount is external. A variable attenuation circuit that can be controlled from an attenuation control terminal 406, which is a terminal, is assumed. In addition, this variable attenuation circuit is assumed to be fabricated on, for example, a Si semiconductor substrate.

Specifically, the variable attenuation circuit in the present invention has a signal attenuation MOSFET (signal attenuation element) 411 inserted in series between the signal input terminal 404 and the signal output terminal 405. It has an attenuation unit 400, an attenuation amount control circuit unit 401 that controls the ON resistance of the signal attenuation MOSFET 411, and a source bias circuit unit 402 that applies a bias to the source of the signal attenuation MOSFET 411. The high frequency signal is attenuated by an attenuation amount corresponding to the attenuation amount control signal generated by the amount control circuit unit 401.

In addition, in this variable attenuation circuit, a capacitor 403 is added between the gate of the signal attenuation MOSFET 411 and the ground terminal. The effect of this capacity 403 can be broadly divided into two points. First point Attenuation control circuit block Noise component force S generated in 401, prevention of mixing into high frequency signal line (line from signal input terminal 404 to signal output terminal 405) via gate of MOSFET 411 for signal attenuation It is. Second-point force S, high-attenuation state due to parasitic capacitance generated between drain gate and gate source of MOSFET411 for signal attenuation This is to prevent a high frequency signal from leaking between the signal input terminal 404 and the signal output terminal 405.

[0109] Further, the source bias circuit section 402 of this variable attenuating circuit creates a bias voltage by using the source bias generating MOSFET 417 having the same threshold voltage fluctuation / temperature characteristics as the signal attenuating MOSFET 411! As a result, the manufacturing process of the signal attenuating MOSFET 411 has an effect of correcting variations in threshold voltage due to temperature fluctuations.

In addition, the signal attenuating MOSFET 411 of the variable attenuating circuit has a triple well structure, and a resistor 424 having a high resistance value is additionally provided between the back gate portion and the substrate. The effect of the resistor 424 having the high resistance value is to prevent a signal from leaking to the substrate through the back gate.

[0111] This variable attenuation circuit includes a capacitor 425 and a switch 426 between the connection between the resistor 422 for supplying the source bias to the MOSFET 411 for signal attenuation and the resistor 423 for supplying the drain bias and the ground terminal. Naoki IJ circuit power S has been added. The effect of the capacitor 425 and the switch 426 is that a high-frequency signal is supplied in the signal input terminal 404 in a high attenuation state via a resistor inserted between the drain and source of the signal attenuation MOSFET 411 to supply the source bias and the drain bias. Is to prevent leakage to the signal output terminal 405. In other words, signal leakage is prevented by dividing the resistor and grounding at high frequency. Insert a switch to eliminate the signal leakage in the low attenuation state where the signal passes, so that the capacity is not visible in the low attenuation state.

[0112] Here, a method of controlling the switch 426 will be described. When the voltage Vc at the attenuation control terminal 406 is low, the switch 426 is turned on, and when the voltage Vc is high, the switch 426 is turned off. Since the voltage Vc changes continuously, the switch 426 accurately changes from an ON state to an OFF state rather than an ON or OFF operation (continuous ON / OFF operation). The switch 426 is an analog switch, mainly a MOSFET.

[0113] As a control circuit for the switch (MOSFET) 426, for example, the gate potential of the MOSFET is fixed and the source / drain terminal of the MOSFET is connected to the attenuation control terminal 406 through a resistor as described above. Performs continuous on / off operation. [0114] The circuit connection of the variable attenuation circuit will be specifically described below.

First, as a signal attenuating element, for example, an N-channel MOS FET having a triple-well structure is suitable. The signal attenuating MOSFET 411 is inserted in series in the signal path between the signal input terminal 404 and the signal output terminal 405 of the high-frequency variable attenuating circuit, and between the signal input terminal 404 and the signal attenuating MOSFET 411. The DC blocking capacitor 412 that blocks the DC component and passes only the high frequency component is inserted, and the DC blocking capacitor 413 is also inserted between the signal attenuation MOSFET 411 and the signal output terminal 405. Yes. Between the back gate portion of the MOSFET 411 for signal attenuation and the substrate, a resistor 424 having a high resistance value for blocking signal leakage is inserted! /.

Next, an attenuation control circuit unit 401 is connected to the gate of the signal attenuation MOSFET 411. The configuration of the attenuation control circuit unit 401 will be described. Attenuation control resistor 415 and attenuation control resistor 416 are connected in series, and the other terminal of attenuation control resistor 415 is connected to attenuation control terminal (Vc) 406 for attenuation control. The other terminal of resistor 416 is connected to the ground terminal. Between the connection between the attenuation control resistor 415 and the attenuation control resistor 416 and the gate of the signal attenuation MOSFET 411 is connected a resistor 414 having a high resistance value that blocks high frequency and allows only DC to pass. ing. Further, a capacitor 403 is added between the gate of the signal attenuation MOSFET 411 and the ground terminal.

The source bias circuit portion 402 connected to the source terminal of the signal attenuating MOSFET 411 will be described. The resistor 420 and the resistor 421 are connected in series, the other terminal of the resistor 420 is connected to the power supply voltage terminal (Vdd) 407, and the other terminal of the resistor 421 is connected to the ground terminal. The gate of the source bias generating MOSFET 417 is connected to the connection portion between the resistor 420 and the resistor 421, and this source bias generating MOSFET 417 has the same manufacturing process as the signal attenuating MOSFET 411, “temperature variation variation. A resistor 418 is connected between the drain of the source bias generating MOSFET 417 and the power supply voltage terminal 407, and a resistor 419 is connected between the source of the source bias generating MOSFET 417 and the ground terminal. In addition, a resistor 422 having a high resistance value that cuts off the high frequency and passes only DC is connected between the source of the source bias generating MOSFET 417 and the source of the signal attenuating MOSFET 411. A resistor 423 having a resistance value is connected between the source of the signal and the drain of the MOSFET 411 for signal attenuation. A series circuit of a capacitor 425 and a switch 426 is added between the connection between the resistor 422 that supplies the source bias to the MOSFE T411 for signal attenuation and the resistor 423 that supplies the drain bias and the ground terminal.

[0118] Fig. 10 is a diagram showing the variation of each voltage value with respect to the temperature of the variable attenuation circuit when the source bias circuit unit 402 as shown in Fig. 1 is used, and Fig. 11 shows the control voltage at that time. FIG. 6 is a diagram showing gain characteristics for the same. In Fig. 10, unlike Fig. 8, Vref is reduced as the temperature rises. As a result, Vg—Vref—Vth is always constant regardless of temperature fluctuations, whether the temperature increases and the threshold voltage Vth increases or the temperature decreases and the threshold voltage Vth decreases. As shown in Fig. 11, the same control characteristics can be drawn.

[0119] The circuit operation for realizing the variation correction as shown in Fig. 11 will be described using the variable attenuation circuit of Fig. 4 as V. The gate potential of the source bias generating MOSFET 417 in the source bias circuit section 402 in FIG. 4 is determined by resistance division between the resistor 420 and the resistor 421. Since the source bias generation MOSFET 417 has the characteristic that the threshold voltage increases as the temperature rises the same as the signal attenuation MOSFET 411, the threshold voltage increases as the temperature rises, while the gate potential increases. Since it is constant, the source potential decreases and the current flowing through the source bias generating MOSFET 417 decreases. As a result, the source bias potential of the signal attenuating MOSFET 411 is reduced, and correction of the threshold voltage fluctuation can be realized.

Next, the circuit operation for realizing the linear control characteristics will be described using the variable attenuation circuit in FIG. A continuous control voltage from 0 V to the power supply voltage potential is input to the attenuation control terminal (Vc) 406 of the attenuation control circuit unit 401 in FIG. This control voltage is divided by the attenuation control resistor 415 and the attenuation control resistor 416 and input to the gate of the signal attenuation MOSFET 411. The signal attenuating MOSFET 411 is used with a drain-source bias of 0 V. When the gate potential is 0 V, the ON resistance is the largest and the ON resistance gradually decreases as the gate potential increases. When the voltage is reached, the ON resistance is minimized. As the ON resistance changes, the attenuation of the passage characteristic from the signal input terminal 404 to the signal output terminal 405 also changes. In addition, any voltage can be controlled by dividing with resistors 415 and 416. Characteristics are feasible.

[0121] However, when a variable attenuation circuit is realized on a Si substrate, for example, the signal leaks due to the parasitic capacitance generated between the drain and gate and between the gate and source of the signal attenuation MOSF ET411, and the signal attenuation MOSFET 411 is turned on. The attenuation determined by resistance cannot be obtained, and linearity cannot be ensured. In order to eliminate the influence, a capacitor 403 is inserted between the gate of the signal attenuating MOSFET 411 and the ground terminal. By inserting the capacitor 403, the signal leakage path between the drain gate and the gate source of the signal attenuating MOS FET 411 is cut off to ensure linearity.

[0122] In addition, when a variable attenuation circuit is realized with the same Si substrate as described above, for example, the impedance between the back gate of the signal attenuation MOSFET 411 and the substrate is lowered due to the low substrate resistance. Through this part, the signal leaks to the board, and the attenuation determined by the ON resistance of the signal attenuation MOSF ET411 cannot be obtained, and linearity cannot be ensured. In order to eliminate the influence, for example, the signal attenuating MOSFET 411 is manufactured in a triple-well structure, and a resistor having a high resistance value is inserted between the back gate of the signal attenuating MOSFET 411 and the substrate. The path through which the signal leaks is blocked to ensure linearity.

Further, for example, when a variable attenuation circuit is realized using a MOSFET on a Si substrate, it is necessary to apply the same potential to the source and drain of the signal attenuation MOSFET 411. At that time, the voltage generated by the source bias circuit 402 is supplied to the source via the source bias generating resistor 422 having a high resistance value, and is supplied to the drain via the drain bias generating resistor 423 having a high resistance value. The method is generally used. In this case, in a high attenuation state, a signal leaks from the drain to the source via the resistor, and there is a problem that the attenuation amount cannot be as high as the attenuation characteristic when the MOSFE T411 for signal attenuation is cut off. In order to eliminate this effect, for example, a series circuit of a capacitor 425 and a switch 426 is connected between the connection between the source bias generating resistor 422 and the drain bias generating resistor 423 of the signal attenuating MOSFET 411 and the ground terminal. In the high isolation state, when the switch 426 is turned on, a signal leaks from the input terminal 404 to the output terminal 405 via the source bias generating resistor 422 and the drain bias generating resistor 423. It can cut off and improve the attenuation characteristics at the time of high isolation. In the passing state, switch 426 is set to OFF. This prevents the signal from leaking when passing due to the influence of the capacity 425.

FIG. 14A shows the results (attenuation control characteristics) of circuit simulation using the variable attenuation circuit of FIGS. 4 and 2. In the figure, symbol E1 indicates the characteristics of the conventional circuit (Fig. 2), and symbol E2 indicates the characteristics of the circuit of the present invention (Fig. 4). There is no difference in the maximum output level (Vc = l.8V) between the conventional circuit and the circuit of the present invention.However, at Vc = l.5V or less, the conventional circuit has a large amount of signal leakage and sufficient attenuation. Conversely, in the circuit of the present invention to which Example 3 is applied, the capacitor 403 added to the gate of the signal attenuating MOSFET 411, the resistor 424 added to the back gate of the signal attenuating MOSFET 411, and the source bias circuit 402 are added. By adding a series circuit consisting of a capacitance 425 and a switch 426, an attenuation close to the original performance of the signal attenuation MOSFET 411 was obtained, and the attenuation control characteristics were greatly improved.

[0125] In addition, the variable attenuation circuit has improved noise characteristics due to the addition of the capacitor 403. The attenuation amount control circuit unit 401 is usually composed of a resistor. Therefore, noise generated by this resistor enters through the gate of the MOSFET 411 for signal attenuation and is applied to the high-frequency signal that enters from the signal input terminal 404 to deteriorate the noise characteristics, for example, GSM communication system reception band noise, etc. No longer meet the requirements.

However, the noise generated in the attenuation control circuit unit 401 is reduced by adding the capacitor 403.

Noise characteristics can be improved in any state of the variable attenuation circuit which is blocked by the filter effect of 403 and resistor 414 and continuously changes. Fig. 14B shows the results (noise characteristics) of a circuit simulation using the variable attenuation circuit of Figs. 4 and 2. In the figure, symbol F1 indicates the characteristics of the conventional circuit (Fig. 2), and symbol F2 indicates the characteristics of the circuit of the present invention (Fig. 4). In Example 3, the addition of the capacitor 403 greatly improved the noise characteristics.

As described above, the variable bias circuit having the signal attenuating MOSFET 411 includes the source bias circuit 402, the capacitor 403, the resistor 424 added to the back gate, the capacitor 425 added to the source bias circuit, and the switch 426. By adding a series circuit, it becomes possible to compensate for variations in the threshold value of the MOSFET 411 for signal attenuation due to variations in temperature variations, and the signal attenuation MOSFET 411 and other resistors can be compensated for in any attenuation state. Signal leakage could be eliminated and linearity could be improved. Furthermore, the noise generated by the attenuation control circuit unit 401 can be reduced, and the noise characteristics can be improved. As a result, a variable attenuation circuit compatible with multi-band and multi-communication systems can be realized by the Si process, and it can be integrated into a single chip with other radio circuit blocks.

Note that the source bias circuit 402, the capacitor 403, and the resistor added to the back gate

It may be configured such that only one, only two, only three, or all of the series circuit 424 and the capacitance 425 and switch 426 added to the source bias circuit are connected. The MOSFET may be a P-channel MOSFET. Moreover, it is sufficient that the same effect can be exhibited even if the triple-well structure is not used. Alternatively, the source bias circuit additional capacitor 425 and the switch 425 in series may be provided with only the source bias circuit additional capacitor 425.

[Example 4]

A variable attenuation circuit (integrated circuit) according to Example 4 of the present invention will be described below with reference to FIG.

FIG. 6 shows a variable attenuation circuit using at least one of the variable attenuation circuit of FIG. 1, the variable attenuation circuit of FIG. 3, or the variable attenuation circuit of FIG. The circuit configuration and operating principle will be described.

[0131] In general, a variable attenuation circuit using GaAs or the like is often fabricated independently on a substrate. In that case, both input and output must be terminated at 50 Ω at high frequencies. Configure the circuit. In FIG. 16, reference numerals 1601 to 1604 denote variable resistors (variable attenuation circuits), respectively. Vc is the attenuation control terminal, Vref;! To Vref4 is the bias terminal, IN is the input terminal, and OUT is the output terminal. In this circuit configuration, the variable resistance part inserted in parallel (shunt) is terminated at 50 Ω for both input and output from the high attenuation state to the low attenuation state. However, when fabricated on a Si substrate, both input and output need not be terminated at 50 Ω. For example, if the input side is a digital circuit such as an inverter, the input impedance of the variable attenuation circuit is low. In addition, by inserting a variable resistor in the first stage, the input impedance of the variable attenuation circuit is lowered, and a large driving force is required for the preceding circuit. In such a case, as shown in Figure 5. A ladder-type variable attenuation circuit is desirable. In FIG. 5, 501 and 502 are variable attenuation circuits as shown in FIG. 1 or FIG. 4, 503 and 504 are variable attenuation circuits as shown in FIG. 3, 505 is a signal input terminal, 506 is a signal output terminal, 507 Is an attenuation control terminal.

[0132] By inserting a variable resistor in the first stage, the effect of inserting the resistance is obtained, improving the attenuation characteristics, and constantly increasing the input impedance of the variable attenuation circuit. As a result, the driving power of the previous circuit can be reduced, and low power consumption can be realized.

FIG. 6 shows a variable attenuation circuit using the variable attenuation circuit of FIGS. 4 and 3 in the circuit configuration of FIG.

In FIG. 6, the high-frequency signal that has entered from the signal input terminal 601 is attenuated by the attenuation operation units 611, 612, 613, and 614 and is output from the signal output terminal 602. Here, the attenuation operation units 611, 612, 613, and 614 are a combination of the signal attenuation unit and the attenuation amount control circuit unit in FIG. 4 or FIG.

The attenuation is continuously controlled from the high attenuation state to the low attenuation state by the attenuation amount control terminal (Vc) 603. In this variable attenuation circuit, a common source bias generation circuit 615 shown in FIG. 4 is added as a threshold voltage variation correction circuit for the MOSFET for signal attenuation of the attenuation operation unit 611 and the attenuation operation unit 613. The gate bias generation circuit 616 shown in Fig. 3 was added as a correction circuit for the threshold voltage variation of the 612 signal attenuating MO SFET, and the variation of the threshold voltage of the signal attenuating MOSFET in the attenuation unit 614 was corrected. As a circuit, a gate bias generation circuit 617 shown in FIG. 3 is added. In addition, a capacitor is added between the gate of each signal attenuation MOSFET and the ground terminal to ensure linearity and improve noise characteristics. Each MOSFET has a triple-well structure, and a resistor having a high resistance value is inserted between the back gate and the substrate to reduce signal leakage to the substrate. Attenuation operation unit 611 and attenuation operation unit 613 signals A series circuit of a capacitor and a switch is inserted between the connection between the source bias generation resistor and drain bias generation resistor of the attenuation MOSFET and the ground terminal. Yes.

[0135] Here, the series circuit force of the capacitors and MOSFETs constituting the damping operation units 12 and 14 plays the role of the above capacitance and switch.

15A and 15B are circuit simulations using the variable attenuation circuit of FIG. It is the result of having gone. Fig. 15A shows the attenuation control characteristic, and Fig. 15B shows the noise characteristic. In FIG. 15A, symbol G1 indicates the characteristics of the conventional circuit (for example, the circuit of FIG. 2), and symbol G2 indicates the characteristics of the circuit of the present invention (FIG. 4). In FIG. 15B, symbol HI indicates the characteristics of the conventional circuit (for example, the circuit of FIG. 2), and symbol H2 indicates the characteristics of the circuit of the present invention (FIG. 6). Capacitance added to the gate, resistance added to the back gate, capacitance added to the source bias circuit and the series circuit of the switch, the linearity is greatly improved, the series (series) signal attenuation unit, By connecting two stages of parallel (shunt) signal attenuators alternately, the attenuation control characteristics shown in Fig. 15A were realized, and a variable attenuation range of 50 dB or more was achieved in both the 800 MHz band and 2 GHz band. From Fig. 15B, it can be seen that the noise characteristics have also been greatly improved. As a result, it was possible to produce a variable attenuation circuit with excellent variation characteristics, linearity, and noise characteristics.

In the variable attenuation circuit of FIG. 6, at least one of the capacitances added between the gate of each signal attenuation MOSFET and the ground terminal, or a high between the back gate and the substrate. It is added to at least one of the resistors having the resistance value, at least one of the threshold voltage variation correction circuits of the signal attenuation MOSFET, or the source bias generating resistor and the drain bias generating resistor. As long as at least one of the capacities is added, all need not be connected. In addition, the connection of the parallel (shunt) signal attenuator and the series (series) signal attenuator does not have to be in this order, and any number of stages may be used. The MOSFET may be a P-channel MOSFET. Moreover, it is sufficient that the same effect can be exhibited even if the triple-luel structure is not used.

[Example 5]

Hereinafter, an integrated circuit according to Embodiment 5 of the present invention will be described with reference to FIG.

FIG. 7 is a block diagram showing an example of a high-frequency radio transmission circuit system (apparatus) using the variable attenuation circuit of FIG. 1, FIG. 3, FIG. 4, or FIG. The circuit configuration and operating principle will be described.

[0140] As shown in Fig. 7, this high-frequency wireless transmission circuit system divides the oscillation signal of an oscillator (VCO) 701 by a divider 702, and a buffer (Buffer) composed of an inverter or the like. ) After passing through 703, the gain is controlled by variable attenuation circuit (Variable Attenuator) 704 The signal is attenuated, amplified by a driver amplifier (Driver) 705, further amplified by a high frequency amplifier (PA) 706, and transmitted from an antenna 707.

[0141] By applying the present invention to the variable attenuation circuit 704 of the high-frequency wireless transmission circuit system in FIG. 7, even when the variable attenuation circuit is constructed on the same Si semiconductor substrate as other circuit blocks, the variation characteristics A variable attenuation circuit with excellent linearity, isolation characteristics, and noise characteristics can be realized, and a system with good pass characteristics can be obtained.

[0142] The configuration example of the high-frequency wireless transmission circuit system is not limited to the above, and a wireless transmission device and a wireless transmission device each including at least one variable attenuation circuit, at least one oscillator, and at least one amplifier. Any wireless transmission circuit system having an antenna connected to and capable of transmitting and receiving at least one radio frequency may be used.

[0143] According to the fifth embodiment, the same effects as those of the above-described embodiments can be obtained.

Industrial applicability

[0144] The present invention is useful for attenuation of high-frequency signals in various wireless communication devices.

Claims

The scope of the claims

[1] A signal attenuating unit having a signal attenuating element inserted in series in a signal path between the signal input unit and the signal output unit;

An attenuation amount control circuit unit that applies an attenuation amount control signal to the signal attenuation element; a bias circuit unit that applies a bias to the signal attenuation element;

A variable attenuation circuit comprising a capacitor connected between a connection portion between the signal attenuation element and the attenuation amount control circuit portion and a ground terminal.

[2] The signal attenuating element is an FET, the attenuation control circuit unit applies an attenuation control signal to the gate terminal of the FET to control the ON resistance of the FET, and the bias circuit unit is the FET The variable attenuation circuit according to claim 1, wherein a bias is applied to a source terminal, and the capacitor is connected between a gate terminal of the FET and the ground terminal.

[3] A signal attenuating unit having a signal attenuating FET inserted in series in the signal path between the signal input unit and the signal output unit;

An attenuation control circuit unit that applies an attenuation control signal to the gate terminal of the signal attenuation FET to control the ON resistance of the signal attenuation FET;

And a bias circuit unit that applies a bias to a source terminal of the signal attenuation FET, wherein the bias circuit unit compensates for variation in threshold voltage of the signal attenuation FET.

[4] A signal attenuating unit having a signal attenuating FET inserted in series in the signal path between the signal input unit and the signal output unit,

A variable attenuation circuit comprising: a bias circuit unit that applies a bias to a source terminal of the signal attenuation FET; and a resistor connected between a back gate unit of the signal attenuation FET and a substrate.

[5] A signal attenuation unit having a signal attenuation FET inserted in series in the signal path between the signal input unit and the signal output unit,

Applying an attenuation control signal to the gate terminal of the signal attenuating FET, the signal attenuating F Attenuation control circuit that controls the ON resistance of the ET,

A variable attenuation circuit comprising: a bias circuit section that applies a bias to a source terminal of the signal attenuation FET; and a capacitor or a capacitor and a switch connected between the bias circuit section and a ground terminal.

[6] A FET is inserted in the signal path between the signal input unit and the signal output unit, and the signal applied to the gate terminal of this FET controls the attenuation of the signal applied to the signal input unit. A signal attenuating unit for output by controlling,

An attenuation control circuit unit that applies a signal to the gate terminal to vary the ON resistance value of the FET;

A first capacitor element connected between the other end of the resistance element having one end connected to the source terminal of the FET and the ground terminal, and a DC circuit for applying a DC voltage through the resistance element; and a backside of the FET A variable attenuation circuit comprising: a resistor connected between a gate portion and the ground terminal; and a second capacitor element connected between the gate terminal and the ground terminal.

[7] A signal attenuating unit having a signal attenuating element inserted between the signal path between the signal input unit and the signal output unit and the ground terminal;

A variable attenuation circuit including a capacitor connected between a connection portion between the signal attenuating element and the bias circuit portion and the ground terminal.

[8] The signal attenuating element is an FET, and the attenuation control circuit unit applies an attenuation control signal to the drain terminal of the FET to control the ON resistance of the FET, and the bias circuit unit 8. The variable attenuation circuit according to claim 7, wherein a bias is applied to a gate terminal of the FET, and the capacitor is connected between the gate terminal of the FET and the ground terminal.

[9] A signal attenuator having a signal attenuating FET inserted between the signal path between the signal input unit and the signal output unit and the ground terminal,

An attenuation control circuit unit that provides an attenuation control signal to the drain terminal of the signal attenuation FET to control the ON resistance of the signal attenuation FET; And a bias circuit unit that applies a bias to the gate terminal of the signal attenuation FET, wherein the bias circuit unit compensates for variations in threshold voltage of the signal attenuation FET.

[10] A signal attenuating unit having a signal attenuating FET inserted between the signal path between the signal input unit and the signal output unit and the ground terminal,

Applying an attenuation control signal to the drain terminal of the signal attenuating FET

Attenuation control circuit that controls the ON resistance of the FET,

A variable attenuation circuit comprising: a bias circuit section that applies a bias to the gate terminal of the signal attenuation FET; and a resistor connected between the back gate section of the signal attenuation FET and the substrate.

[11] The first capacitive element is configured such that a first capacitive element and a current path terminal pair of FET are inserted and connected in series between the signal path between the signal input unit and the signal output unit and the AC ground. And a signal attenuating unit for controlling and outputting the attenuation amount of the signal applied to the signal input unit by a signal applied to a connection part between the FET and one end of the current path of the FET,

Attenuation control circuit unit that applies a signal to the one end of the FET to vary the ON resistance value of the FET,

A bias circuit section for applying a DC voltage to the gate terminal of the FET via a resistance element; and a resistor connected between the back gate section of the FET and the ground terminal; and the gate terminal and the ground terminal Variable attenuating circuit with a second capacitive element connected between

[12] a first signal attenuating unit having a first signal attenuating element inserted in series in a signal path between the signal input unit and the signal output unit;

A first attenuation control circuit unit for supplying an attenuation control signal to the first signal attenuation element;

A first bias circuit for applying a bias to the first signal attenuating element; a connection between the first signal attenuating element and the first attenuation control circuit; and a ground terminal. With the first capacity made,

Inserted between the signal path between the signal input unit and the signal output unit and the ground terminal. A second signal attenuating unit having a second signal attenuating element,

A second attenuation control circuit unit for supplying the attenuation control signal to the second signal attenuation element;

A second bias circuit section for applying a bias to the second signal attenuating element; a connection section between the second signal attenuating element and the second bias circuit section; and a ground terminal. And a variable attenuation circuit having a second capacitance.

[13] The first signal attenuating element includes a first FET, and the first attenuation control circuit unit applies an attenuation control signal to the gate terminal of the first FET to provide the first FET. The first bias circuit unit applies a bias to the source terminal of the first FET, and the first capacitor is between the gate terminal of the first FET and the ground terminal. Connected to

The second signal attenuating element is a second FET, and the second attenuation control circuit unit applies an attenuation control signal to the drain terminal of the second FET to turn on the ON resistance of the second FET. The second bias circuit unit applies a bias to the gate terminal of the second FET, and the second capacitor is connected between the gate terminal of the second FET and the ground terminal. The variable attenuation circuit according to claim 12.

[14] a first signal attenuating unit having a first signal attenuating FET inserted in series in a signal path between the signal input unit and the signal output unit;

A first attenuation control circuit that controls an ON resistance of the first signal attenuation FET by applying an attenuation control signal to the gate terminal of the first signal attenuation FET;

A first bias circuit section for applying a bias to a source terminal of the first signal attenuating FET;

A second signal attenuating unit having a second signal attenuating FET inserted between a signal path between the signal input unit and the signal output unit and a ground terminal;

A second attenuation control circuit unit that provides an attenuation control signal to the drain terminal of the second signal attenuation FET to control the ON resistance of the second signal attenuation FET;

A second bias circuit section for applying a bias to the gate terminal of the second signal attenuating FET, The first bias circuit section includes a first bias FET for compensating for a threshold voltage of the first signal attenuating FET! /, A value voltage variation,

The variable bias circuit, wherein the second bias circuit section includes a second bias FET that compensates for a threshold voltage variation of the second signal attenuating FET.

[15] a first signal attenuating unit having a first signal attenuating FET inserted in series in a signal path between the signal input unit and the signal output unit;

A second bias circuit section for applying a bias to the gate terminal of the second signal attenuating FET;

A first resistor connected between the back gate portion of the first signal attenuating FET and the substrate;

A variable attenuation circuit comprising: a second resistor connected between a back gate portion of the second signal attenuation FET and the substrate.

[16] a first signal attenuating unit having a first signal attenuating FET inserted in series in a signal path between the signal input unit and the signal output unit;

A second signal attenuating unit having a second signal attenuating FET inserted between a signal path between the signal input unit and the signal output unit and a ground terminal; A second attenuation control circuit unit that provides an attenuation control signal to the drain terminal of the second signal attenuation FET to control the ON resistance of the second signal attenuation FET;

A variable attenuation circuit including a capacitor or a capacitor and a switch connected between the first bias circuit section and a ground terminal.

[17] A first resistor is connected between the back gate portion of the first signal attenuating FET and the ground terminal,

17. The variable attenuation circuit according to claim 16, wherein a second resistor is connected between the back gate portion of the second signal attenuation FET and the ground terminal.

[18] A wireless transmission device including at least one variable attenuation circuit according to claim 1, at least one high-frequency amplification circuit, and at least one oscillator, and is connected to the wireless transmission device to transmit a radio frequency. A high-frequency radio circuit system including an antenna to perform.

[19] A wireless transmission device comprising at least one variable attenuation circuit according to claim 3, at least one high-frequency amplification circuit, and at least one oscillator, and is connected to the wireless transmission device to transmit a radio frequency. A high-frequency radio circuit system including an antenna to perform.

[20] A wireless transmission device including at least one variable attenuation circuit according to claim 4, at least one high-frequency amplification circuit, and at least one oscillator, and is connected to the wireless transmission device to transmit a radio frequency. A high-frequency radio circuit system including an antenna to perform.

[21] A wireless transmission device including at least one variable attenuation circuit according to claim 5, at least one high-frequency amplification circuit, and at least one oscillator, and is connected to the wireless transmission device to transmit a radio frequency. A high-frequency radio circuit system including an antenna to perform.

[22] A wireless transmission device comprising at least one variable attenuation circuit according to claim 7, at least one high-frequency amplification circuit, and at least one oscillator, and connected to the wireless transmission device to transmit a radio frequency A high-frequency radio circuit system including an antenna to perform.

[23] A wireless transmission device including at least one variable attenuation circuit according to claim 9, at least one high-frequency amplification circuit, and at least one oscillator, and is connected to the wireless transmission device to transmit a radio frequency. A high-frequency radio circuit system including an antenna to perform.

[24] A wireless transmission device comprising at least one variable attenuation circuit according to claim 11, at least one high-frequency amplification circuit, and at least one oscillator; and a wireless frequency connected to the wireless transmission device. A high-frequency radio circuit system including an antenna for transmitting.

[25] A wireless transmission device comprising at least one variable attenuation circuit according to claim 12, at least one high-frequency amplification circuit, and at least one oscillator, and a wireless frequency connected to the wireless transmission device. A high-frequency radio circuit system including an antenna for transmitting.