WO2008023730A1 - Circuit intégré, dispositif électronique et procédé de mesure - Google Patents

Circuit intégré, dispositif électronique et procédé de mesure Download PDF

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Publication number
WO2008023730A1
WO2008023730A1 PCT/JP2007/066271 JP2007066271W WO2008023730A1 WO 2008023730 A1 WO2008023730 A1 WO 2008023730A1 JP 2007066271 W JP2007066271 W JP 2007066271W WO 2008023730 A1 WO2008023730 A1 WO 2008023730A1
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WIPO (PCT)
Prior art keywords
signal
threshold
external terminal
integrated circuit
potential
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PCT/JP2007/066271
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English (en)
Japanese (ja)
Inventor
Tomoyuki Inomoto
Masahiro Ishii
Takeshi Nakayama
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Panasonic Corporation
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Publication date
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Publication of WO2008023730A1 publication Critical patent/WO2008023730A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31932—Comparators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits

Definitions

  • Patent Document 1 discloses an apparatus for measuring signal waveforms at multiple observation points inside an integrated circuit without using a digital oscilloscope.
  • Patent Document 1 Japanese Patent Publication 2006-276010
  • the probe may not be connected to the target terminal because of the mounting density of each component on the circuit board.
  • the analog waveform of the signal may not be observed.
  • the oscilloscope mechanism may be mounted on the LSI itself, it is necessary to mount an A / D converter with a high sampling speed, which increases the circuit scale. It's not realistic.
  • an object of the present invention is to provide an integrated circuit that can measure the signal waveform of the external terminal without greatly increasing the circuit scale even if the probe of the oscilloscope cannot be connected.
  • the present invention provides an integrated circuit that performs a predetermined function, and a first threshold excess signal that indicates whether or not the potential of an external terminal exceeds a first threshold
  • the first comparison means for outputting and whether the potential of the external terminal exceeds the second threshold value Detects the time difference between the second comparison means for outputting the second threshold excess signal indicating the state of the signal, the timing when the content of the first threshold excess signal is switched, and the timing when the content of the second threshold excess signal is switched.
  • a difference detecting means for outputting the information indicating the time difference detected by the difference detecting means to the outside.
  • the predetermined function is a function required for an electronic device in which the integrated circuit is mounted.
  • an encoding function, an encoding function, a display The function corresponds to it.
  • the integrated circuit can output information on a time difference from the timing when the potential of the signal applied to the external terminal exceeds a certain threshold potential until it exceeds the next threshold potential. it can.
  • the information of the time difference in various threshold potential pairs is output from the integrated circuit, so that the estimated analog signal waveform can be observed on a monitor of an external device or the like.
  • the difference detection means a delay unit that delays a plurality of input signals by a predetermined time, a change unit that sequentially changes the number of delay elements through which the first threshold exceeded signal passes, It is changed by the changing unit, and it is determined whether or not the timing at which the contents of the first threshold value excess signal that has passed through the determined number of delay elements and the second threshold value excess signal match is the same.
  • a coincidence determination unit and a calculation unit that calculates the time difference based on the number of delay elements that have passed the first threshold value excess signal when it is determined that the coincidence determination unit has matched may be omitted.
  • the second threshold value is variable
  • the integrated circuit further includes a setting unit that sets the second threshold value in the second comparison unit, and a second threshold value that is sequentially set in the setting unit. And a control means for causing the output means to output a time difference calculated each time it is changed.
  • the integrated circuit can set the second threshold value to various threshold values, the timing at which the external terminal signal potential exceeds various threshold values and the external terminal signal potential exceeds the fixed threshold value. Since multiple timing differences can be obtained, the analog signal waveform at the external terminal can be plotted.
  • the integrated circuit further includes an instruction receiving unit that receives an instruction from an external device to detect timing at which of a rising edge and a falling edge
  • the difference detection unit includes: From the timing when the signal exceeding the first threshold exceeds the content indicating that the potential of the external terminal exceeds the first threshold, the content indicates that! / ,!
  • the signal exceeding the second threshold indicates that the potential of the external terminal exceeds the second threshold. It's better to detect the time difference until the timing when the content is switched to the content indicating! /, Na! /
  • the delay amount can be measured by designating whether the timing is aligned with the rising edge or the falling edge of the signal output from each comparison means.
  • the integrated circuit further includes receiving means connected to an external device and receiving a designation signal for designating an external terminal from the external device, and the control means receives the designation received by the receiving means.
  • An external terminal may be selected based on the signal, and the time difference related to the external terminal may be output to the output unit.
  • an external terminal for which an analog signal waveform is to be observed can be designated by an external device, the analog signal waveform of a signal applied to a desired external terminal of the integrated circuit can be observed.
  • the present invention may be an electronic device that is equipped with an integrated circuit according to the present invention.
  • the electronic device measuring the integrated circuit according to the present invention has a function of outputting data to the outside, the signal waveform of the signal applied to the external terminal of the mounted integrated circuit is changed to the electronic device. It can be observed with a monitor for observation without disassembling.
  • FIG. 1 is a functional block diagram showing a functional configuration of an integrated circuit according to the present invention.
  • FIG. 2 is a functional block diagram showing a functional configuration of a DLL unit 111.
  • FIG. 3 is a functional block diagram showing a functional configuration of fixed delay unit 201.
  • FIG. 4 is a diagram showing an example of the waveform of each signal output from fixed delay section 201.
  • FIG. 5 is a functional block diagram showing a functional configuration of variable delay section 202.
  • FIG. 7 shows a signal input to gate 601 and an output signal based on the input signal.
  • FIG. 8 is a diagram showing a signal input to gate 602 and an output signal based on the input signal.
  • FIG. 9 is a functional block diagram showing a functional configuration of a control unit 117. 10] A diagram showing the delay amount when the variable threshold potential is set to 0. IV.
  • FIG. 12 is a conceptual diagram of a data structure showing a delay amount stored in a memory 120.
  • FIG. 13 is a signal waveform diagram displayed on PC 140 based on the measured and output delay amount. 14] A flowchart showing the operation of the control unit 117 when measuring the potential.
  • FIG. 15 is a diagram showing one usage pattern of the present invention.
  • FIG. 1 is a functional block diagram showing a functional configuration of an LSI according to the present invention.
  • LSI100 is configured to execute functions required for electronic devices with LSI100 mounted, and to output data for estimating the signal waveform applied to external terminals to external devices.
  • LSI 100 includes external terminals 101 and 102, comparators 103 to; 106, selectors 107 and 108, DL section 111, control section 117, CPU 120, memory 120, and input / output terminals. It is comprised including 123.
  • the configuration shown here is only the configuration necessary for measuring the waveform of the signal applied to the external terminals 101, 102, and is the configuration for the function that the LSI 100 should fulfill! Show me!
  • the comparator 103 holds a predetermined fixed threshold potential.When the potential of the signal applied to the external terminal 101 exceeds the fixed threshold potential, the comparator 103 outputs a logical value H (High). It has a function of outputting a logical value L (Low) when the potential of the signal applied to the terminal 101 does not exceed the fixed threshold potential.
  • the fixed threshold potential is 0.8V
  • the comparator 105 holds a predetermined fixed threshold potential. When the potential of the signal applied to the external terminal 102 exceeds the fixed threshold potential, the comparator 105 sets the logical value H to the external terminal. It has a function of outputting a logical value L when the potential of the signal applied to 102 does not exceed the fixed threshold potential.
  • the fixed threshold potential is 0.8V.
  • the comparator 106 holds the variable threshold potential specified by the control unit 117. When the potential of the signal applied to the external terminal 102 exceeds the variable threshold potential, the comparator 106 sets the logical value H to the external terminal 102. It has a function to output a logical value L when the potential of the signal applied to the signal exceeds the fixed threshold potential.
  • the variable threshold potential is set by the control unit 117 via the signal line 116.
  • Corrected paper (parent shell U91) It has a function of outputting to the signal line 110 as a signal.
  • the DLL unit 111 delays the signal on the signal line 110 so that the rising edges or the falling edges of the signals output to the signal line 109 and the signal line 110 coincide with each other. It has a function of outputting to the signal line 112 a delay amount when the signal phases match, and a function of outputting to the signal line 113 a phase matching signal indicating that the signal phases match. Details will be described later with reference to FIG. Note that the phase usually refers to a periodic signal, but in this embodiment, it is simply described that the rising edges of the signals match or the falling edges of the signals match. To do.
  • the memory 120 has a function of storing a delay amount written by the control unit 117.
  • the I / F conversion adapter 130 is in charge of communication between the observation PC 140 and the control unit 117.
  • the control command output from the observation PC 140 based on the USB standard is converted into a 12C standard signal.
  • Observation PC 140 obtains from LSI interface 130 a function for outputting a command for designating an external terminal of LSI 100 for which a signal waveform is to be measured and a signal waveform of a signal applied to the external terminal. And a function of displaying a signal waveform diagram.
  • Figure 2 shows the functional configuration of DLL unit 111. It is a functional block diagram.
  • the DLL unit 111 includes a fixed delay unit 201, a variable delay unit 202, a phase comparison unit 203, a 7bit Up Down counter 204, and a phase match detection unit 205.
  • the fixed delay unit 201 delays the first threshold excess signal output from the selector 107 via the signal line 109 by a predetermined amount and outputs the delayed first threshold excess signal to the signal line 206, and the input signal And a function of outputting a signal for determining a rising edge and a falling edge.
  • the fixed delay unit 201 includes a gate 301, a gate 302, and 128 delay elements 300 ;! to 3128. Each delay element has a function of delaying the input signal by 20 pS (pico_Second).
  • the gate 301 performs a logical product of a signal obtained by inverting the first over-threshold signal after passing through the 128 delay elements and the signal applied to the signal line 109, and as a result, It has a function of outputting an up period determination signal to the signal line 210.
  • the rising period determination signal is used to determine the rising period of the signal applied to the signal line 206.
  • the gate 302 includes a signal obtained by passing the first threshold exceeding signal applied to the signal line 109 through 128 delay elements, and a signal obtained by inverting the first threshold exceeding signal applied to the signal line 109. And has a function of outputting a fall period determination signal as a result to the signal line 211.
  • the falling period determination signal is used to determine the falling period of the signal applied to the signal line 206.
  • FIG. 4 shows an example of the waveform of the signal output from fixed delay section 201.
  • the rising period determination signal applied to the line 210 is a pulse having a width of 1280 pS before and after the rising edge.
  • the rise of the delayed first threshold excess signal applied to the signal spring 206 is observed only during the period when the rising period judgment signal is H.
  • the falling period determination signal output to the signal line 211 is a panel having a width of 1280 pS before and after the falling edge of the signal line 206.
  • the fall of the signal applied to the signal line 206 is observed only during the period when the fall period determination signal of the signal line 211 becomes H! /.
  • the variable delay unit 202 has a function of outputting a signal obtained by delaying the second threshold excess signal input via the signal line 110 as instructed from the 7-bit UpD own counter 204 via the signal line 112. .
  • the selector 501 and 128 delay elements 500;! To 5128 are included.
  • Each delay element has a function of delaying the input signal by 20 pS.
  • a function of outputting to 207 Specifically, if the delay amount, which is a 7-bit signal applied to the signal line 112, is “7′h00”, the output of the delay element 5001 is selected and output to the signal line. If “7 ′ h01”, the output of the delay element 5002 is selected and output to the signal line.
  • Each delay element 500;! To 5128 has a function of outputting an input signal with a delay of 20 pS.
  • the phase comparison unit 203 selects one of the rising period determination signal and the falling period determination signal based on the edge selection signal applied to the signal line 114, and selects the signal power of the selected one. , The rising or falling edge of the delayed first threshold exceeding signal applied to the signal spring 206 rises quickly, or the rising or falling edge of the delayed second threshold exceeding signal applied to the signal line 207 is early. It has a function of judging whether it is slow or not, outputting an H pulse to the signal line 208 when it is judged as late, and outputting an H pulse to the signal line 209 when it is judged as early. Note that the phase comparison unit 203 selects the rising period determination signal when the edge selection signal indicates H, and selects the falling period determination signal when the edge selection signal indicates L.
  • the rank offer comparison 203 includes gates 601, 602, 606, and 607 and selectors 603 to 605.
  • the gate 601 receives the signal received via the signal line 206 and the signal received via the signal line 207. It has a function of taking a logical product with the inverted signal and outputting it.
  • FIG. 7 shows a waveform example of the signal applied to the signal line 206, a waveform example of the signal applied to the signal line 207, and a signal output from the gate 601 based on these signals. The waveform is shown. As can be seen from FIG. 7, when the signal applied to the signal line 206 is H and the signal force applied to the signal line 207, the gate 601 outputs a logical value H.
  • the selector 603 has a function of selecting and outputting either the signal output from the gate 601 or the signal output from the gate 602 based on the signal received via the signal line 114. . Specifically, when the edge selection signal applied to the signal line 114 is H, the signal from the gate 602 is selected and output, and the edge selection signal applied to the signal line 114 is L. The signal from the gate 601 is selected and output.
  • the selector 604 has a function of selecting and outputting either the signal output from the gate 601 or the signal output from the gate 602 based on the signal received via the signal line 114. . Specifically, when the edge selection signal applied to signal line 114 is H, the signal from gate 601 is selected and output, and the edge selection signal applied to signal line 114 is L Then, the signal from the gate 602 is selected and output.
  • the gate 606 has a function of taking a logical product of the signal output from the selector 603 and the signal output from the selector 605 and outputting the logical product to the signal line 208.
  • the gate 607 has a function of calculating a logical product of the signal output from the selector 604 and the signal output from the selector 605 and outputting the logical product to the signal line 209.
  • the CPU-IF 901 has a function of executing communication with the CPU 120 in the LSI 100 via the signal line 118 and the internal bus 119, and a function of outputting data held by each unit in the control unit 117; It has a function of outputting data from the CPU 120 to each unit in the control unit 117.
  • the D / A converter 905 has a function of outputting the threshold potential set in the comparators 103 and 105 received from the threshold register 904 to the signal line 116. Specifically, when the value held by the threshold register 904 is “0x1”, it is 0.IV, when it is “0x2”, 0.2V, and the value of the threshold register 904 in increments of 0.1V. In response to this, a threshold potential is output to the signal line 116.
  • the memory I / F 906 has a function of writing the delay amount output from the sequencer 903 to a predetermined address in the memory 120 based on the value of the threshold register 904, and the delay amount data written in the memory 120 to the external IF IF 907. Has a function to output.
  • the external-IF907 is stored in the memory 120 output from the memory I / F 906 and the function of outputting various information output from the observation PC 140 to each part in the LSI 100 via the input / output terminal 123. And a function of outputting a delay amount to the signal line 123.
  • the information output from the observation PC 140 includes, for example, information indicating the power of aligning the signal at the rising edge or falling edge, and information indicating which external terminal the observation target is.
  • the input selection register 908 has a function of outputting to the signal line 115 an external terminal selection signal indicating which external terminal is observed based on an instruction acquired from the external IF 907.
  • the above is the configuration for observing the signal waveform of the external terminals constituting the LSI 100. Now, the data obtained from this using specific examples and the signal waveforms obtained from the obtained data will be described.
  • FIG. 10 is a diagram schematically showing an analog signal waveform of a signal applied to the external terminal and a signal applied to each signal line based on the analog signal waveform.
  • FIG. 10 shows the switching of the logical value of each signal when the threshold value of the comparator 104 is set to 0.1V.
  • the logical value of the signal line 110 changes from L to H.
  • the logical value of the signal line 109 changes from L to H.
  • the signal applied to the signal line 109 is passed through the delay element of the fixed delay unit 201 through 64 stages.
  • the signal spring 206 has a waveform of signal spring 206. As can be seen from the figure, the signal is passed through the 64 stage delay element. As a result, the logical value of the signal changes from L to H after 1280 pS.
  • the time T1 shown in Fig. 10 corresponds to 1280pS.
  • the signal applied to the signal line 207 is applied to the signal line 206 by the function of the variable delay unit 202! /, And the timing at which the logic line 202 of the signal is switched from L to H coincides. !
  • the number 80 of delay elements that have been passed through is stored in the memory 120 at an address where data is stored when the comparator 104 uses 0.1V as a threshold value.
  • FIG. Figure 11 an example when the threshold value of the comparator 104 is set to 0.2 V is shown in FIG. Figure 11
  • the logical value of the signal line 110 changes from L to H.
  • the logical value of the signal line 109 changes from L to H.
  • the signal applied to the signal line 109 is passed through the delay element of the fixed delay section 201 through 64 stages, and the signal spring 206 has a waveform. As can be seen from the figure, the signal is passed through the 64 stage delay element. As a result, the logical value of the signal has changed from L to H after 1280 pS.
  • the time T1 shown in Fig. 11 corresponds to 1280pS.
  • the signal applied to the signal line 207 is applied to the signal line 206 by the function of the variable delay unit 202! /, And the timing at which the logic line 202 of the signal is switched from L to H coincides. !
  • the value of 1560pS is the value of the signal applied to the external terminal from 0.1V because the signal output from the comparator set at the threshold of 0.8V was intentionally passed through the 64 stage delay element. It is not the time required to reach 0.8V.
  • the difference between time T3 and time T1 corresponds to the time required for the potential of the signal applied to the external terminal to rise from 0.4V to 0.8V.
  • the number 78 of delay elements that have been passed through is stored in the memory 120 at an address for storing data when the comparator 104 uses 0.2V as a threshold value.
  • FIG. 12 is a diagram showing a configuration example of data stored in the memory 120.
  • An address for storing a delay amount is determined in advance according to a threshold value set in the comparator. For example, the address In 0x1, the amount of delay when the threshold value is set to 0.4 is stored. In this case, the number of delay elements 80 through which the signal has passed in order to match the signal is stored here. .
  • Address 0x2 stores 78 delay elements as the amount of delay when the threshold is 0.2V.
  • the delay amount obtained by 17 measurements from convenience IV to 1.8V is observed via the I / F conversion adapter 130 from the external-IF907 via the input / output terminal 123. Is output to PC140.
  • the observation PC 140 acquires the information shown in FIG.
  • the observation PC 140 can calculate the time required to rise from a certain potential to a certain potential by taking the difference in the number of delay elements between the thresholds. In other words, when 0.IV is used as a reference, the time difference is calculated such that the time required for the signal potential to rise from 0.1V to 0.2V, the time required for the signal potential to rise from 0.1V to 0.3V, and so on. it can.
  • Figure 13 shows an example of an analog waveform that can be observed by the observation PC 140 based on the time difference thus calculated.
  • Figure 13 shows external terminals that can be observed with an actual observation PC140. It is a figure which shows the prediction waveform of the signal applied to 01.
  • FIG. 13 since the time required to reach each threshold potential set in the comparator 103 can be calculated, the time at each threshold potential is plotted as shown in FIG. Then, an analog signal waveform as shown by the dotted line in FIG. 13 can be obtained.
  • FIG. 1 shows the operation for automatically measuring the delay amount at each threshold value from 0.1 V to 1.8 V and outputting the measured delay amount from the LSI 100 to the observation PC 140 according to the CPU 120.
  • the operation for observing the signal waveform of external terminal 110 will be described.
  • the phase shall be matched to the rising edge.
  • “0x1” is held in the threshold register 904 of the control unit 117 based on the CPU 120 force and the instruction.
  • the held value is output to the D / A converter 905, and the D / A converter 905 converts the received value “0x1” into 0.IV and outputs it to the signal line 116.
  • the comparator 104 that has received the threshold value of 0.4 via the signal line 116 holds the threshold potential as 0.1 V (step S141).
  • LSI 100 measures the delay amount based on the threshold potential set in comparator 104 (step S143). Specifically, when the threshold potential is set to 0.1 V, the comparator 104 outputs the signal that has been output so far at the timing when the potential of the signal applied to the external terminal 101 exceeds 0.4. Change from 1 to H and output the first threshold exceeded signal. In addition, the comparator 103 also outputs a signal that exceeds the second threshold by changing the signal L applied to the external terminal 101 from L to H when the potential of the signal applied to the external terminal 101 exceeds 0.8V.
  • the selector 107 selects the signal from the comparator 103, and the selector 108 Selects and outputs the signal from the comparator 104.
  • the DLL unit 111 detects the timing difference between the rising edges of the signal lines 109 and 110. That is, in the DLL unit 111, the signal potential of the external terminal 101 of the signal obtained by delaying the signal applied to the signal line 109 by 64 delay elements (1280 pS) by the fixed delay unit 201 is 0. The signal so that the rising edge, which is the timing exceeding 8V, matches the rising edge, which is the timing when the signal potential of the external terminal 101 of the signal applied to the signal line 110 exceeds 0.1V. The signal applied to the line 110 is passed through the delay element of the variable delay unit 202. Then, the DLL unit 111 outputs the delay amount at the coincidence timing, that is, the number of the passed delay elements to the sequencer 903 of the control unit 117. When the sequencer 903 receives the phase match detection signal from the signal line 113 and receives the delay amount from the signal line 112, the sequencer 903 writes the delay amount at that time in the memory 120 based on the information held in the threshold register 904.
  • the control unit 117 detects whether or not “0x12” indicating the value power threshold 1.8V held by the threshold register 904 is reached (step S 145).
  • the CPU 120 stores the value in the threshold value register 904. Hold and hold the value obtained by adding 0. IV to the value! (Step S1 46). For example, if the value held in the threshold register 904 is “0x1” indicating 0.IV, it is set to “0x2” indicating 0.2V. Then, the process returns to step S143, and the subsequent processing is executed, and the delay amount up to 1.8V is measured.
  • the control unit 117 sets each threshold value stored in the memory 120.
  • the number indicating the delay element is converted into a difference from the value when the threshold value of the comparator 104 is set to 0. IV. Since the delay amount for one delay element is 20 pS, it is converted to a value obtained by multiplying the number of delay elements obtained by conversion by 20. Then, the control unit 117 outputs the data converted to the time required for each threshold potential from 0. IV to the obtained value obtained by the conversion to the I / F conversion adapter 130 via the external terminal 121 ( Step S147).
  • the I / F conversion adapter 130 converts the data format and outputs it to the observation PC 140. Then, the observation PC 140 can measure an analog signal waveform applied to the external terminal 101 in a graph as shown in FIG.
  • the LSI 100 needs to receive the same waveform signal 18 times from 0.1 V to 1.8 V at the external terminal 101.
  • the signal applied to the external terminal by the LSI100 has two threshold potentials.
  • the analog signal waveform applied to the external terminal of the LSI100 can be estimated by a PC monitor etc. Is realized.
  • FIG. 15 shows a device on which the LSI 100 is mounted and its usage pattern.
  • the mobile phone 150 is connected to the observation PC 140 via the connector 151.
  • the observation PC 140 is equivalent to that shown in the first embodiment, and the mobile phone 150 is equipped with the LSI 100 shown in the first embodiment.
  • the connector 151 is connected to the input / output terminal 123 inside the mobile phone 150.
  • mobile phone 150 Since mobile phone 150 has LS 1100 mounted inside itself even after product assembly of mobile phone 150, the analog waveform of the signal applied to the external terminal fs element of LSI 100 is used. Mobile phone 150 can be observed without disassembling.
  • the present invention may be a method of measuring and outputting a delay amount for estimating the signal waveform of the external terminal of the LSI shown in the above embodiment.
  • it may be a computer program executed by a computer to execute the method and measure a delay amount between each threshold potential of a signal applied to an external terminal! /.
  • the power of using the comparators 103 and 105 as a comparator with a fixed threshold value it is necessary to increase or decrease the signal applied to the external terminal from a certain potential to a certain potential. Since it is only necessary to measure time, the comparators 103 and 105 may be comparators with variable thresholds. For example, when measuring the signal waveform at the external terminal 101, the threshold value of the comparator 103 is set to 0.1 V, and the threshold value of the comparator 104 is set. Set the value to 0.2V, measure the delay amount, then repeat the measurement of the delay amount by setting the comparator 103 threshold value to 0.2V and the comparator 104 threshold value to 0.3V. You may take a technique to solve.
  • a mobile phone is shown as an example of a device on which an LSI is mounted.
  • any device may be used as long as it is mounted on an LSI and has a mechanism for outputting a signal to the outside.
  • it may be a PDA (Personal Digital Assistance) or a DVD (Digital Versatile Disc) player.
  • data related to the amount of delay is not limited to wire transmission, and if the device equipped with LSI has a wireless transmission function, it can be transmitted wirelessly! /.
  • the fixed threshold potential is set to 0.8V
  • the variable threshold potential is set to a potential between 0.4V and 1.8V. Since the potential of the signal applied to the external terminal differs depending on the device on which the LSI is mounted, the threshold potential is determined by the device on which the LSI is mounted. For example, the maximum potential of the signal applied to the LSI is 3V. In this case, the fixed threshold potential may be set to 1.5V, and the variable threshold potential may be set from 0. IV to 2.9V.

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Abstract

L'invention concerne la mesure d'une forme d'onde de signal d'un terminal externe d'un circuit intégré auquel une sonde d'un oscilloscope ne peut pas être connectée. Le circuit intégré est muni d'un comparateur, qui est connecté au terminal externe et présente un seuil fixe, et un comparateur de variables de seuil. Le circuit intégré mesure une différentielle entre des chronométrages, les comparateurs émettant des signaux indiquant que les potentiels des terminaux externes dépassent la valeur seuil. Chaque chronométrage est détecté en changeant en série les valeurs seuil des comparateurs de variables de seuil et une forme d'onde de signal est estimée à partir de chaque chronométrage.
PCT/JP2007/066271 2006-08-22 2007-08-22 Circuit intégré, dispositif électronique et procédé de mesure WO2008023730A1 (fr)

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JP2006224859 2006-08-22

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JP2000314750A (ja) * 1999-04-20 2000-11-14 Tektronix Inc デジタル・オシロスコープの動作制御方法

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