WO2007141847A1 - Display device - Google Patents
Display device Download PDFInfo
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- WO2007141847A1 WO2007141847A1 PCT/JP2006/311381 JP2006311381W WO2007141847A1 WO 2007141847 A1 WO2007141847 A1 WO 2007141847A1 JP 2006311381 W JP2006311381 W JP 2006311381W WO 2007141847 A1 WO2007141847 A1 WO 2007141847A1
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- WIPO (PCT)
- Prior art keywords
- electrode
- display
- units
- scan
- pulse
- Prior art date
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0439—Pixel structures
- G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Definitions
- the present invention relates to a large display device, and more particularly to electrical connection of a scanning pulse circuit of a large display device having a plurality of plasma 'tube' array forces each having a phosphor layer therein.
- Plasma display panels emit light by exciting phosphors with ultraviolet light of 147nm, which generates plasma discharge in a closed discharge space of a large number of vertical and horizontal small cells, and discharges plasma power. Let The cell space is formed between two stacked glass sheets.
- a plasma 'tube' array PTA
- a phosphor layer is formed in an elongated glass' tube or a support member on which the phosphor layer is formed is inserted to form a large number of cell spaces in the tube. .
- a large display screen of 6 m ⁇ 3 m can be formed.
- a sustain voltage pulse for the X electrode is printed from the X electrode driver device, and a scan driver for the Y electrode driver device from the sustain voltage pulse circuit for the Y electrode of the Y electrode driver device.
- a sustain voltage pulse for the Y electrode is applied through the circuit.
- Patent Document 1 Japanese Unexamined Patent Application Publication No. 2004-178854 (Patent Document 1) describes an arc tube array type display device.
- the arc tube array type display device includes an arc tube array that constitutes a display screen, and supports the arc tube array from the display surface side and the back side, and a number of electrodes for applying voltage to the arc tube. Supports formed in stripes on the array facing surface, terminal electrode lead-out portions provided on the support outside the display area of the display screen, and relay electrode lead-out portions provided on the support in the display area of the display screen And a first driver for applying a voltage to the terminal electrode lead-out portion and a second driver for applying a voltage to the relay electrode lead-out portion. Accordingly, even a display device having a large screen size has an electrode structure that does not cause a voltage drop, thereby preventing uneven brightness of the display device.
- Patent Document 1 Japanese Patent Laid-Open No. 2004-178854 Disclosure of the invention
- the length of the display electrode increases as the size increases.
- Display electrode resistance, inductance, and z or capacitance components increase. If the inductance of the display electrode from the position where the pulse voltage is applied to the position of the cell is increased, the waveform and effective voltage value of the applied voltage pulse for address discharge and sustain discharge may be affected. If the rise delay time of the address voltage pulse is increased due to the distortion of the pulse waveform, the duration of the effective applied voltage pulse applied to the light emitting cell is shortened, so that the cell is likely to fail the sustain discharge.
- the resistance of the display electrode to the position of the cell far from the applied position force of the Nors voltage increases, the voltage drop increases and the difference in effective voltage between the cells increases, resulting in luminance variations between the cells. It becomes easy.
- the width or thickness of the display electrode is usually increased, but the light shielding rate of the display electrode is increased, and thus the luminous efficiency of the display device is increased. As a result, the display image quality may be lowered.
- the inventors have arranged a scanning circuit for a multi-unit plasma tube array and a large-sized display device having a plurality of juxtaposed multi-unit plasma tube arrays having a drive circuit. It has been recognized that designing the connection in an advantageous manner can greatly reduce the address discharge failure and the associated sustain discharge failure in each unit, thereby reducing the display brightness unevenness.
- An object of the present invention is to reduce luminance unevenness in a large display device composed of a plurality of units.
- Another object of the present invention is to reduce address discharge failures in a large display device composed of a plurality of units.
- Still another object of the present invention is to prevent a synchronization deviation of scan pulses of a plurality of scan drive circuits of a large display device composed of a plurality of units.
- the display device includes a phosphor layer formed therein, a discharge gas sealed therein, and a plurality of gas discharge tubes each having a plurality of light emitting points in the longitudinal direction.
- a plurality of pairs of display electrodes are arranged on the display surface side of the plurality of gas discharge tubes, and a plurality of signal electrodes are arranged on the back side of the plurality of gas discharge tubes.
- the plurality of pairs of display electrodes of the plurality of units are electrically connected to have a length corresponding to the plurality of units.
- the display device applies a scanning voltage to one display electrode of each of the plurality of pairs of display electrodes of the plurality of units in the first period, and displays one of the display electrodes in the second period.
- At least one scan driving circuit for applying a sustain voltage pulse to the electrodes, and in the second period, the other of the display electrode pairs of the plurality of pairs of display electrodes of the plurality of units.
- at least one sustain voltage circuit for applying a sustain voltage pulse potential to the display electrode.
- the single scan driver circuit is located at the boundary between two adjacent units in the unit! Then, a scanning voltage is applied to one of the display electrode pairs of the plurality of display electrodes, and a sustain voltage pulse is applied to the one display electrode.
- another scan drive circuit in the plurality of scan drive circuits includes a boundary between the other two adjacent units in the plurality of units.
- a scanning voltage is applied to one of the display electrode pairs of the plurality of display electrodes, and a sustain voltage pulse is applied to the one display electrode.
- the scanning voltage pulse of each of the one scanning driving circuit and the other scanning driving circuit has a period between adjacent scanning voltage pulses, in order to prevent synchronization with the other scanning voltage pulse. Have.
- the present invention it is possible to reduce luminance unevenness in a large display device composed of a plurality of units, to reduce address discharge failures, and to reduce a plurality of large display devices composed of a plurality of units. Therefore, it is possible to prevent the scan pulse from being out of synchronization in the scan drive circuit.
- FIG. 1 illustrates a schematic partial structure of a unit 300 of an array of plasma tubes or gas discharge tubes 11R, 11G and 11B, typically for a color display.
- the unit 300 of the plasma 'tube' array (PTA) consists of an array of transparent elongated color 'plasma' tubes 11R, 11G and 11B arranged in parallel to each other, a transparent front support sheet.
- X represents a sustain electrode or X electrode of the display electrode 2
- Y represents a scan electrode or Y electrode of the display electrode 2.
- R, G, and B indicate red, green, and blue emission colors of the phosphor.
- the support substrates 31 and 32 are made of, for example, flexible PET film or glass.
- Elongated plasma 'tubes 11R, 11G, and 1 IB capillaries 20 are made of transparent insulators, such as borosilicate glass, Pyrex®, soda glass, quartz glass or zerodur, typically
- the tube diameter is 2 mm or less, for example, the tube cross-sectional width is about lmm and the height is about 0.55 mm, the length is 300 mm or more, and the tube wall thickness is about 0.1 mm.
- Support members on which the phosphor layers 4 of red, green, and blue (R, G, and B) are respectively formed are inserted and arranged on the rear side of the plasma 'tubes 11R, 11G, and 1IB. Discharged gas is introduced and both ends are sealed. On the inner surfaces of the plasma tubes 11R, 11G, and 11B, an electron emission film 5 having MgO force is formed.
- the phosphor layers R, G, B typically have a thickness in the range of about 10 m to about 50 ⁇ m.
- the support member is made of an insulator such as borosilicate glass, Neurex (registered trademark), quartz glass, soda glass, lead glass, and the like as in the plasma tubes 11R, 11G, and 11B.
- a phosphor layer 4 is formed on the support member.
- the support member is an outer portion of the glass tube. After the phosphor paste is applied on the support member and baked to form the phosphor layer 4 on the support member, the support member is inserted into the glass tube. Can be arranged.
- various phosphor pastes known in the art can be used. Togashi.
- the electron emission film 5 generates electrons by collision with charged particles of the discharge gas.
- the phosphor layer 4 is excited by vacuum ultraviolet light generated by de-excitation of the discharge gas enclosed in the tube excited by applying a voltage to the display electrode pair 2, and generates visible light.
- FIG. 2A shows a front-side support substrate 31 on which a plurality of transparent display electrode pairs 2 are formed.
- FIG. 2B shows a back side support substrate 32 on which a plurality of signal electrodes 3 are formed.
- the signal electrode 3 is formed on the front surface, that is, the inner surface of the back side support substrate 32, and is provided along the longitudinal direction of the plasma tubes 11R, 11G, and 1IB.
- the pitch between the adjacent signal electrodes 3 is substantially the same as the width of each of the plasma tubes 11R, 11G, and 1IB, for example, lmm.
- the plurality of display electrode pairs 2 are formed on the back surface, that is, the inner surface of the front-side support substrate 31 in a well-known form, and are arranged in a direction perpendicular to the signal electrode 3.
- the width of the display electrode 2 is, for example, 0.75 mm, and the distance between the edges of each pair of display electrodes 2 is, for example, 0.4 mm.
- a distance serving as a non-discharge region or a non-discharge gap is secured between the display electrode pair 2 and the adjacent display electrode pair 2, and the distance is, for example, 1. lmm.
- the signal electrode 3 and the display electrode pair 2 are brought into close contact with the lower outer peripheral surface portion and the upper outer peripheral surface portion of the plasma tubes 11R, 11G, and 11B when the PTA unit 300 is assembled.
- an adhesive may be interposed between each electrode and the plasma tube surface to bond them.
- the intersection of the signal electrode 3 and the display electrode pair 2 is a unit light emitting region.
- one of the display electrode pairs 2 is used as the scan electrode Y, a selective discharge is generated at the intersection of the scan electrode Y and the signal electrode 3, and a light emitting region is selected.
- a display discharge is generated at the display electrode pair 2 and the phosphor layer emits light.
- the selective discharge is a counter discharge generated in the plasma tubes 11R, 11G, and 1IB between the scanning Y electrode and the signal electrode 3 facing each other in the vertical direction.
- Display discharge is generated in the plasma tubes 11R, 11G and 11B between a pair of display electrodes arranged in parallel on a plane. This is a surface discharge.
- the display electrode pair 2 and the signal electrode 3 can generate a discharge in the discharge gas inside the tube by applying a voltage.
- the electrode structure of plasma 'tubes 11R, 11G and 11B is a structure in which three electrodes are arranged in one light emitting part, and the display discharge is generated by display electrode pair 2.
- the display electrode 2 and the signal electrode 3 may have a structure in which display discharge is generated. That is, the display electrode pair 2 may be one, and the display electrode 2 may be used as a scanning electrode to generate a selective discharge and a display discharge (opposite discharge) between the display electrode 2 and the signal electrode 3. ⁇ .
- FIG. 3 shows a cross-sectional structure perpendicular to the longitudinal direction of the tubes of the plasma “tube” array 11 of the PTA unit 300.
- the plasma 'tubes 11R, 11G, and 1IB have phosphor layers 4R, 4G, and 4B formed on the inner surfaces of the back support members 6R, 6G, and 6B, and have a cross-sectional width of 1 Omm, cross-sectional height 0.55mm, tube wall thickness 0. lmm, and length lm to 3m capillary force.
- the red phosphor 4 R includes a yttria-based ((Y. Ga) BO: Eu) material
- the green phosphor 4G is zinc silicate.
- the blue phosphor 4B contains BAM (BaMgAl 2 O: Eu).
- a back-side support substrate 32 is bonded to the bottom surfaces of the plasma tubes 11R, 11G, and 11B via an adhesive layer 34.
- Signal electrodes 3R, 3G, and 3B are arranged on the bottom surfaces of the plasma tubes 11R, 11G, and 11B and on the top surface of the back support substrate 32.
- FIG. 4 shows the electrical characteristics of the X electrode driver circuit board 500, the Y electrode driver circuit 700, the address electrode driver circuit (AD) 46, and the driver control circuit 42 on the back of the PTA unit 300 of the normal display device 10. Indicate the ideal connection.
- FIG. 5 shows a sustain voltage pulse circuit (SST) 60 and a scan pulse circuit (SCN) 70 for the Y electrode in an ordinary Y electrode driver circuit 700 connected to the PTA unit 300, and an X electrode driver circuit.
- SST sustain voltage pulse circuit
- SCN scan pulse circuit
- Sustain voltage pulse circuit (SST) 50 is connected to X electrodes XI to Xn via switches. It includes a bias voltage source Vs and a ground potential GND connected to the X electrode XI ⁇ : Xn through the switch.
- the sustain voltage pulse circuit (SST) 60 includes a high voltage pulse voltage source Vs connected to the scan pulse circuit (SCN) 70 via the switch, and a ground potential connected to the scan pulse circuit 70 via the switch. Includes GND.
- Scanning pulse circuit (SCN) 70 couples pulse voltage source Vs and ground potential GND to Y electrodes Yl to Yn.
- the scan pulse circuit 70 further includes a bias voltage source Vsc connected to the ⁇ electrodes ⁇ 1 to ⁇ via the switch, and a scan pulse power source Vy connected to the Y electrodes Y1 to Yn via the switch. .
- n pairs of display electrodes 2 of PTA unit 300 are n pairs of display electrodes 2 of PTA unit 300.
- the X electrodes (XI, Yl) to (Xn, ⁇ ) are connected to the sustain voltage pulse circuit 50 for the X electrodes on the X electrode driver circuit board 500 via the flexible cable 500FC from the right side of the front support board 31.
- the left electrode of the front support substrate 31 is also connected to the scanning pulse circuit 70 on the high electrode circuit board 600 of the high electrode driver circuit 700 via the flexible cable 70FC.
- the sustain voltage pulse circuit 60 for the saddle electrode on the saddle electrode driver circuit 700 is connected to the scan pulse circuit 70 via a flexible cable.
- the m signal electrodes 3 Al to Am of the unit 300 are connected to the address driver circuit 46 through the flexible cable 46FC from the bottom side of the back support board 32.
- the X electrode driver circuit board 500 further includes a reset circuit (RST) 51.
- the Y high voltage circuit board 600 further includes a reset circuit (RST) 61.
- the driver control circuit 42 is connected to the X electrode driver circuit board 500, the Y electrode high voltage circuit board 600 of the Y electrode driver circuit 700, and the address' driver circuit 46.
- a power source (PS) 40 that supplies power to the circuits 42, 46, 500, and 700 is further provided.
- One picture is typically composed of one frame period.
- one frame is composed of two fields, and in progressive scanning, one frame is composed of one field. .
- 30 frames per second are required for video display using the normal television system. Therefore, in the display by this kind of gas discharge display device 10, binary light emission control is used.
- one field F is replaced with a set of q subfields SF.
- the field period Tf which is a field transfer period is divided into q subfield periods Tsf, and one subfield period Tsf is assigned to each subfield SF. Further, the subfield period Tsf is divided into a reset period TR for initialization, an address period TA for addressing, and a display period TS for light emission by sustain discharge.
- the length of the reset period TR and the address period TA is constant regardless of the weight, whereas the number of pulses in the display period TS is larger and the length of the display period TS is The greater the weight, the longer. In this case, the length of the subfield period Tsf is longer as the weight of the corresponding subfield SF is larger.
- FIG. 6 exemplifies a schematic drive sequence of output drive voltage waveforms of the X electrode driver circuit board 500, the Y electrode driver circuit 700, and the address' driver circuit 42 in the normal display device 10.
- the waveform shown is an example, and the amplitude, polarity, and timing can be changed in various ways.
- the order of reset period TR, address period TA, and sustain period TS is the same in q subfields SF, and the drive sequence is repeated for each subfield SF.
- a negative polarity pulse Prxl and a positive polarity pulse Prx2 are sequentially applied to all the display electrodes X, and a positive polarity pulse Pry is applied to all the display electrodes Y. 1 and negative polarity pulse Pry2 are applied in order.
- Pulses Prxl, P ryl and Pry2 are ramp waveforms or blunt pulses whose amplitude gradually increases with the rate of change at which a microdischarge occurs.
- the first applied pulses Prxl and Pryl are applied once to generate moderate wall charges of the same polarity in all discharge cells regardless of light emission Z non-light emission in the previous subfield SF. Subsequently, by applying pulses Prx2 and Pry2 to the discharge cells where moderate wall charges are present, the wall charges are adjusted so as to be reduced to a level where they are not redischarged by the sustain pulses (erased state).
- the driving voltage applied to the cell is This is a composite voltage representing the difference in the amplitude of the pulses applied to the display electrodes X and Y.
- the address period ⁇ only a discharge cell that emits light forms a wall charge necessary for maintaining the discharge.
- the negative polarity scan pulse is applied to the display electrode ⁇ ⁇ corresponding to the selected row for each row selection period (scanning time for one row). Apply Vy.
- the address pulse Va is applied only to the address electrode A corresponding to the selected cell that should generate the address discharge. That is, based on the subfield data Dsf for m columns of the selected row j, the address electrodes A to
- Address discharge is generated between the address electrode A and the discharge tube.
- the display data written by the address discharge is stored in the form of wall charges on the cell inner wall of the discharge tube, and the surface discharge between the display electrodes X and Y is generated by the subsequent application of the sustain pulse.
- a sustain pulse Ps having a polarity (positive polarity in the example shown in the figure) that is first added to the wall charge generated in the previous address discharge to generate a sustain discharge is applied.
- the sustain pulse Ps is alternately applied to the display electrode X and the display electrode Y.
- the amplitude of the sustain pulse Ps is the sustain voltage Vs.
- the sustain pulse Ps By applying the sustain pulse Ps, a surface discharge is generated in the discharge cell in which a predetermined wall charge remains.
- the number of times that the sustain pulse Ps is applied corresponds to the weight of the subfield SF as described above.
- the address electrode A may be biased to a voltage Vas having the same polarity as the sustain pulse Ps.
- FIG. 7 shows an X electrode driver circuit board 500, a Y electrode driver circuit 700, and two address electrode driver circuits (AD) 46 at the back of two adjacent PTA units 301 and 302 of a normal display device 12. Show the electrical connection of.
- the PTA unit 301 has a power supply 40, a driver control circuit 42, an address “driver circuit 46 for the PTA unit 301, and an X electrode driver circuit board 500 on the back surface thereof.
- the PTA unit 302 has an address driver circuit 46 and an electrode driver circuit 700 for the PTA unit 302 on the back surface thereof.
- the X electrodes of n display electrode pairs 2 (XI, Yl) to (Xn, ⁇ ) of the PTA unit 301 are connected to the X electrode driver circuit board 500 from the right side of the front support board 31 via a flexible cable. .
- ⁇ Display of ⁇ pair of unit 302 ⁇ electrodes of electrode pairs 2 (XI, Yl) to (Xn, ⁇ ) are connected to the scanning pulse circuit 70 of the ⁇ electrode driver circuit 700 from the left side of the front support substrate 31 through a flexible cable.
- Each of the saddle units 301 and 302 has a width of Ly, and therefore the length of the display electrode pair 2 of each PTA unit has Ly.
- the length of Ly is, for example, a value in the range of 0.5 to 2. Om.
- FIG. 8 shows the waveform of the scanning voltage pulse Vy along the longitudinal direction of the scanning electrode Yj of the display electrode pair 2 extending across two adjacent PTA units 301 and 302 of the display device 12. ing.
- FIG. 9 shows an X electrode driver circuit board 500 on the back right side of the PTA unit 321, a Y electrode driver circuit 700 on the back left side of the PTA unit 321, and a PTA in the display device 102 according to the embodiment of the present invention.
- An example of the electrical connection of the two address electrode driver circuits (AD) 46 on the lower back side of units 321 and 322 is shown.
- PTA units 321 and 322 have display electrode pairs 2 (XI, Yl) to (Xn, ⁇ ) connected to each other at the boundary between them.
- X Display electrode pair 2 (XI, ⁇ 1) to ( ⁇ , ⁇ ) of ⁇ unit 321 has an X-electrode via the flexible cable 500FC. It is connected to the sustain voltage pulse circuit 50 (FIG. 4) for the X electrode on the driver circuit board 500.
- the ⁇ electrode is connected to the ⁇ electrode driver from the part of the front support board 31 on the boundary between the left side of ⁇ unit 321 and the right side of ⁇ unit 322 via flexible cable 700FC. Connected to scan pulse circuit 70 of circuit 700.
- the Y electrode high voltage circuit board 600 of the Y electrode driver circuit 700 is connected to the scan pulse circuit 70 through a flexible cable.
- the m signal electrodes 3 Al to Am of the PTA unit 321 are flexible from the end of the rear support board 32 at the bottom of the PTA unit 321 to the flexible 'cable 46FC address of the PTA unit 321 to the driver circuit 46 Connected.
- the driver control circuit 42 is connected to the X electrode driver circuit board 500, the Y electrode high voltage circuit board 600 of the Y electrode driver circuit 700, and the address' driver circuit 46 of the PTA unit 321 via respective cables. Connected. On the back of the PTA unit 321, there is a power supply (PS) 40 that supplies power to Sarakuko, circuits 42, 46, 500 and 700.
- PS power supply
- the m signal electrodes 3 Al to Am of the PTA unit 322 are connected to the driver circuit 46 at the address of the PTA unit 322 via the flexible cable 46FC from the end of the back support board 32 at the bottom of the PTA unit 322.
- the driver control circuit 42 is further connected to the address' driver circuit 46 of the PTA unit 322 via a cable indicated by a one-dot chain line.
- the scanning pulse circuit 70 applies the scanning voltage pulse Vy in parallel to two portions of the length Ly of the 2Ly Y electrode at the boundary between the PTA units 321 and 322.
- the length of the Y electrode from is equal to the horizontal width Ly of each of the PTA units 321 and 322, which is half that of (2Ly) in FIG. Therefore, the partial force of the Y electrode on the boundary to which the scanning voltage pulse of the scan pulse circuit 70 is applied.
- the scan voltage pulse In the discharge cell of the Y electrode portion in each of the PTA units 321 and 322 at the farthest position, the scan voltage pulse— The effective width and height of V y are sufficient, so the possibility of successful address discharge increases
- FIG. 10 shows two X electrode driver circuit boards 500, PTA unit 321 on the right rear side of PTA unit 321 and the left rear side of PTA unit 327 in display device 104, according to another embodiment of the present invention.
- An example of the electrical connection of the Y electrode driver circuit 700 on the left side of the back side and the two address electrode driver circuits (AD) 46 on the lower side of the back side of the PTA units 321 and 322 is shown.
- the PTA units 321 and 327 are at the boundary between them.
- the display electrode pairs 2 (XI, Yl) to (Xn, ⁇ ) are connected to each other.
- the electrical connection of the X electrode driver circuit board 500, the ⁇ electrode driver circuit 700, and the address electrode driver circuit (AD) 46 related to the ⁇ unit 321 is the same as in FIG.
- the X electrodes of the ⁇ pair of display electrodes 2 (XI, ⁇ 1) to ( ⁇ , ⁇ ) of the unit 327 are connected via the flexible cable 500FC from the end of the front support board 31 on the left side of the unit 327 Connected to the X electrode driver circuit board 500 on the back of the boot 327.
- M m signal electrodes 3 Al to Am of unit 327 are connected to the address and driver circuit 46 of the PTA unit 327 through the flexible cable 46FC from the end of the back support board 32 at the bottom of the PTA unit 327 .
- the driver control circuit 42 is further connected to the X electrode driver circuit board 500 and the address' driver circuit 46 of the PTA unit 322 via a cable indicated by a one-dot chain line.
- the scanning pulse circuit 70 applies the scanning voltage pulse Vy to the two portions of the length Ly of the 2Ly Y electrode at the boundary between the PTA units 321 and 327.
- the length of the Y electrode is equal to the width Ly of each of the PTA units 321 and 327. Therefore, in the discharge cell of the Y electrode portion in each of the PTA units 321 and 327 located farthest from the Y electrode portion on the boundary where the scan voltage pulse of the scan pulse circuit 70 is applied, the scan voltage pulse Vy Since the effective width and height are sufficient, the possibility of successful address discharge is increased.
- FIG. 11 shows an X electrode driver circuit board 500 on the rear right side of the PTA unit 33 and a Y electrode driver circuit on the rear left side of the PTA unit 331 in the display device 106 according to still another embodiment of the present invention.
- An example of the electrical connection of 700 and two address electrode driver circuits (AD) 46 on the lower back side of PTA units 331 and 332 is shown.
- PTA units 331 and 332 have display electrode pairs 2 (XI, Yl) to (Xn,, ⁇ ) connected to each other at the boundary between them.
- the electrical connection between the electrode driver circuit 700 and the address electrode driver circuit (AD) 46 related to the unit 331 is the same as that of the unit 321 in FIG. In this case, the X electrode driver circuit board 500 is placed on the back of the unit 331.
- the X electrode of electrode 2 (XI, ⁇ 1) to ( ⁇ , ⁇ ) is connected to the left side of ⁇ unit 331 and ⁇ unit 3
- the front support board 31 on the boundary between the right sides of 32 is connected to the X electrode driver circuit board 500 on the back side of the PTA unit 332 via the flexible cable 500 FC.
- the m signal electrodes 3 Al to Am of the PTA unit 332 are also connected to the address “driver circuit 46” of the PTA unit 321 in the end force of the back support substrate 32 at the bottom of the PTA unit 332.
- the driver control circuit 42 is connected to the X electrode driver circuit board 500 of the PTA unit 322 and the address' driver circuit 46 via a cable indicated by a one-dot chain line.
- Scan pulse circuit 70 applies the scan voltage pulse Vy to two portions of length Ly of length 2Ly at the boundary between PTA units 331 and 332.
- the length of the Y electrode is equal to the width Ly of each of the PTA units 331 and 332. Therefore, in the discharge cell of the Y electrode portion in each of the PTA units 331 and 332 located farthest from the Y electrode portion on the boundary to which the scan voltage pulse of the scan pulse circuit 70 is applied, the scan voltage pulse Vy Since the effective width and height are sufficient, the possibility of successful address discharge is increased.
- FIGS. 12A and 12B show scanning pulse circuits 70 and Z or X from the display electrode pair 2 on the inner surface of the front support substrate 31 at the boundary between two adjacent PTA units 331 and 332 in FIG.
- the method of drawing out the connection line 22 to the electrode driver circuit board 500 is shown.
- the Y electrode connection line 22 is formed on the flexible cable 70FC.
- the X electrode connection line 22 is formed on the flexible cable 500FC.
- each of the front support substrates 31 on the front support substrate 31 extends from the right side of the front support substrate 31 of the separate PTA unit 332 to the lower side of the rear support substrate 32 along the outer surface of the plasma tube 11B.
- a connection line 22 connected to the display electrode pair 2 is formed.
- the left side of the PTA unit 331 is connected to the right side of the PTA unit 332 so that the corresponding display electrode pairs 22 of the PTA unit 321 and the PTA unit 332 are in contact with each other. Make it inconspicuous.
- connection line 22 drawn from the Y electrode in the display electrode 2 is connected to the scan pulse circuit 70 disposed on the left side of the back surface of the PTA unit 331 via a flexible cable 70FC (FIG. 11).
- the connection line 22 drawn from the X electrode in the display electrode pair 2 is connected to the PTA unit via the flexible cable 500FC (Fig. 11). It is connected to an X electrode driver circuit board 500 arranged on the right side of the back surface of 332.
- the X electrode 2 in the display electrode pair 2 has a flexible 'cable 500FC on the right side of the PTA unit 331 and the left side of the PTA unit 332 as shown in Figs. 9 and 10. You can connect to the corresponding X electrode driver circuit board 500 via.
- FIG. 13 illustrates two X electrode driver circuit boards 500, two Ys on the back of four adjacent PT A units 331, 332, 326, and 327 of a display device 108, according to yet another embodiment of the invention.
- An example of electrical connection of the electrode driver circuit 700 and four address electrode driver circuits (AD) 46 is shown.
- the display device 108 has display electrode pairs 2 (XI, ⁇ 1) to ( ⁇ , ⁇ ) connected to each other at the boundaries of the PTA units 331, 332, 326, and 327 ⁇ .
- ⁇ ⁇ Connections in units 331 and 332 are the same as in Fig. 9.
- the connection at ⁇ unit 327 is the same as in Fig.10.
- the electrical connection of ⁇ electrode driver circuit 700 for ⁇ unit 326 is the same as that of ⁇ unit 331 in Fig. 11. In this case, the power supply 40 and the driver control circuit 42 are not arranged on the back surface of the ⁇ unit 326.
- the scan pulse circuit 70 of the unit 331 applies its scan voltage pulse -Vy to two portions of the length Ly of the 4Ly Y electrode at the boundary between the cuts 331 and 332. Since each is applied, the length of the Y electrode from the boundary is equal to the lateral width Ly of each of the PTA units 331 and 332.
- the scanning pulse circuit 70 of the PTA unit 326 applies the scanning voltage pulse 1 Vy to two portions of the length Ly of the Y electrode having a length of 4 Ly at the boundary between the PTA units 326 and 327. The length of the Y electrode from the boundary is equal to the width Ly of each of the PTA units 326 and 327.
- FIG. 14 illustrates two X-electrode dryno cycles on the back of five adjacent PTA units 321, 322, 325, 326, and 327 of display device 110, according to yet another embodiment of the present invention.
- An example of the electrical connection of a road substrate 500, two Y electrode driver circuits 700, and five address electrode driver circuits (AD) 46 is shown.
- Display device 110 (This is a display electrode pair 2 (XI, ⁇ 1) to ( ⁇ , ⁇ ) connected to each other at the boundaries of units 321, 322, 325, 326, and 327 ⁇ .
- the connections in the dredge units 311 and 312 are the same as in FIG.
- the connections in units 326 and 327 are the same as in FIG.
- the connection at ⁇ unit 325 is the same as that of ⁇ unit 322 in Fig. 9.
- the scan pulse circuit 70 of the unit 321 generates its scan voltage pulse—Vy at the boundary between the mute 321 and 322, with the lengths Ly and 1.5Ly of the 4Ly Y electrodes. Since each part is applied to each part, the length of each part of the Y electrode is equal to the width Ly of the PTA unit 331 and 1.5 Ly.
- the scan pulse circuit 70 of the PTA unit 326 applies its scan voltage pulse—Vy to the two parts of length Ly and 1.5Ly of the 4Ly Y electrode at the boundary between the PTA units 326 and 327, respectively. Therefore, the length of each part of the Y electrode from the boundary is equal to the lateral width Ly and 1.5Ly of the PTA unit 327.
- FIG. 15 shows two X electrode driver circuit boards on the back of six adjacent PTA units 321, 322, 324, 325, 326 and 327 of the display device 112, according to yet another embodiment of the present invention. Examples of electrical connections for 500, three Y electrode driver circuits 700, and six address electrode driver circuits (AD) 46 are shown.
- AD address electrode driver circuits
- Display device 112 (This is a display electrode pair 2 (XI, ⁇ 1) to ( ⁇ ,) connected to each other at the boundaries of PTA units 321, 322, 324, 325, 326, and 327 ⁇ . ⁇ ).
- ⁇ Units 321 and 322 are the same as in FIG.
- the connections in dredging units 325, 326 and 327 are the same as in FIG.
- the connection in ⁇ unit 324 is the same as that in ⁇ unit 326.
- Scanning pulse circuit 70 of ⁇ units 331, 324 and 326 Apply Vy to the boundary between the two adjacent PTA units 331 and 332, 324 and 325, and 326 and 327, and apply them to the two parts of the length Ly of the 4Ly Y electrode respectively. Therefore, the length of the Y electrode of the boundary force is equal to the lateral width Ly of each of the PTA modules 321, 322, 324, 325, 326 and 327. Therefore, the apportioning of the Y electrode in each of the PTA units 321, 32 2, 324, 325, 326 and 327 located farthest from the portion of the Y electrode on the boundary where the scan voltage pulse of the scan pulse circuit 70 is applied. In the discharge senor, the effective width and height of the scanning voltage pulse Vy are sufficient, so the possibility of successful address discharge increases.
- FIG. 16 serves to illustrate the scan pulse waveforms for synchronizing the scan pulses of the two or more sets of scan pulse circuits 70 of FIGS.
- One of two arbitrary sets of scan pulse circuits 70 in each of FIGS. 13 to 15 is a scan pulse circuit A, and the other is a scan pulse circuit B.
- the scan pulse of the scan pulse circuit A is in the scan pulse OFF state as shown in FIG. 16E for each Y electrode other than the Y electrode Yj.
- the Y electrode Yj selected by one set of scan pulse circuits A should be effectively turned on, the period Tb in FIG. 16C, and the Y electrodes Yj before and after that selected by another set of scan pulse circuits B — 1 or Yj + 1 should be effectively turned on Period Tb 'and force in Fig. 16D Due to the delay of one scan pulse In order not to overlap, it is necessary to provide a margin period Tt considering the pulse delay time D at the transition between the on state and the off state. Therefore, the scan pulse has a slope (ramp) that falls to the ground potential GND force potential Vy in the first margin period Tt, and a slope that rises to the potential-Vy force ground potential GND in the second margin period Tt. Have.
- FIG. 1 illustrates a schematic partial structure of an array of plasma tubes or gas discharge tubes of a conventional color display device.
- FIG. 2A shows a front-side support substrate on which a plurality of transparent display electrode pairs are formed.
- FIG. 2B shows a backside support substrate on which a plurality of signal electrodes or signal electrodes are formed.
- FIG. 3 shows the structure of a cross section perpendicular to the longitudinal direction of the tube of the plasma tube array of the display device.
- FIG. 4 shows the electrical connections of the X electrode driver circuit board, the Y electrode driver circuit, the address electrode driver circuit, and the driver control circuit on the back of the PTA unit of a normal display device.
- Fig. 5 shows the sustain voltage pulse circuit and scan pulse circuit for the Y electrode in the normal Y electrode driver circuit connected to the PTA unit, and the sustain voltage pulse for the X electrode on the X electrode driver circuit board. Show the schematic configuration of the circuit!
- FIG. 6 shows an example of a schematic drive sequence of output drive voltage waveforms of an X electrode driver circuit board, a Y electrode driver circuit, and an address' driver circuit in a normal display device.
- FIG. 7 shows the electrical connection of the X electrode driver circuit board, the Y electrode driver circuit, and the two address electrode driver circuits on the back of two PTA units arranged adjacent to each other in a normal display device.
- FIG. 8 shows the waveform of the scanning voltage pulse Vy along the longitudinal direction of the scanning electrode Yj of the pair of display electrodes extending across two adjacent PTA units of the display device.
- FIG. 9 is a diagram illustrating an X electrode driver circuit board on the right rear side of the PTA unit, a Y electrode driver circuit on the left rear side of the PTA unit, and a rear surface of the PTA unit in the display device according to the embodiment of the present invention. An example of the electrical connection of the lower two address electrode driver circuits is shown.
- FIG. 10 shows two X electrode driver circuit boards on the right rear side of the PTA unit and the left rear side of the PTA unit, and the Y electrode on the rear left side of the PTA unit in the display device according to another embodiment of the present invention.
- An example of the electrical connection of the driver circuit and the two address electrode driver circuits on the lower back side of the PTA unit is shown.
- FIG. 11 is a diagram showing an X electrode driver circuit board on the right rear side of the PTA unit, a Y electrode driver circuit on the left rear side of the PTA unit, and a display device according to still another embodiment of the present invention. An example of the electrical connection of the two address electrode driver circuits on the lower back side of the PTA unit is shown.
- FIGS. 12A and 12B show the connection lines from the display electrode pair on the inner surface of the front support substrate to the scan pulse circuit and the Z or X electrode driver circuit substrate at the boundary between two adjacent PTA units in FIG. Show me how to pull out.
- FIG. 13 shows four adjacent PTs of a display device according to yet another embodiment of the present invention.
- FIG. 14 shows five adjacent PTs of a display device according to still another embodiment of the present invention.
- FIG. 15 is a diagram showing six adjacent PTs of a display device according to still another embodiment of the present invention.
- Fig. 16 shows the same scan pulse of two or more sets of scan pulse circuits of Figs. 13, 14 and 15. This is useful for explaining the scanning pulse waveform for taking a period.
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Abstract
In a display device (102), a plurality of pairs of display electrodes (X1, Y1)-(Xn, Yn) of a plurality of units are electrically connected to provide a length of the plurality of units. One scanning drive circuit (700) applies a scanning voltage to the display electrodes (Y1-Yn) on one side among the display electrode pairs, and applies a sustaining voltage pulse to the display electrodes (Y1-Yn), on a boundary between two adjacent units (321, 322) among the units.
Description
明 細 書 Specification
表示装置 Display device
技術分野 Technical field
[0001] 本発明は、大型の表示装置に関し、特に、内部に蛍光体層を有する複数のプラズ マ 'チューブ'アレイ力もなる大型の表示装置の走査パルス回路の電気的接続に関 する。 TECHNICAL FIELD [0001] The present invention relates to a large display device, and more particularly to electrical connection of a scanning pulse circuit of a large display device having a plurality of plasma 'tube' array forces each having a phosphor layer therein.
背景技術 Background art
[0002] プラズマ .ディスプレイ .パネル (PDP)は、縦横の多数の小セルの閉じた放電空間 内でプラズマ放電を生じさせ、放電プラズマ力も放出される 147nmの紫外光で蛍光 体を励起して発光させる。そのセル空間は、重ね合わせた 2枚の平板のガラスの間に 形成される。一方、プラズマ 'チューブ 'アレイ (PTA)では、細長いガラス'チューブ 内に蛍光体層を形成しまたは蛍光体層を形成した支持部材を挿入して、そのチュー ブ内に多数のセル空間を形成する。そのようなプラズマ 'チューブを多数並置するこ とによって、例えば 6m X 3mの大型の表示画面を形成することができる。通常のプラ ズマ ·チューブ ·アレイでは、 X電極ドライバ装置から X電極用の維持電圧パルスが印 カロされ、 Y電極ドライバ装置の Y電極用の維持電圧ノ ルス回路から Y電極ドライバ装 置の走査ドライバ回路を介して Y電極用の維持電圧パルスが印加される。 [0002] Plasma display panels (PDPs) emit light by exciting phosphors with ultraviolet light of 147nm, which generates plasma discharge in a closed discharge space of a large number of vertical and horizontal small cells, and discharges plasma power. Let The cell space is formed between two stacked glass sheets. On the other hand, in a plasma 'tube' array (PTA), a phosphor layer is formed in an elongated glass' tube or a support member on which the phosphor layer is formed is inserted to form a large number of cell spaces in the tube. . By arranging a large number of such plasma tubes, for example, a large display screen of 6 m × 3 m can be formed. In a normal plasma tube array, a sustain voltage pulse for the X electrode is printed from the X electrode driver device, and a scan driver for the Y electrode driver device from the sustain voltage pulse circuit for the Y electrode of the Y electrode driver device. A sustain voltage pulse for the Y electrode is applied through the circuit.
[0003] 特開 2004— 178854号公報 (特許文献 1)には、発光管アレイ型表示装置が記載 されている。その発光管アレイ型表示装置は、表示画面を構成する発光管アレイと、 発光管アレイを表示面側と背面側から支持するとともに、発光管に電圧を印加するた めの多数の電極が発光管アレイ対向面にストライプ状に形成された支持体と、表示 画面の表示領域外で支持体に設けられた端子電極引き出し部と、表示画面の表示 領域内で支持体に設けられた中継電極引き出し部と、端子電極引き出し部に電圧を 印加する第 1ドライバと、中継電極引き出し部に電圧を印加する第 2ドライバとを備え ている。それによつて、大きな画面サイズの表示装置でも、電圧降下が生じない電極 構造を有し、それによつて表示装置の輝度ムラを防止する。 [0003] Japanese Unexamined Patent Application Publication No. 2004-178854 (Patent Document 1) describes an arc tube array type display device. The arc tube array type display device includes an arc tube array that constitutes a display screen, and supports the arc tube array from the display surface side and the back side, and a number of electrodes for applying voltage to the arc tube. Supports formed in stripes on the array facing surface, terminal electrode lead-out portions provided on the support outside the display area of the display screen, and relay electrode lead-out portions provided on the support in the display area of the display screen And a first driver for applying a voltage to the terminal electrode lead-out portion and a second driver for applying a voltage to the relay electrode lead-out portion. Accordingly, even a display device having a large screen size has an electrode structure that does not cause a voltage drop, thereby preventing uneven brightness of the display device.
特許文献 1:特開 2004— 178854号公報
発明の開示 Patent Document 1: Japanese Patent Laid-Open No. 2004-178854 Disclosure of the invention
発明が解決しょうとする課題 Problems to be solved by the invention
[0004] それぞれの X電極および Y電極用の駆動回路を具えた並置された複数ユニットの プラズマ ·チューブ ·アレイ力 なる大型の表示装置では、サイズが大きくなるほど表 示電極の長さが増大し、表示電極の抵抗、インダクタンスおよび zまたは容量成分が 増大する。パルス電圧の印加位置から離れたセルの位置までの表示電極のインダク タンスが増大すると、アドレス放電およびサスティン放電用の印加電圧パルスの波形 および実効電圧値に影響を与えることがある。パルス波形の歪みによってアドレス電 圧パルスの立ち上がり遅延時間が長くなると、発光セルに印加される有効印加電圧 パルスの持続時間が短くなり、従ってセルはサスティン放電を失敗しやすくなる。また 、 ノ ルス電圧の印加位置力 離れたセルの位置までの表示電極の抵抗が増大すると 電圧降下が増大し、セル間の実効電圧の差が増大するので、セル間に輝度のばら つきが生じやすくなる。 [0004] In a large-sized display device having a plurality of juxtaposed plasma / tube / array powers equipped with driving circuits for each X electrode and Y electrode, the length of the display electrode increases as the size increases. Display electrode resistance, inductance, and z or capacitance components increase. If the inductance of the display electrode from the position where the pulse voltage is applied to the position of the cell is increased, the waveform and effective voltage value of the applied voltage pulse for address discharge and sustain discharge may be affected. If the rise delay time of the address voltage pulse is increased due to the distortion of the pulse waveform, the duration of the effective applied voltage pulse applied to the light emitting cell is shortened, so that the cell is likely to fail the sustain discharge. In addition, when the resistance of the display electrode to the position of the cell far from the applied position force of the Nors voltage increases, the voltage drop increases and the difference in effective voltage between the cells increases, resulting in luminance variations between the cells. It becomes easy.
[0005] そのような表示電極のインダクタンスおよび抵抗の増大を防止するために、通常、 表示電極の幅または厚さを増大させるが、表示電極の遮光率が高くなり、従って表示 装置の発光効率が低くなり、それによつて表示画質が低下することがあった。 In order to prevent such an increase in the inductance and resistance of the display electrode, the width or thickness of the display electrode is usually increased, but the light shielding rate of the display electrode is increased, and thus the luminous efficiency of the display device is increased. As a result, the display image quality may be lowered.
[0006] 発明者たちは、駆動回路を具えた並置された複数ユニットのプラズマ ·チューブ'ァ レイカ なる大型の表示装置にぉ 、て、複数ユニットのプラズマ ·チューブ ·アレイに 対する走査回路の配置および接続を有利な形態で設計することによって各ユニット におけるアドレス放電の失敗およびそれに伴うサスティン放電の失敗を大幅に減少さ せることができ、それによつて表示の輝度ムラが減少する、と認識した。 [0006] The inventors have arranged a scanning circuit for a multi-unit plasma tube array and a large-sized display device having a plurality of juxtaposed multi-unit plasma tube arrays having a drive circuit. It has been recognized that designing the connection in an advantageous manner can greatly reduce the address discharge failure and the associated sustain discharge failure in each unit, thereby reducing the display brightness unevenness.
[0007] 本発明の目的は、複数ユニットからなる大型の表示装置において輝度ムラを減少さ せることである。 An object of the present invention is to reduce luminance unevenness in a large display device composed of a plurality of units.
[0008] 本発明の別の目的は、複数ユニットからなる大型の表示装置においてアドレス放電 の失敗を減少させることである。 [0008] Another object of the present invention is to reduce address discharge failures in a large display device composed of a plurality of units.
[0009] 本発明のさらに別の目的は、複数ユニットからなる大型の表示装置の複数の走査 駆動回路の走査パルスの同期ずれを防止することである。 [0009] Still another object of the present invention is to prevent a synchronization deviation of scan pulses of a plurality of scan drive circuits of a large display device composed of a plurality of units.
課題を解決するための手段
[0010] 本発明の特徴によれば、表示装置は、内部に、蛍光体層が形成されると共に放電 ガスが封入され、長手方向に複数の発光点をそれぞれ有する複数のガス放電管が 並置され、その複数のガス放電管の表示面側に複数対の表示電極が配置され、そ の複数のガス放電管の背面側に複数の信号電極が配置された複数のユニットからな る。その複数のユニットのその複数対の表示電極は、その複数のユニット分の長さを 有するように電気的に接続されている。その表示装置は、第 1の期間においてその複 数のユニットのその複数対の表示電極の各表示電極対のうちの一方の表示電極に 走査電圧を印加し、第 2の期間においてその一方の表示電極に維持電圧ノ ルスを 印加する少なくとも 1つの走査駆動回路と、その第 2の期間にお 、てその複数のュ- ットのその複数対の表示電極の各表示電極対のうちの他方の表示電極に維持電圧 パルス用の電位を印加する少なくとも 1つの維持電圧回路と、を具えている。その 1つ の走査駆動回路は、その複数のユニットの中の隣接する 2つのユニットの間の境界に お!、て、その複数対の表示電極の各表示電極対のうちのその一方の表示電極に走 查電圧を印加し、その一方の表示電極に維持電圧パルスを印加する。 Means for solving the problem [0010] According to a feature of the present invention, the display device includes a phosphor layer formed therein, a discharge gas sealed therein, and a plurality of gas discharge tubes each having a plurality of light emitting points in the longitudinal direction. A plurality of pairs of display electrodes are arranged on the display surface side of the plurality of gas discharge tubes, and a plurality of signal electrodes are arranged on the back side of the plurality of gas discharge tubes. The plurality of pairs of display electrodes of the plurality of units are electrically connected to have a length corresponding to the plurality of units. The display device applies a scanning voltage to one display electrode of each of the plurality of pairs of display electrodes of the plurality of units in the first period, and displays one of the display electrodes in the second period. At least one scan driving circuit for applying a sustain voltage pulse to the electrodes, and in the second period, the other of the display electrode pairs of the plurality of pairs of display electrodes of the plurality of units. And at least one sustain voltage circuit for applying a sustain voltage pulse potential to the display electrode. The single scan driver circuit is located at the boundary between two adjacent units in the unit! Then, a scanning voltage is applied to one of the display electrode pairs of the plurality of display electrodes, and a sustain voltage pulse is applied to the one display electrode.
[0011] 本発明の別の特徴によれば、その複数の走査駆動回路の中の別の 1つの走査駆 動回路は、その複数のユニットの中の隣接する他の 2つのユニットの間の境界におい て、その複数対の表示電極の各表示電極対のうちのその一方の表示電極に走査電 圧を印加し、その一方の表示電極に維持電圧パルスを印加する。その 1つの走査駆 動回路およびその別の 1つの走査駆動回路の各々の走査電圧パルスは、他方の走 查電圧パルスとの間の同期ずれを防止するための期間を、隣接走査電圧パルス間 に有する。 [0011] According to another feature of the invention, another scan drive circuit in the plurality of scan drive circuits includes a boundary between the other two adjacent units in the plurality of units. In this case, a scanning voltage is applied to one of the display electrode pairs of the plurality of display electrodes, and a sustain voltage pulse is applied to the one display electrode. The scanning voltage pulse of each of the one scanning driving circuit and the other scanning driving circuit has a period between adjacent scanning voltage pulses, in order to prevent synchronization with the other scanning voltage pulse. Have.
発明の効果 The invention's effect
[0012] 本発明によれば、複数ユニットからなる大型の表示装置において輝度ムラを減少さ せることができ、アドレス放電の失敗を減少させることができ、複数ユニットからなる大 型の表示装置の複数の走査駆動回路の走査パルスの同期ずれを防止することがで きる。 [0012] According to the present invention, it is possible to reduce luminance unevenness in a large display device composed of a plurality of units, to reduce address discharge failures, and to reduce a plurality of large display devices composed of a plurality of units. Therefore, it is possible to prevent the scan pulse from being out of synchronization in the scan drive circuit.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
[0013] 本発明の実施形態を、図面を参照して説明する。図面において、同様の構成要素
には同じ参照番号が付されて 、る。 An embodiment of the present invention will be described with reference to the drawings. Similar components in drawings Are given the same reference numbers.
[0014] 図 1は、通常カラー表示装置用のプラズマ 'チューブまたはガス放電管 11R、 11G および 11Bのアレイのユニット 300の概略的な部分的構造を例示して 、る。図 1にお いて、プラズマ'チューブ'アレイ(PTA)のユニット 300は、互いに平行に配置された 透明な細長いカラ一'プラズマ 'チューブ 11R、 11Gおよび 11Bのアレイ、透明な前 面側の支持シートまたは薄い基板力 なる前面側支持基板 31、透明なまたは不透 明な背面側の支持シートまたは薄 、基板力 なる背面側支持基板 32、複数の表示 電極対または主電極対 2、および複数の信号電極またはアドレス電極 3を含んで!/、る 。図 1において、 Xは表示電極 2のうちの維持電極または X電極を示し、 Yは表示電極 2のうちの走査電極または Y電極を示している。 R、 Gおよび Bは蛍光体の発光色であ る赤、緑および青を示している。支持基板 31および 32は、例えば可撓性の PETフィ ルム、ガラス等で作られている。 [0014] FIG. 1 illustrates a schematic partial structure of a unit 300 of an array of plasma tubes or gas discharge tubes 11R, 11G and 11B, typically for a color display. In FIG. 1, the unit 300 of the plasma 'tube' array (PTA) consists of an array of transparent elongated color 'plasma' tubes 11R, 11G and 11B arranged in parallel to each other, a transparent front support sheet. Front support substrate 31 with thin substrate force, transparent support substrate or thin with transparent or opaque back support substrate 32 with substrate force, multiple display electrode pairs or main electrode pair 2, and multiple signals Including the electrode or address electrode 3! / In FIG. 1, X represents a sustain electrode or X electrode of the display electrode 2, and Y represents a scan electrode or Y electrode of the display electrode 2. R, G, and B indicate red, green, and blue emission colors of the phosphor. The support substrates 31 and 32 are made of, for example, flexible PET film or glass.
[0015] 細長いプラズマ 'チューブ 11R、 11Gおよび 1 IBの細管 20は、例えばホウケィ酸ガ ラス、パイレックス (登録商標)、ソーダガラス、石英ガラスまたはゼロデュアのような透 明な絶縁体で作製され、典型的には、管径が 2mm以下であり、例えば、管の断面の 幅約 lmmおよび高さ約 0. 55mmであり、長さが 300mm以上であり、管壁の厚さ約 0. lmmの寸法を有する。 [0015] Elongated plasma 'tubes 11R, 11G, and 1 IB capillaries 20 are made of transparent insulators, such as borosilicate glass, Pyrex®, soda glass, quartz glass or zerodur, typically For example, the tube diameter is 2 mm or less, for example, the tube cross-sectional width is about lmm and the height is about 0.55 mm, the length is 300 mm or more, and the tube wall thickness is about 0.1 mm. Have
[0016] プラズマ 'チューブ 11R、 11Gおよび 1 IBの内部の背面側には、赤、緑、青(R、 G 、 B)の蛍光体層 4をそれぞれ形成した支持部材がそれぞれ挿入されて配置され、放 電ガスが導入されて、両端が封止されている。プラズマ 'チューブ 11R、 11Gおよび 1 1Bの内面には MgO力もなる電子放出膜 5が形成されている。蛍光体層 R、 G、 Bは、 典型的には、約 10 m〜約 50 μ mの範囲の厚さを有する。 [0016] Support members on which the phosphor layers 4 of red, green, and blue (R, G, and B) are respectively formed are inserted and arranged on the rear side of the plasma 'tubes 11R, 11G, and 1IB. Discharged gas is introduced and both ends are sealed. On the inner surfaces of the plasma tubes 11R, 11G, and 11B, an electron emission film 5 having MgO force is formed. The phosphor layers R, G, B typically have a thickness in the range of about 10 m to about 50 μm.
[0017] 支持部材は、プラズマ 'チューブ 11R、 11G、 11Bと同様に、例えばホウケィ酸ガラ ス、ノィレックス (登録商標)、石英ガラス、ソーダガラス、鉛ガラスのような絶縁体で作 製され、この支持部材上に蛍光体層 4が形成されている。支持部材は、ガラス管の外 部で、支持部材上に蛍光体ペーストを塗布し、それを焼成して支持部材上に蛍光体 層 4を形成した後、その支持部材をガラス管内に挿入して配置することができる。その ような蛍光体ペーストとして、当該分野で公知の各種の蛍光体ペーストを利用するこ
とがでさる。 [0017] The support member is made of an insulator such as borosilicate glass, Neurex (registered trademark), quartz glass, soda glass, lead glass, and the like as in the plasma tubes 11R, 11G, and 11B. A phosphor layer 4 is formed on the support member. The support member is an outer portion of the glass tube. After the phosphor paste is applied on the support member and baked to form the phosphor layer 4 on the support member, the support member is inserted into the glass tube. Can be arranged. As such phosphor paste, various phosphor pastes known in the art can be used. Togashi.
[0018] 電子放出膜 5は、放電ガスの荷電粒子との衝突により電子を発生する。蛍光体層 4 は、表示電極対 2に電圧を印加することにより励起された管内に封入された放電ガス が脱励起することによって発生する真空紫外光によって励起され、可視光を発生す る。 [0018] The electron emission film 5 generates electrons by collision with charged particles of the discharge gas. The phosphor layer 4 is excited by vacuum ultraviolet light generated by de-excitation of the discharge gas enclosed in the tube excited by applying a voltage to the display electrode pair 2, and generates visible light.
[0019] 図 2Aは、透明な複数の表示電極対 2が形成された前面側支持基板 31を示してい る。図 2Bは、複数の信号電極 3が形成された背面側支持基板 32を示している。 FIG. 2A shows a front-side support substrate 31 on which a plurality of transparent display electrode pairs 2 are formed. FIG. 2B shows a back side support substrate 32 on which a plurality of signal electrodes 3 are formed.
[0020] 信号電極 3は、背面側支持基板 32の前面すなわち内面上に形成され、プラズマ- チューブ 11R、 11Gおよび 1 IBの長手方向に沿って設けられている。隣接する信号 電極 3間のピッチは、プラズマ 'チューブ 11R、 11Gおよび 1 IBの各々の幅とほぼ同 じであり、例えば lmmである。複数の表示電極対 2は、周知の形態で前面側支持基 板 31の背面すなわち内面上に形成され、信号電極 3と直角に交差する方向に配置 されている。表示電極 2の幅は例えば 0. 75mmであり、各 1対の表示電極 2の端縁 間の距離は例えば 0. 4mmである。表示電極対 2と隣の表示電極対 2の間には、非 放電領域となる距離または非放電ギャップが確保され、その距離は例えば 1. lmm である。 [0020] The signal electrode 3 is formed on the front surface, that is, the inner surface of the back side support substrate 32, and is provided along the longitudinal direction of the plasma tubes 11R, 11G, and 1IB. The pitch between the adjacent signal electrodes 3 is substantially the same as the width of each of the plasma tubes 11R, 11G, and 1IB, for example, lmm. The plurality of display electrode pairs 2 are formed on the back surface, that is, the inner surface of the front-side support substrate 31 in a well-known form, and are arranged in a direction perpendicular to the signal electrode 3. The width of the display electrode 2 is, for example, 0.75 mm, and the distance between the edges of each pair of display electrodes 2 is, for example, 0.4 mm. A distance serving as a non-discharge region or a non-discharge gap is secured between the display electrode pair 2 and the adjacent display electrode pair 2, and the distance is, for example, 1. lmm.
[0021] 信号電極 3と表示電極対 2は、 PTAユニット 300の組み立て時にプラズマ 'チュー ブ 11R、 11Gおよび 11Bの下側の外周面部分と上側の外周面部分にそれぞれ密着 するように接触させる。その密着性を良くするために、それぞれの電極とプラズマ 'チ ユーブ面との間に接着剤を介在させて接着してもよい。 [0021] The signal electrode 3 and the display electrode pair 2 are brought into close contact with the lower outer peripheral surface portion and the upper outer peripheral surface portion of the plasma tubes 11R, 11G, and 11B when the PTA unit 300 is assembled. In order to improve the adhesion, an adhesive may be interposed between each electrode and the plasma tube surface to bond them.
[0022] この PTAユニット 300を正面から平面的にみた場合、信号電極 3と表示電極対 2と の交差部が単位発光領域となる。表示は、表示電極対 2のいずれ力 1本を走査電極 Yとして用い、その走査電極 Yと信号電極 3との交差部で選択放電を発生させて発光 領域を選択し、その放電により当該領域の管内面に形成された壁電荷を利用して、 表示電極対 2で表示放電を発生させ、蛍光体層を発光させることによって行う。選択 放電は、垂直方向に対向する走査 Y電極と信号電極 3との間のプラズマ ·チューブ 1 1R、 11Gおよび 1 IB内で発生される対向放電である。表示放電は、平面上に平行 に配置された 1対の表示電極間のプラズマ 'チューブ 11R、 11Gおよび 11B内で発
生される面放電である。 [0022] When the PTA unit 300 is viewed from the front, the intersection of the signal electrode 3 and the display electrode pair 2 is a unit light emitting region. For display, one of the display electrode pairs 2 is used as the scan electrode Y, a selective discharge is generated at the intersection of the scan electrode Y and the signal electrode 3, and a light emitting region is selected. Using the wall charges formed on the inner surface of the tube, a display discharge is generated at the display electrode pair 2 and the phosphor layer emits light. The selective discharge is a counter discharge generated in the plasma tubes 11R, 11G, and 1IB between the scanning Y electrode and the signal electrode 3 facing each other in the vertical direction. Display discharge is generated in the plasma tubes 11R, 11G and 11B between a pair of display electrodes arranged in parallel on a plane. This is a surface discharge.
[0023] 表示電極対 2と信号電極 3は、電圧を印加することによって管内部の放電ガスに放 電を発生させることが可能である。図 1では、プラズマ 'チューブ 11R、 11Gおよび 11 Bの電極構造は、 1つの発光部位に 3つの電極が配置された構成であり、表示電極 対 2によって表示放電が発生される構造である力 これに限定されるものではなぐ表 示電極 2と信号電極 3の間で表示放電が発生される構造であってもよい。即ち、表示 電極対 2を 1本とし、この表示電極 2を走査電極として用 、て信号電極 3との間に選択 放電と表示放電 (対向放電)を発生させる形式の電極構造であってもよ ヽ。 The display electrode pair 2 and the signal electrode 3 can generate a discharge in the discharge gas inside the tube by applying a voltage. In Fig. 1, the electrode structure of plasma 'tubes 11R, 11G and 11B is a structure in which three electrodes are arranged in one light emitting part, and the display discharge is generated by display electrode pair 2. However, the display electrode 2 and the signal electrode 3 may have a structure in which display discharge is generated. That is, the display electrode pair 2 may be one, and the display electrode 2 may be used as a scanning electrode to generate a selective discharge and a display discharge (opposite discharge) between the display electrode 2 and the signal electrode 3.ヽ.
[0024] 図 3は、 PTAユニット 300のプラズマ'チューブ'アレイ 11の管の長手方向に垂直な 断面の構造を示している。 PTAユニット 300において、プラズマ 'チューブ 11R、 11 Gおよび 1 IBは、その中の背面側の支持部材 6R、 6Gおよび 6Bの内面に蛍光体層 4R、 4Gおよび 4Bが形成されており、断面幅 1. Omm、断面高さ 0. 55mm,管壁の 厚さ 0. lmm、および長さ lm〜3mの細管力もなる。一実施例として、赤の蛍光体 4 Rはイットリア系((Y. Ga) BO: Eu)の材料を含み、緑の蛍光体 4Gはジンクシリケー FIG. 3 shows a cross-sectional structure perpendicular to the longitudinal direction of the tubes of the plasma “tube” array 11 of the PTA unit 300. In the PTA unit 300, the plasma 'tubes 11R, 11G, and 1IB have phosphor layers 4R, 4G, and 4B formed on the inner surfaces of the back support members 6R, 6G, and 6B, and have a cross-sectional width of 1 Omm, cross-sectional height 0.55mm, tube wall thickness 0. lmm, and length lm to 3m capillary force. As an example, the red phosphor 4 R includes a yttria-based ((Y. Ga) BO: Eu) material, and the green phosphor 4G is zinc silicate.
3 Three
ト系(Zn SiO : Mn)の材料を含み、青の蛍光体 4Bは BAM系(BaMgAl O : Eu) The blue phosphor 4B contains BAM (BaMgAl 2 O: Eu).
2 4 10 17 の材料を含む。 2 4 10 17 materials included.
[0025] 図 3において、プラズマ 'チューブ 11R、 11Gおよび 11Bの底面には、粘着剤層 34 を介して背面側支持基板 32が接着されている。プラズマ 'チューブ 11R、 11Gおよ び 11Bの底面に、および背面側支持基板 32の上面に信号電極 3R、 3Gおよび 3Bが 配置されている。 In FIG. 3, a back-side support substrate 32 is bonded to the bottom surfaces of the plasma tubes 11R, 11G, and 11B via an adhesive layer 34. Signal electrodes 3R, 3G, and 3B are arranged on the bottom surfaces of the plasma tubes 11R, 11G, and 11B and on the top surface of the back support substrate 32.
[0026] 図 4は、通常の表示装置 10の PTAユニット 300の背面における X電極ドライバ回路 基板 500、 Y電極ドライバ回路 700、アドレス電極ドライバ回路 (AD) 46、およびドラ ィバ制御回路 42の電気的接続を示して 、る。 [0026] FIG. 4 shows the electrical characteristics of the X electrode driver circuit board 500, the Y electrode driver circuit 700, the address electrode driver circuit (AD) 46, and the driver control circuit 42 on the back of the PTA unit 300 of the normal display device 10. Indicate the ideal connection.
[0027] 図 5は、 PTAユニット 300に接続された、通常の Y電極ドライバ回路 700における Y 電極用の維持電圧パルス回路(SST) 60および走査パルス回路(SCN) 70と、 X電 極ドライバ回路基板 500上の X電極用の維持電圧パルス回路 50の概略的構成を示 している。 FIG. 5 shows a sustain voltage pulse circuit (SST) 60 and a scan pulse circuit (SCN) 70 for the Y electrode in an ordinary Y electrode driver circuit 700 connected to the PTA unit 300, and an X electrode driver circuit. A schematic configuration of the sustain voltage pulse circuit 50 for the X electrode on the substrate 500 is shown.
[0028] 維持電圧パルス回路(SST) 50は、スィッチを介して X電極 XI〜: Xnに接続される
バイアス電圧源 Vs、およびスィッチを介して X電極 XI〜: Xnに接続される接地電位 G NDを含んでいる。 [0028] Sustain voltage pulse circuit (SST) 50 is connected to X electrodes XI to Xn via switches. It includes a bias voltage source Vs and a ground potential GND connected to the X electrode XI˜: Xn through the switch.
[0029] 維持電圧パルス回路(SST) 60は、スィッチを介して走査パルス回路(SCN) 70に 接続された高 ヽパルス電圧源 Vs、およびスィッチを介して走査パルス回路 70に接続 された接地電位 GNDを含んでいる。走査パルス回路(SCN) 70は、パルス電圧源 V sおよび接地電位 GNDを Y電極 Yl〜Ynに結合する。走査パルス回路 70は、さらに 、スィッチを介して Υ電極 Υ1〜Υηに接続されるバイアス電圧源 Vsc、およびスィッチ を介して Y電極 Y 1〜Ynに接続される走査パルス電源— Vyを含んでいる。 [0029] The sustain voltage pulse circuit (SST) 60 includes a high voltage pulse voltage source Vs connected to the scan pulse circuit (SCN) 70 via the switch, and a ground potential connected to the scan pulse circuit 70 via the switch. Includes GND. Scanning pulse circuit (SCN) 70 couples pulse voltage source Vs and ground potential GND to Y electrodes Yl to Yn. The scan pulse circuit 70 further includes a bias voltage source Vsc connected to the Υ electrodes Υ1 to Υη via the switch, and a scan pulse power source Vy connected to the Y electrodes Y1 to Yn via the switch. .
[0030] 図 4を参照すると、表示装置 10において、 PTAユニット 300の n対の表示電極対 2 Referring to FIG. 4, in display device 10, n pairs of display electrodes 2 of PTA unit 300
(XI, Yl)〜(Xn, Υη)の X電極は、前面支持基板 31の右辺からフレキシブル.ケー ブル 500FCを介して X電極ドライバ回路基板 500上の X電極用の維持電圧パルス 回路 50に接続され、その Υ電極は、前面支持基板 31の左辺力もフレキシブル'ケー ブル 70FCを介して Υ電極ドライバ回路 700の Υ電極高電圧回路基板 600上の走査 パルス回路 70に接続される。 Υ電極ドライバ回路 700上の Υ電極用の維持電圧パル ス回路 60は、フレキシブル ·ケーブルを介して走査パルス回路 70に接続される。 ΡΤ Αユニット 300の m本の信号電極 3 Al〜Amは、背面支持基板 32の底辺からフレキ シブル ·ケーブル 46FCを介してアドレス ·ドライバ回路 46に接続される。 X電極ドライ バ回路基板 500はさらにリセット回路 (RST) 51を含んでいる。 Y高電圧回路基板 60 0はさらにリセット回路 (RST) 61を含んでいる。ドライバ制御回路 42が、 X電極ドライ バ回路基板 500、 Y電極ドライバ回路 700の Y電極高電圧回路基板 600およびアド レス'ドライバ回路 46に接続される。 PTAユニット 300の背面には、さらに、各回路 42 、 46、 500および 700に電力を供給する電源(PS) 40が設けられている。 The X electrodes (XI, Yl) to (Xn, Υη) are connected to the sustain voltage pulse circuit 50 for the X electrodes on the X electrode driver circuit board 500 via the flexible cable 500FC from the right side of the front support board 31. The left electrode of the front support substrate 31 is also connected to the scanning pulse circuit 70 on the high electrode circuit board 600 of the high electrode driver circuit 700 via the flexible cable 70FC. The sustain voltage pulse circuit 60 for the saddle electrode on the saddle electrode driver circuit 700 is connected to the scan pulse circuit 70 via a flexible cable. Α The m signal electrodes 3 Al to Am of the unit 300 are connected to the address driver circuit 46 through the flexible cable 46FC from the bottom side of the back support board 32. The X electrode driver circuit board 500 further includes a reset circuit (RST) 51. The Y high voltage circuit board 600 further includes a reset circuit (RST) 61. The driver control circuit 42 is connected to the X electrode driver circuit board 500, the Y electrode high voltage circuit board 600 of the Y electrode driver circuit 700, and the address' driver circuit 46. On the back surface of the PTA unit 300, a power source (PS) 40 that supplies power to the circuits 42, 46, 500, and 700 is further provided.
[0031] 次に、一般的なプラズマ ·チューブ ·アレイ型の AC型ガス放電表示装置の駆動法 の一例について説明する。 1つのピクチャ(映像)は典型的には 1フレーム期間で構 成されており、インターレース型走査では 1フレームが 2つのフィールドで構成され、 プログレッシブ型走査では 1フレームが 1つのフィールドで構成されている。また、通 常のテレビジョン方式による動画表示のためには 1秒間に 30フレームの表示が必要 である。そこでこの種ガス放電表示装置 10による表示では、 2値の発光制御によって
階調を持ったカラー再現を行うために、典型的にはそのような 1フィールド Fを q個の サブフィールド SFの集合に置き換える。しばしば、これらサブフィールド SFに順に 2° , 21, 22, . . . 2q_1等の異なる重みを付けて各サブフィールド SFの表示放電の回数を 設定する。サブフィールド単位の発光 Z非発光の組合せで R, Gおよび Bの各色毎 に N ( = l + 21 + 22 + . . . + 2q_1 )段階の輝度設定を行うことができる。このようなフィ 一ルド構成に合わせてフィールド転送周期であるフィールド期間 Tfを q個のサブフィ 一ルド期間 Tsfに分割し、各サブフィールド SFに 1つのサブフィールド期間 Tsfを割り 当てる。さらに、サブフィールド期間 Tsfを、初期化のためのリセット期間 TR、アドレツ シングのためのアドレス期間 TA、および維持放電による発光のための表示期間 TS に分ける。典型的には、リセット期間 TRおよびアドレス期間 TAの長さが重みに係わ らず一定であるのに対し、表示期間 TSにおけるパルス数は重みが大き 、ほど多く、 表示期間 TSの長さは重みが大きいほど長い。この場合、サブフィールド期間 Tsfの 長さも、該当するサブフィールド SFの重みが大きいほど長い。 Next, an example of a driving method of a general plasma tube array type AC gas discharge display device will be described. One picture (video) is typically composed of one frame period. In interlaced scanning, one frame is composed of two fields, and in progressive scanning, one frame is composed of one field. . In addition, 30 frames per second are required for video display using the normal television system. Therefore, in the display by this kind of gas discharge display device 10, binary light emission control is used. In order to perform color reproduction with gradation, typically one field F is replaced with a set of q subfields SF. Often, the number of display discharges in each subfield SF is set by giving different weights such as 2 °, 2 1 , 2 2 , ... N (= l + 2 1 + 2 2 + ... + 2 q_1 ) levels of brightness can be set for each color of R, G, and B by combining light emission Z and no light emission in subfield units. According to such a field configuration, the field period Tf which is a field transfer period is divided into q subfield periods Tsf, and one subfield period Tsf is assigned to each subfield SF. Further, the subfield period Tsf is divided into a reset period TR for initialization, an address period TA for addressing, and a display period TS for light emission by sustain discharge. Typically, the length of the reset period TR and the address period TA is constant regardless of the weight, whereas the number of pulses in the display period TS is larger and the length of the display period TS is The greater the weight, the longer. In this case, the length of the subfield period Tsf is longer as the weight of the corresponding subfield SF is larger.
[0032] 図 6は、通常の表示装置 10における、 X電極ドライバ回路基板 500、 Y電極ドライバ 回路 700およびアドレス 'ドライバ回路 42の出力駆動電圧波形の概略的な駆動シー ケンスを例示している。なお、図示の波形は一例であり、振幅、極性およびタイミング を様々に変更することができる。 FIG. 6 exemplifies a schematic drive sequence of output drive voltage waveforms of the X electrode driver circuit board 500, the Y electrode driver circuit 700, and the address' driver circuit 42 in the normal display device 10. The waveform shown is an example, and the amplitude, polarity, and timing can be changed in various ways.
[0033] リセット期間 TR、アドレス期間 TAおよびサスティン期間 TSの順序は、 q個のサブフ ィールド SFにおいて同じであり、駆動シーケンスはサブフィールド SF毎に繰り返され る。各サブフィールド SFのリセット期間 TRにおいては、全ての表示電極 Xに対して負 極性のパルス Prxlと正極性のパルス Prx2とを順に印加し、全ての表示電極 Yに対 して正極性のパルス Pry 1と負極性のパルス Pry2とを順に印加する。パルス Prxl, P rylおよび Pry2は微小放電が生じる変化率で振幅が漸増するランプ波形または鈍 波パルスである。最初に印加されるパルス Prxlおよび Prylは、前サブフィールド SF における発光 Z非発光に係わらず全ての放電セルにいったん同一極性の適度の壁 電荷を生じさせるために印加される。引き続き適度の壁電荷が存在する放電セルに パルス Prx2および Pry2を印加することにより、この壁電荷を維持パルスでは再放電 しないレベル (消去状態)まで減少させるように調整する。セルに加わる駆動電圧は、
表示電極 Xおよび Yに印加されるパルスの振幅の差を表す合成電圧である。 [0033] The order of reset period TR, address period TA, and sustain period TS is the same in q subfields SF, and the drive sequence is repeated for each subfield SF. In the reset period TR of each subfield SF, a negative polarity pulse Prxl and a positive polarity pulse Prx2 are sequentially applied to all the display electrodes X, and a positive polarity pulse Pry is applied to all the display electrodes Y. 1 and negative polarity pulse Pry2 are applied in order. Pulses Prxl, P ryl and Pry2 are ramp waveforms or blunt pulses whose amplitude gradually increases with the rate of change at which a microdischarge occurs. The first applied pulses Prxl and Pryl are applied once to generate moderate wall charges of the same polarity in all discharge cells regardless of light emission Z non-light emission in the previous subfield SF. Subsequently, by applying pulses Prx2 and Pry2 to the discharge cells where moderate wall charges are present, the wall charges are adjusted so as to be reduced to a level where they are not redischarged by the sustain pulses (erased state). The driving voltage applied to the cell is This is a composite voltage representing the difference in the amplitude of the pulses applied to the display electrodes X and Y.
[0034] アドレス期間 ΤΑにおいては、発光させる放電セルのみに放電維持に必要な壁電 荷を形成する。全ての表示電極 Xおよび全ての表示電極 Υを所定電位にバイアスし た状態で、行選択期間(1行分のスキャン時間)毎に選択行に対応した表示電極 Υに 負極性のスキャン'パルス— Vyを印加する。この行選択と同時にアドレス放電を生じ させるべき選択セルに対応したアドレス電極 Aのみにアドレス ·パルス Vaを印加する 。つまり、選択行 jの m列分のサブフィールドデータ Dsfに基づいてアドレス電極 A〜 In the address period ΤΑ, only a discharge cell that emits light forms a wall charge necessary for maintaining the discharge. With all display electrodes X and all display electrodes Υ biased to a predetermined potential, the negative polarity scan pulse is applied to the display electrode 対 応 corresponding to the selected row for each row selection period (scanning time for one row). Apply Vy. Simultaneously with the row selection, the address pulse Va is applied only to the address electrode A corresponding to the selected cell that should generate the address discharge. That is, based on the subfield data Dsf for m columns of the selected row j, the address electrodes A to
1 1
Aの電位を走査ライン毎に 2値制御する。これによつて、選択セルでは表示電極 Yと m Binary control of A potential for each scan line. As a result, in the selected cell, the display electrodes Y and m
アドレス電極 Aとの間で放電管内にアドレス放電が生じる。そのアドレス放電によって 書き込まれた表示データが放電管のセル内壁に壁電荷の形で記憶され、その後の サスティン'パルスの印加により表示電極 X—Y間の面放電が生じる。 Address discharge is generated between the address electrode A and the discharge tube. The display data written by the address discharge is stored in the form of wall charges on the cell inner wall of the discharge tube, and the surface discharge between the display electrodes X and Y is generated by the subsequent application of the sustain pulse.
[0035] サステスティン期間 TSにおいては、最初に先のアドレス放電で生じた壁電荷と加 算されて維持放電を発生する極性(図の例では正極性)のサスティン'パルス Psを印 加する。その後、表示電極 Xと表示電極 Yとに対して交互にサスティン'パルス Psを 印加する。サスティン'パルス Psの振幅は維持電圧 Vsである。サスティン'パルス Ps の印加によって、所定の壁電荷が残存する放電セルにおいて面放電が生じる。サス ティン'パルス Psの印加回数は、上述したようにサブフィールド SFの重みに対応する 。なお、サスティン期間 TS全体にわたって不要な対向放電を防止するために、アド レス電極 Aをサスティン'パルス Psと同極性の電圧 Vasにバイアスしてもよい。 In the sustain period TS, a sustain pulse Ps having a polarity (positive polarity in the example shown in the figure) that is first added to the wall charge generated in the previous address discharge to generate a sustain discharge is applied. Thereafter, the sustain pulse Ps is alternately applied to the display electrode X and the display electrode Y. The amplitude of the sustain pulse Ps is the sustain voltage Vs. By applying the sustain pulse Ps, a surface discharge is generated in the discharge cell in which a predetermined wall charge remains. The number of times that the sustain pulse Ps is applied corresponds to the weight of the subfield SF as described above. In order to prevent unnecessary counter discharge throughout the sustain period TS, the address electrode A may be biased to a voltage Vas having the same polarity as the sustain pulse Ps.
[0036] 図 7は、通常の表示装置 12の隣接配置された 2つの PTAユニット 301および 302 の背面における X電極ドライバ回路基板 500、 Y電極ドライバ回路 700および 2つの アドレス電極ドライバ回路 (AD) 46の電気的接続を示して 、る。 [0036] FIG. 7 shows an X electrode driver circuit board 500, a Y electrode driver circuit 700, and two address electrode driver circuits (AD) 46 at the back of two adjacent PTA units 301 and 302 of a normal display device 12. Show the electrical connection of.
[0037] PTAユニット 301は、その背面に、電源 40、ドライバ制御回路 42、 PTAユニット 30 1用のアドレス 'ドライバ回路 46、および X電極ドライバ回路基板 500を有する。 PTA ユニット 302は、その背面に、 PTAユニット 302用のアドレス 'ドライバ回路 46、およ ひ Ύ電極ドライバ回路 700を有する。 PTAユニット 301の n対の表示電極対 2 (XI, Yl)〜(Xn, Υη)の X電極は、前面支持基板 31の右辺からフレキシブル 'ケーブル を介して X電極ドライバ回路基板 500に接続される。 ΡΤΑユニット 302の η対の表示
電極対 2 (XI, Yl)〜(Xn, Υη)の Υ電極は、前面支持基板 31の左辺からフレキシ ブル.ケーブルを介して Υ電極ドライバ回路 700の走査パルス回路 70に接続される。 ΡΤΑユニット 301および 302の各々は Lyの横幅を有し、従って各 PTAユニットの表 示電極対 2の長さは Lyを有する。 Lyの長さは、例えば 0. 5〜2. Omの範囲の値であ る。 The PTA unit 301 has a power supply 40, a driver control circuit 42, an address “driver circuit 46 for the PTA unit 301, and an X electrode driver circuit board 500 on the back surface thereof. The PTA unit 302 has an address driver circuit 46 and an electrode driver circuit 700 for the PTA unit 302 on the back surface thereof. The X electrodes of n display electrode pairs 2 (XI, Yl) to (Xn, Υη) of the PTA unit 301 are connected to the X electrode driver circuit board 500 from the right side of the front support board 31 via a flexible cable. . ΡΤΑ Display of η pair of unit 302 Υ electrodes of electrode pairs 2 (XI, Yl) to (Xn, Υη) are connected to the scanning pulse circuit 70 of the Υ electrode driver circuit 700 from the left side of the front support substrate 31 through a flexible cable. Each of the saddle units 301 and 302 has a width of Ly, and therefore the length of the display electrode pair 2 of each PTA unit has Ly. The length of Ly is, for example, a value in the range of 0.5 to 2. Om.
[0038] 図 8は、表示装置 12の隣接する 2つの PTAユニット 301および 302にわたつて延び る表示電極対 2のうちの走査電極 Yjの長手方向に沿った走査電圧パルス Vyの波 形を示している。 [0038] FIG. 8 shows the waveform of the scanning voltage pulse Vy along the longitudinal direction of the scanning electrode Yj of the display electrode pair 2 extending across two adjacent PTA units 301 and 302 of the display device 12. ing.
[0039] 走査期間 TSにおいて走査パルス回路 70から走査電極 Yjに印加された走査電圧 パルス Vyは、矩形に近い台形の波形を有するが、走査電極 Yjの長手方向の距離 (D = 0〜D = 2Ly)が長くなるに従って、そのインダクタンス成分によってより大きいリ ンギングを生じ、その電気抵抗によって高さがより小さくなるように、より歪んだ波形を 有する。従って、走査パルス回路 70の走査電圧パルスが印加される境界上の Y電極 の部分力も最も遠 、位置(D = 2Ly)にある PTAユニット 301における走査電極 Yjの 部分の放電セルでは、走査電圧パルス Vyの実効的な幅および高さが不充分なの で、アドレス放電に失敗することがある。それによつて、そのようなセルは、その後のサ スティン期間 TSにおけるサスティン放電に失敗することがある。 [0039] The scan voltage pulse Vy applied to the scan electrode Yj from the scan pulse circuit 70 in the scan period TS has a trapezoidal waveform close to a rectangle, but the longitudinal distance of the scan electrode Yj (D = 0 to D = As 2Ly) becomes longer, the inductance component causes more ringing, and the electric resistance has a more distorted waveform so that the height becomes smaller. Therefore, the partial force of the Y electrode on the boundary to which the scan voltage pulse of the scan pulse circuit 70 is applied is the farthest, and in the discharge cell of the scan electrode Yj portion in the PTA unit 301 at the position (D = 2Ly), the scan voltage pulse Address discharge may fail due to insufficient effective width and height of Vy. As a result, such a cell may fail to sustain discharge in the subsequent sustain period TS.
[0040] 図 9は、本発明の実施形態による、表示装置 102における、 PTAユニット 321の背 面右側の X電極ドライバ回路基板 500、 PTAユニット 321の背面左側の Y電極ドライ バ回路 700、および PTAユニット 321および 322の背面下側の 2つのアドレス電極ド ライバ回路 (AD) 46の電気的接続の例を示して 、る。 FIG. 9 shows an X electrode driver circuit board 500 on the back right side of the PTA unit 321, a Y electrode driver circuit 700 on the back left side of the PTA unit 321, and a PTA in the display device 102 according to the embodiment of the present invention. An example of the electrical connection of the two address electrode driver circuits (AD) 46 on the lower back side of units 321 and 322 is shown.
[0041] 表示装置 102において、 PTAユニット 321および 322は両者の間の境界において 互いに接続された表示電極対 2 (XI, Yl)〜(Xn, Υη)を有する。 ΡΤΑユニット 321 の η対の表示電極対 2 (XI, Υ1)〜(Χη, Υη)の X電極は、 ΡΤΑユニット 321の右辺 における前面支持基板 31の端部力もフレキシブル ·ケーブル 500FCを介して X電極 ドライバ回路基板 500上の X電極用の維持電圧パルス回路 50 (図 4)に接続される。 その Υ電極は、 ΡΤΑユニット 321の左辺と ΡΤΑユニット 322の右辺の間の境界上の 前面支持基板 31の部分からフレキシブル ·ケーブル 700FCを介して Υ電極ドライバ
回路 700の走査パルス回路 70に接続される。 Y電極ドライバ回路 700の Y電極高電 圧回路基板 600は、フレキシブル 'ケーブルを介して走査パルス回路 70に接続され る。 PTAユニット 321の m本の信号電極 3 Al〜Amは、 PTAユニット 321の底辺に おける背面支持基板 32の端部からフレキシブル 'ケーブル 46FCを介して PTAュ- ット 321のアドレス 'ドライバ回路 46に接続される。 In display device 102, PTA units 321 and 322 have display electrode pairs 2 (XI, Yl) to (Xn, Υη) connected to each other at the boundary between them. X Display electrode pair 2 (XI, Υ1) to (Χη, Υη) of ΡΤΑ unit 321 has an X-electrode via the flexible cable 500FC. It is connected to the sustain voltage pulse circuit 50 (FIG. 4) for the X electrode on the driver circuit board 500. The Υ electrode is connected to the 支持 electrode driver from the part of the front support board 31 on the boundary between the left side of ΡΤΑ unit 321 and the right side of ΡΤΑ unit 322 via flexible cable 700FC. Connected to scan pulse circuit 70 of circuit 700. The Y electrode high voltage circuit board 600 of the Y electrode driver circuit 700 is connected to the scan pulse circuit 70 through a flexible cable. The m signal electrodes 3 Al to Am of the PTA unit 321 are flexible from the end of the rear support board 32 at the bottom of the PTA unit 321 to the flexible 'cable 46FC address of the PTA unit 321 to the driver circuit 46 Connected.
[0042] ドライバ制御回路 42が、 X電極ドライバ回路基板 500、 Y電極ドライバ回路 700の Y 電極高電圧回路基板 600、および PTAユニット 321のアドレス 'ドライバ回路 46にそ れぞれのケーブルを介して接続される。 PTAユニット 321の背面には、さら〖こ、各回 路 42、 46、 500および 700に電力を供給する電源(PS) 40が設けられている。 PTA ユニット 322の m本の信号電極 3 Al〜Amは、 PTAユニット 322の底辺における背 面支持基板 32の端部からフレキシブル 'ケーブル 46FCを介して PTAユニット 322 のアドレス 'ドライバ回路 46に接続される。ドライバ制御回路 42は、さらに、一点鎖線 で示されたケーブルを介して PTAユニット 322のアドレス 'ドライバ回路 46に接続さ れる。 [0042] The driver control circuit 42 is connected to the X electrode driver circuit board 500, the Y electrode high voltage circuit board 600 of the Y electrode driver circuit 700, and the address' driver circuit 46 of the PTA unit 321 via respective cables. Connected. On the back of the PTA unit 321, there is a power supply (PS) 40 that supplies power to Sarakuko, circuits 42, 46, 500 and 700. The m signal electrodes 3 Al to Am of the PTA unit 322 are connected to the driver circuit 46 at the address of the PTA unit 322 via the flexible cable 46FC from the end of the back support board 32 at the bottom of the PTA unit 322. . The driver control circuit 42 is further connected to the address' driver circuit 46 of the PTA unit 322 via a cable indicated by a one-dot chain line.
[0043] 走査パルス回路 70はその走査電圧パルス Vyを PTAユニット 321と 322の間の 境界において長さ 2Lyの Y電極のうちの長さ Lyの 2つの部分に並列にそれぞれ印加 するので、その境界からの Y電極の長さは PTAユニット 321と 322の各々の横幅 Ly に等しく、図 9の場合(2Ly)の 2分の 1である。従って、走査パルス回路 70の走查電 圧パルスが印加される境界上の Y電極の部分力 最も遠い位置にある PTAユニット 321および 322の各々における Y電極の部分の放電セルでは、走査電圧パルス—V yの実効的な幅および高さが充分なので、アドレス放電に成功する可能性が高くなる [0043] The scanning pulse circuit 70 applies the scanning voltage pulse Vy in parallel to two portions of the length Ly of the 2Ly Y electrode at the boundary between the PTA units 321 and 322. The length of the Y electrode from is equal to the horizontal width Ly of each of the PTA units 321 and 322, which is half that of (2Ly) in FIG. Therefore, the partial force of the Y electrode on the boundary to which the scanning voltage pulse of the scan pulse circuit 70 is applied. In the discharge cell of the Y electrode portion in each of the PTA units 321 and 322 at the farthest position, the scan voltage pulse— The effective width and height of V y are sufficient, so the possibility of successful address discharge increases
[0044] 図 10は、本発明の別の実施形態による、表示装置 104における、 PTAユニット 32 1の背面右側および PTAユニット 327の背面左側の 2つの X電極ドライバ回路基板 5 00、 PTAユニット 321の背面左側の Y電極ドライバ回路 700、および PTAユニット 3 21および 322の背面下側の 2つのアドレス電極ドライバ回路(AD) 46の電気的接続 の例を示している。 [0044] FIG. 10 shows two X electrode driver circuit boards 500, PTA unit 321 on the right rear side of PTA unit 321 and the left rear side of PTA unit 327 in display device 104, according to another embodiment of the present invention. An example of the electrical connection of the Y electrode driver circuit 700 on the left side of the back side and the two address electrode driver circuits (AD) 46 on the lower side of the back side of the PTA units 321 and 322 is shown.
[0045] 表示装置 104において、 PTAユニット 321および 327は両者の間の境界において
互いに接続された表示電極対 2 (XI, Yl)〜(Xn, Υη)を有する。 ΡΤΑユニット 321 に関する X電極ドライバ回路基板 500、 Υ電極ドライバ回路 700およびアドレス電極ド ライバ回路 (AD) 46の電気的接続は、図 9の場合と同様である。 ΡΤΑユニット 327の η対の表示電極 2 (XI, Υ1)〜(Χη, Υη)の X電極は、 ΡΤΑユニット 327の左辺にお ける前面支持基板 31の端部からフレキシブル ·ケーブル 500FCを介して ΡΤΑュ-ッ ト 327の背面の X電極ドライバ回路基板 500に接続される。 ΡΤΑユニット 327の m本 の信号電極 3 Al〜Amは、 PTAユニット 327の底辺における背面支持基板 32の端 部からフレキシブル ·ケーブル 46FCを介して PTAユニット 327のアドレス ·ドライバ回 路 46に接続される。ドライバ制御回路 42は、さらに、一点鎖線で示されたケーブルを 介して PTAユニット 322の X電極ドライバ回路基板 500およびアドレス 'ドライバ回路 46に接続される。 [0045] In the display device 104, the PTA units 321 and 327 are at the boundary between them. The display electrode pairs 2 (XI, Yl) to (Xn, Υη) are connected to each other. The electrical connection of the X electrode driver circuit board 500, the Υ electrode driver circuit 700, and the address electrode driver circuit (AD) 46 related to the ΡΤΑ unit 321 is the same as in FIG. The X electrodes of the η pair of display electrodes 2 (XI, Υ1) to (Χη, Υη) of the unit 327 are connected via the flexible cable 500FC from the end of the front support board 31 on the left side of the unit 327 Connected to the X electrode driver circuit board 500 on the back of the boot 327. M m signal electrodes 3 Al to Am of unit 327 are connected to the address and driver circuit 46 of the PTA unit 327 through the flexible cable 46FC from the end of the back support board 32 at the bottom of the PTA unit 327 . The driver control circuit 42 is further connected to the X electrode driver circuit board 500 and the address' driver circuit 46 of the PTA unit 322 via a cable indicated by a one-dot chain line.
[0046] 走査パルス回路 70はその走査電圧パルス Vyを PTAユニット 321と 327の間の 境界において長さ 2Lyの Y電極のうちの長さ Lyの 2つの部分にそれぞれ印加するの で、その境界からの Y電極の長さは PTAユニット 321と 327の各々の横幅 Lyに等し い。従って、走査パルス回路 70の走査電圧パルスが印加される境界上の Y電極の部 分から最も遠い位置にある PTAユニット 321および 327の各々における Y電極の部 分の放電セルでは、走査電圧パルス Vyの実効的な幅および高さが充分なので、 アドレス放電に成功する可能性が高くなる。 [0046] The scanning pulse circuit 70 applies the scanning voltage pulse Vy to the two portions of the length Ly of the 2Ly Y electrode at the boundary between the PTA units 321 and 327. The length of the Y electrode is equal to the width Ly of each of the PTA units 321 and 327. Therefore, in the discharge cell of the Y electrode portion in each of the PTA units 321 and 327 located farthest from the Y electrode portion on the boundary where the scan voltage pulse of the scan pulse circuit 70 is applied, the scan voltage pulse Vy Since the effective width and height are sufficient, the possibility of successful address discharge is increased.
[0047] 図 11は、本発明のさらに別の実施形態による、表示装置 106における、 PTAュ- ット 33の背面右側の X電極ドライバ回路基板 500、 PTAユニット 331の背面左側の Y 電極ドライバ回路 700、および PTAユニット 331および 332の背面下側の 2つのアド レス電極ドライバ回路 (AD) 46の電気的接続の例を示して 、る。 FIG. 11 shows an X electrode driver circuit board 500 on the rear right side of the PTA unit 33 and a Y electrode driver circuit on the rear left side of the PTA unit 331 in the display device 106 according to still another embodiment of the present invention. An example of the electrical connection of 700 and two address electrode driver circuits (AD) 46 on the lower back side of PTA units 331 and 332 is shown.
[0048] 表示装置 106において、 PTAユニット 331および 332は両者の間の境界において 互いに接続された表示電極対 2 (XI, Yl)〜(Xn, Υη)を有する。 ΡΤΑユニット 331 に関する Υ電極ドライバ回路 700およびアドレス電極ドライバ回路 (AD) 46の電気的 接続は、図 9の ΡΤΑユニット 321と同様である。この場合、 ΡΤΑユニット 331の背面に は X電極ドライバ回路基板 500が配置されて!ヽな 、。 ΡΤΑユニット 332の η対の表示 電極 2 (XI, Υ1)〜(Χη, Υη)の X電極は、 ΡΤΑユニット 331の左辺と ΡΤΑユニット 3
32の右辺の間の境界上の前面支持基板 31の部分からフレキシブル ·ケーブル 500 FCを介して PTAユニット 332の背面の X電極ドライバ回路基板 500に接続される。 P TAユニット 332の m本の信号電極 3 Al〜Amは、 PTAユニット 332の底辺における 背面支持基板 32の端部力も PTAユニット 321のアドレス 'ドライバ回路 46に接続さ れる。ドライバ制御回路 42は、さら〖こ、一点鎖線で示されたケーブルを介して PTAュ ニット 322の X電極ドライバ回路基板 500およびアドレス 'ドライバ回路 46に接続され る。 In display device 106, PTA units 331 and 332 have display electrode pairs 2 (XI, Yl) to (Xn,, η) connected to each other at the boundary between them. The electrical connection between the electrode driver circuit 700 and the address electrode driver circuit (AD) 46 related to the unit 331 is the same as that of the unit 321 in FIG. In this case, the X electrode driver circuit board 500 is placed on the back of the unit 331. Display of η pair of ΡΤΑ unit 332 The X electrode of electrode 2 (XI, Υ1) to (Χη, Υη) is connected to the left side of ΡΤΑ unit 331 and ΡΤΑ unit 3 The front support board 31 on the boundary between the right sides of 32 is connected to the X electrode driver circuit board 500 on the back side of the PTA unit 332 via the flexible cable 500 FC. The m signal electrodes 3 Al to Am of the PTA unit 332 are also connected to the address “driver circuit 46” of the PTA unit 321 in the end force of the back support substrate 32 at the bottom of the PTA unit 332. The driver control circuit 42 is connected to the X electrode driver circuit board 500 of the PTA unit 322 and the address' driver circuit 46 via a cable indicated by a one-dot chain line.
[0049] 走査パルス回路 70はその走査電圧パルス Vyを PTAユニット 331と 332の間の 境界において長さ 2Lyの Y電極のうちの長さ Lyの 2つの部分にそれぞれ印加するの で、その境界からの Y電極の長さは PTAユニット 331と 332の各々の横幅 Lyに等し い。従って、走査パルス回路 70の走査電圧パルスが印加される境界上の Y電極の部 分から最も遠い位置にある PTAユニット 331および 332の各々における Y電極の部 分の放電セルでは、走査電圧パルス Vyの実効的な幅および高さが充分なので、 アドレス放電に成功する可能性が高くなる。 [0049] Scan pulse circuit 70 applies the scan voltage pulse Vy to two portions of length Ly of length 2Ly at the boundary between PTA units 331 and 332. The length of the Y electrode is equal to the width Ly of each of the PTA units 331 and 332. Therefore, in the discharge cell of the Y electrode portion in each of the PTA units 331 and 332 located farthest from the Y electrode portion on the boundary to which the scan voltage pulse of the scan pulse circuit 70 is applied, the scan voltage pulse Vy Since the effective width and height are sufficient, the possibility of successful address discharge is increased.
[0050] 図 12Aおよび 12Bは、図 11の隣接する 2つの PTAユニット 331と 332の境界にお いて前面支持基板 31の内面上の表示電極対 2から、走査パルス回路 70および Zま たは X電極ドライバ回路基板 500への接続線 22を引き出す方法を示している。 Y電 極の接続線 22はフレキシブル 'ケーブル 70FC上に形成される。 X電極の接続線 22 はフレキシブル 'ケーブル 500FC上に形成される。 [0050] FIGS. 12A and 12B show scanning pulse circuits 70 and Z or X from the display electrode pair 2 on the inner surface of the front support substrate 31 at the boundary between two adjacent PTA units 331 and 332 in FIG. The method of drawing out the connection line 22 to the electrode driver circuit board 500 is shown. The Y electrode connection line 22 is formed on the flexible cable 70FC. The X electrode connection line 22 is formed on the flexible cable 500FC.
[0051] 図 12Aにおいて、別個の PTAユニット 332の前面支持基板 31の右辺からプラズマ •チューブ 11Bの外面に沿って背面支持基板 32の下側へ延びるように、前面支持基 板 31上のそれぞれの表示電極対 2に接続する接続線 22を形成する。次いで、図 12 Bに示すように、 PTAユニット 321と PTAユニット 332の対応する表示電極対 22を互 いに接触するように、 PTAユニット 331の左辺を PTAユニット 332の右辺に接続して 、継ぎ目が目立たないようにする。表示電極 2の中の Y電極から引き出された接続線 22は、フレキシブル 'ケーブル 70FC (図 11)を介して PTAユニット 331の背面左側 に配置された走査パルス回路 70に接続される。表示電極対 2の中の X電極から引き 出された接続線 22は、フレキシブル 'ケーブル 500FC (図 11)を介して PTAユニット
332の背面右側に配置された X電極ドライバ回路基板 500に接続される。代替構成 として、表示電極対 2の中の X電極 2は、図 9および 10に示されているように、 PTAュ ニット 331の右辺および Zまたは PTAユニット 332の左辺においてフレキシブル 'ケ 一ブル 500FCを介して、対応する X電極ドライバ回路基板 500に接続してもよ 、。 [0051] In FIG. 12A, each of the front support substrates 31 on the front support substrate 31 extends from the right side of the front support substrate 31 of the separate PTA unit 332 to the lower side of the rear support substrate 32 along the outer surface of the plasma tube 11B. A connection line 22 connected to the display electrode pair 2 is formed. Next, as shown in FIG. 12B, the left side of the PTA unit 331 is connected to the right side of the PTA unit 332 so that the corresponding display electrode pairs 22 of the PTA unit 321 and the PTA unit 332 are in contact with each other. Make it inconspicuous. The connection line 22 drawn from the Y electrode in the display electrode 2 is connected to the scan pulse circuit 70 disposed on the left side of the back surface of the PTA unit 331 via a flexible cable 70FC (FIG. 11). The connection line 22 drawn from the X electrode in the display electrode pair 2 is connected to the PTA unit via the flexible cable 500FC (Fig. 11). It is connected to an X electrode driver circuit board 500 arranged on the right side of the back surface of 332. As an alternative configuration, the X electrode 2 in the display electrode pair 2 has a flexible 'cable 500FC on the right side of the PTA unit 331 and the left side of the PTA unit 332 as shown in Figs. 9 and 10. You can connect to the corresponding X electrode driver circuit board 500 via.
[0052] 図 13は、本発明のさらに別の実施形態による、表示装置 108の隣接する 4つの PT Aユニット 331、 332、 326および 327の背面における 2つの X電極ドライバ回路基板 500、 2つの Y電極ドライバ回路 700、および 4つのアドレス電極ドライバ回路(AD) 4 6の電気的接続の例を示して 、る。 [0052] FIG. 13 illustrates two X electrode driver circuit boards 500, two Ys on the back of four adjacent PT A units 331, 332, 326, and 327 of a display device 108, according to yet another embodiment of the invention. An example of electrical connection of the electrode driver circuit 700 and four address electrode driver circuits (AD) 46 is shown.
[0053] 表示装置 108【こお!ヽて、 PTAユニット 331、 332、 326および 327ίまそれぞれの境 界において互いに接続された表示電極対 2 (XI, Υ1)〜(Χη, Υη)を有する。 ΡΤΑ ユニット 331および 332における接続は図 9の場合と同様である。 ΡΤΑユニット 327 における接続は図 10の場合と同様である。 ΡΤΑユニット 326に関する Υ電極ドライバ 回路 700の電気的接続は、図 11の ΡΤΑユニット 331の場合と同様である。この場合 、 ΡΤΑユニット 326の背面には、電源 40およびドライバ制御回路 42が配置されてい ない。 The display device 108 has display electrode pairs 2 (XI, Υ1) to (Χη, Υη) connected to each other at the boundaries of the PTA units 331, 332, 326, and 327ί.接 続 Connections in units 331 and 332 are the same as in Fig. 9. The connection at ΡΤΑunit 327 is the same as in Fig.10. The electrical connection of Υ electrode driver circuit 700 for ΡΤΑ unit 326 is the same as that of ΡΤΑ unit 331 in Fig. 11. In this case, the power supply 40 and the driver control circuit 42 are not arranged on the back surface of the ΡΤΑ unit 326.
[0054] ΡΤΑユニット 331の走査パルス回路 70はその走査電圧パルス—Vyを ΡΤΑュ-ッ ト 331と 332の間の境界において長さ 4Lyの Y電極のうちの長さ Lyの 2つの部分にそ れぞれ印加するので、その境界からの Y電極の長さは PTAユニット 331と 332の各 々の横幅 Lyに等しい。 PTAユニット 326の走査パルス回路 70はその走査電圧パル ス一 Vyを PTAユニット 326と 327の間の境界において長さ 4Lyの Y電極のうちの長 さ Lyの 2つの部分にそれぞれ印加するので、その境界からの Y電極の長さは PTAュ ニット 326と 327の各々の横幅 Lyに等しい。従って、走査パルス回路 70の走査電圧 パルスが印加される境界上の γ電極の部分から最も遠い位置にある PTAユニット 33 1、 332、 326および 327の各々における Y電極の部分の放電セルでは、走査電圧 パルス Vyの実効的な幅および高さが充分なので、アドレス放電に成功する可能性 が高くなる。 [0054] The scan pulse circuit 70 of the unit 331 applies its scan voltage pulse -Vy to two portions of the length Ly of the 4Ly Y electrode at the boundary between the cuts 331 and 332. Since each is applied, the length of the Y electrode from the boundary is equal to the lateral width Ly of each of the PTA units 331 and 332. The scanning pulse circuit 70 of the PTA unit 326 applies the scanning voltage pulse 1 Vy to two portions of the length Ly of the Y electrode having a length of 4 Ly at the boundary between the PTA units 326 and 327. The length of the Y electrode from the boundary is equal to the width Ly of each of the PTA units 326 and 327. Therefore, in the discharge cell of the Y electrode portion in each of the PTA units 33 1, 332, 326, and 327 located farthest from the γ electrode portion on the boundary to which the scan voltage pulse of the scan pulse circuit 70 is applied, the scan is performed. Since the effective width and height of the voltage pulse Vy are sufficient, the possibility of successful address discharge is increased.
[0055] 図 14は、本発明のさらに別の実施形態による、表示装置 110の隣接する 5つの PT Aユニット 321、 322、 325、 326および 327の背面における 2つの X電極ドライノ 回
路基板 500、 2つの Y電極ドライバ回路 700、および 5つのアドレス電極ドライバ回路( AD) 46の電気的接続の例を示して 、る。 [0055] FIG. 14 illustrates two X-electrode dryno cycles on the back of five adjacent PTA units 321, 322, 325, 326, and 327 of display device 110, according to yet another embodiment of the present invention. An example of the electrical connection of a road substrate 500, two Y electrode driver circuits 700, and five address electrode driver circuits (AD) 46 is shown.
[0056] 表示装置 110【こお!ヽて、 ΡΤΑユニット 321、 322、 325、 326および 327ίまそれぞ れの境界において互いに接続された表示電極対 2 (XI, Υ1)〜(Χη, Υη)を有する 。 ΡΤΑユニット 311および 312における接続は図 9の場合と同様である。 ΡΤΑュ-ッ ト 326および 327における接続は図 13の場合と同様である。 ΡΤΑユニット 325にお ける接続は図 9の ΡΤΑユニット 322の場合と同様である。 [0056] Display device 110 [This is a display electrode pair 2 (XI, Υ1) to (Χη, Υη) connected to each other at the boundaries of units 321, 322, 325, 326, and 327ί. Have The connections in the dredge units 311 and 312 are the same as in FIG. The connections in units 326 and 327 are the same as in FIG. The connection at ΡΤΑunit 325 is the same as that of ΡΤΑunit 322 in Fig. 9.
[0057] ΡΤΑユニット 321の走査パルス回路 70はその走査電圧パルス—Vyを ΡΤΑュ-ッ ト 321と 322の間の境界において長さ 4Lyの Y電極のうちの長さ Lyおよび 1. 5Lyの 2つの部分にそれぞれ印加するので、その境界力もの Y電極のそれぞれの部分の長 さは PTAユニット 331の横幅 Lyと 1. 5Lyに等しい。 PTAユニット 326の走査パルス 回路 70はその走査電圧パルス—Vyを PTAユニット 326と 327の間の境界において 長さ 4Lyの Y電極のうちの長さ Lyおよび 1. 5Lyの 2つの部分にそれぞれ印加するの で、その境界からの Y電極のそれぞれの部分の長さは PTAユニット 327の横幅 Lyと 1. 5Lyに等しい。従って、走査パルス回路 70の走査電圧パルスが印加される境界 上の Y電極の咅分力、ら最も遠!ヽ位置にある PTAュニッ卜 321、 322、 325、 326およ び 327の各々における Y電極の部分の放電セルでは、走査電圧パルス Vyの実効 的な幅および高さが充分なので、アドレス放電に成功する可能性が高くなる。 [0057] The scan pulse circuit 70 of the unit 321 generates its scan voltage pulse—Vy at the boundary between the mute 321 and 322, with the lengths Ly and 1.5Ly of the 4Ly Y electrodes. Since each part is applied to each part, the length of each part of the Y electrode is equal to the width Ly of the PTA unit 331 and 1.5 Ly. The scan pulse circuit 70 of the PTA unit 326 applies its scan voltage pulse—Vy to the two parts of length Ly and 1.5Ly of the 4Ly Y electrode at the boundary between the PTA units 326 and 327, respectively. Therefore, the length of each part of the Y electrode from the boundary is equal to the lateral width Ly and 1.5Ly of the PTA unit 327. Therefore, the Y component on the boundary where the scan voltage pulse of the scan pulse circuit 70 is applied, and the Y in each of the PTA units 321, 322, 325, 326 and 327 at the farthest position In the discharge cell of the electrode portion, the effective width and height of the scanning voltage pulse Vy are sufficient, so the possibility of successful address discharge is increased.
[0058] 図 15は、本発明のさらに別の実施形態による、表示装置 112の隣接する 6つの PT Aユニット 321、 322、 324、 325、 326および 327の背面における 2つの X電極ドライ バ回路基板 500、 3つの Y電極ドライバ回路 700、および 6つのアドレス電極ドライバ 回路 (AD) 46の電気的接続の例を示して 、る。 [0058] FIG. 15 shows two X electrode driver circuit boards on the back of six adjacent PTA units 321, 322, 324, 325, 326 and 327 of the display device 112, according to yet another embodiment of the present invention. Examples of electrical connections for 500, three Y electrode driver circuits 700, and six address electrode driver circuits (AD) 46 are shown.
[0059] 表示装置 112【こお!ヽて、 PTAユニット 321、 322、 324、 325、 326および 327ίまそ れぞれの境界において互いに接続された表示電極対 2 (XI, Υ1)〜(Χη, Υη)を有 する。 ΡΤΑユニット 321および 322は図 13の場合と同様である。 ΡΤΑユニット 325、 326および 327における接続は図 13の場合と同様である。 ΡΤΑユニット 324におけ る接続は ΡΤΑユニット 326と同様である。 [0059] Display device 112 [This is a display electrode pair 2 (XI, Υ1) to (Χη,) connected to each other at the boundaries of PTA units 321, 322, 324, 325, 326, and 327ί. Υη). ΡΤΑ Units 321 and 322 are the same as in FIG. The connections in dredging units 325, 326 and 327 are the same as in FIG. The connection in ΡΤΑunit 324 is the same as that in ΡΤΑunit 326.
[0060] ΡΤΑユニット 331、 324および 326の走査パルス回路 70は、その走査電圧パルス
Vyを隣接する 2つの PTAユニット 331と 332、 324と 325、および 326と 327の間 の境界にぉ 、て、長さ 4Lyの Y電極のうちの長さ Lyの 2つの部分にそれぞれ印加す るので、その境界力もの Y電極の長さは PTAュ-ッ卜 321、 322、 324、 325、 326お よび 327の各々の横幅 Lyに等しい。従って、走査パルス回路 70の走査電圧パルス が印加される境界上の Y電極の部分から最も遠い位置にある PTAユニット 321、 32 2、 324、 325、 326および 327の各々における Y電極の咅分の放電セノレでは、走査 電圧パルス Vyの実効的な幅および高さが充分なので、アドレス放電に成功する可 能性が高くなる。 [0060] Scanning pulse circuit 70 of ΡΤΑ units 331, 324 and 326 Apply Vy to the boundary between the two adjacent PTA units 331 and 332, 324 and 325, and 326 and 327, and apply them to the two parts of the length Ly of the 4Ly Y electrode respectively. Therefore, the length of the Y electrode of the boundary force is equal to the lateral width Ly of each of the PTA modules 321, 322, 324, 325, 326 and 327. Therefore, the apportioning of the Y electrode in each of the PTA units 321, 32 2, 324, 325, 326 and 327 located farthest from the portion of the Y electrode on the boundary where the scan voltage pulse of the scan pulse circuit 70 is applied. In the discharge senor, the effective width and height of the scanning voltage pulse Vy are sufficient, so the possibility of successful address discharge increases.
[0061] 図 16は、図 13、 14および 15の 2組以上の走査パルス回路 70の走査パルスの同期 をとるための走査パルス波形を説明するのに役立つ。 [0061] FIG. 16 serves to illustrate the scan pulse waveforms for synchronizing the scan pulses of the two or more sets of scan pulse circuits 70 of FIGS.
[0062] アドレス放電の誤りを防止するためには、ドライバ制御回路 42によって制御される 図 13の PTAユニット 331および 326の 2組の走査パルス回路 70の走査パルス間の 同期、ドライバ制御回路 42によって制御される図 14の PTAユニット 321および 326 の 2組の走査パルス回路 70の走査パルス間の同期、またはドライバ制御回路 42によ つて制御される図 15の PTAユニット 321、 324および 326の 3組の走査パルス回路 7 0の走査パルス間の同期のずれを防止する必要がある。 [0062] In order to prevent an error in address discharge, synchronization between the scan pulses of the two scan pulse circuits 70 of the PTA units 331 and 326 of Fig. 13 controlled by the driver control circuit 42, and by the driver control circuit 42 14 PTA units 321 and 326 of Fig. 14 to be controlled Synchronized between scan pulses of 70, or 3 sets of PTA units 321, 324 and 326 of Fig. 15 controlled by driver control circuit 42 Therefore, it is necessary to prevent the synchronization deviation between the scan pulses of the scan pulse circuit 70.
[0063] 図 13〜15の各々における任意の 2組の走査パルス回路 70の一方を走査パルス回 路 Aとし、その他方を走査パルス回路 Bとする。走査パルス回路 Aおよび Bの走査パ ルスは、 Y電極 Yjの走査パルス期間において走査パルス'オン期間 Taを有し、ァドレ スのための走査電圧パルスの最小値 Vyの期間 Tbおよび Tb, (Tb=Tb' )をそれ ぞれ有する。 Y電極 Yjの走査パルス期間 Taにおいて、 Y電極 Yj以外の Y電極につ V、て走査パルス回路 Aの走査パルスは図 16Eのように走査パルス ·オフ状態を有す る。 One of two arbitrary sets of scan pulse circuits 70 in each of FIGS. 13 to 15 is a scan pulse circuit A, and the other is a scan pulse circuit B. The scan pulses of the scan pulse circuits A and B have a scan pulse 'on period Ta in the scan pulse period of the Y electrode Yj, and the periods Tb and Tb, (Tb = Tb '). In the scan pulse period Ta of the Y electrode Yj, the scan pulse of the scan pulse circuit A is in the scan pulse OFF state as shown in FIG. 16E for each Y electrode other than the Y electrode Yj.
[0064] 走查パノレス回路 Bの図 16Bの走查パノレスは、走查パノレス回路 Aの図 16Aの走查パ ルスより最大で遅延時間 D=Ttだけ遅延するものとする。 1組の走査パルス回路 Aに よって選択された Y電極 Yjが実効的にオン状態になるべき図 16Cの期間 Tbと、別の 1組の走査パルス回路 Bによって選択されたその前後の Y電極 Yj— 1または Yj + 1が 実効的にオン状態になるべき図 16Dの期間 Tb'と力 一方の走査パルスの遅延によ
つて重ならないように、オン状態とオフ状態の間の遷移に、パルス遅延時間 Dを考慮 した余裕期間 Ttを設ける必要がある。従って、走査パルスは、最初の余裕期間 Ttに おいて接地電位 GND力 電位 Vyに立ち下がる傾斜(ランプ)を有し、 2番目の余 裕期間 Ttにおいて電位—Vy力 接地電位 GNDに立ち上がる傾斜を有する。 It is assumed that the running panorace in FIG. 16B of the running panorace circuit B is delayed by a delay time D = Tt at the maximum from the running pulse of FIG. 16A in the running panorace circuit A. The Y electrode Yj selected by one set of scan pulse circuits A should be effectively turned on, the period Tb in FIG. 16C, and the Y electrodes Yj before and after that selected by another set of scan pulse circuits B — 1 or Yj + 1 should be effectively turned on Period Tb 'and force in Fig. 16D Due to the delay of one scan pulse In order not to overlap, it is necessary to provide a margin period Tt considering the pulse delay time D at the transition between the on state and the off state. Therefore, the scan pulse has a slope (ramp) that falls to the ground potential GND force potential Vy in the first margin period Tt, and a slope that rises to the potential-Vy force ground potential GND in the second margin period Tt. Have.
[0065] 以上説明した実施形態は典型例として挙げたに過ぎず、その各実施形態の構成要 素を組み合わせること、その変形およびバリエーションは当業者にとって明らかであり 、当業者であれば本発明の原理および請求の範囲に記載した発明の範囲を逸脱す ることなく、実施形態の種々の変形を行えることは明らかである。 [0065] The embodiment described above is merely given as a typical example, and it is obvious for those skilled in the art to combine the constituent elements of each embodiment, and variations and variations thereof. Obviously, various modifications can be made to the embodiments without departing from the scope of the invention as set forth in the principles and claims.
図面の簡単な説明 Brief Description of Drawings
[0066] [図 1]図 1は、通常のカラー表示装置のプラズマ ·チューブまたはガス放電管のアレイ の概略的な部分的構造を例示して 、る。 [0066] FIG. 1 illustrates a schematic partial structure of an array of plasma tubes or gas discharge tubes of a conventional color display device.
[図 2]図 2Aは、透明な複数の表示電極対が形成された前面側支持基板を示している 。図 2Bは、複数の信号電極または信号電極が形成された背面側支持基板を示して いる。 FIG. 2A shows a front-side support substrate on which a plurality of transparent display electrode pairs are formed. FIG. 2B shows a backside support substrate on which a plurality of signal electrodes or signal electrodes are formed.
[図 3]図 3は、表示装置のプラズマ ·チューブ 'アレイの管の長手方向に垂直な断面の 構造を示している。 [FIG. 3] FIG. 3 shows the structure of a cross section perpendicular to the longitudinal direction of the tube of the plasma tube array of the display device.
[図 4]図 4は、通常の表示装置の PTAユニットの背面における X電極ドライバ回路基 板、 Y電極ドライバ回路、アドレス電極ドライバ回路、およびドライバ制御回路の電気 的接続を示している。 [FIG. 4] FIG. 4 shows the electrical connections of the X electrode driver circuit board, the Y electrode driver circuit, the address electrode driver circuit, and the driver control circuit on the back of the PTA unit of a normal display device.
[図 5]図 5は、 PTAユニットに接続された、通常の Y電極ドライバ回路における Y電極 用の維持電圧パルス回路および走査パルス回路と、 X電極ドライバ回路基板上の X 電極用の維持電圧パルス回路の概略的構成を示して!/ヽる。 [Fig. 5] Fig. 5 shows the sustain voltage pulse circuit and scan pulse circuit for the Y electrode in the normal Y electrode driver circuit connected to the PTA unit, and the sustain voltage pulse for the X electrode on the X electrode driver circuit board. Show the schematic configuration of the circuit!
[図 6]図 6は、通常の表示装置における、 X電極ドライバ回路基板、 Y電極ドライバ回 路およびアドレス 'ドライバ回路の出力駆動電圧波形の概略的な駆動シーケンスを例 示している。 FIG. 6 shows an example of a schematic drive sequence of output drive voltage waveforms of an X electrode driver circuit board, a Y electrode driver circuit, and an address' driver circuit in a normal display device.
[図 7]図 7は、通常の表示装置の隣接配置された 2つの PTAユニットの背面における X電極ドライバ回路基板、 Y電極ドライバ回路および 2つのアドレス電極ドライバ回路 の電気的接続を示している。
[図 8]図 8は、表示装置の隣接する 2つの PTAユニットにわたって延びる表示電極対 のうちの走査電極 Yjの長手方向に沿った走査電圧パルス Vyの波形を示している [FIG. 7] FIG. 7 shows the electrical connection of the X electrode driver circuit board, the Y electrode driver circuit, and the two address electrode driver circuits on the back of two PTA units arranged adjacent to each other in a normal display device. [FIG. 8] FIG. 8 shows the waveform of the scanning voltage pulse Vy along the longitudinal direction of the scanning electrode Yj of the pair of display electrodes extending across two adjacent PTA units of the display device.
[図 9]図 9は、本発明の実施形態による、表示装置における、 PTAユニットの背面右 側の X電極ドライバ回路基板、 PTAユニットの背面左側の Y電極ドライバ回路、およ び PTAユニットの背面下側の 2つのアドレス電極ドライバ回路の電気的接続の例を 示している。 [FIG. 9] FIG. 9 is a diagram illustrating an X electrode driver circuit board on the right rear side of the PTA unit, a Y electrode driver circuit on the left rear side of the PTA unit, and a rear surface of the PTA unit in the display device according to the embodiment of the present invention. An example of the electrical connection of the lower two address electrode driver circuits is shown.
[図 10]図 10は、本発明の別の実施形態による、表示装置における、 PTAユニットの 背面右側および PTAユニットの背面左側の 2つの X電極ドライバ回路基板、 PTAュ ニットの背面左側の Y電極ドライバ回路、および PTAユニットの背面下側の 2つのァ ドレス電極ドライバ回路の電気的接続の例を示している。 FIG. 10 shows two X electrode driver circuit boards on the right rear side of the PTA unit and the left rear side of the PTA unit, and the Y electrode on the rear left side of the PTA unit in the display device according to another embodiment of the present invention. An example of the electrical connection of the driver circuit and the two address electrode driver circuits on the lower back side of the PTA unit is shown.
[図 11]図 11は、本発明のさらに別の実施形態による、表示装置における、 PTAュ- ットの背面右側の X電極ドライバ回路基板、 PTAユニットの背面左側の Y電極ドライ バ回路、および PTAユニットの背面下側の 2つのアドレス電極ドライバ回路の電気的 接続の例を示している。 [FIG. 11] FIG. 11 is a diagram showing an X electrode driver circuit board on the right rear side of the PTA unit, a Y electrode driver circuit on the left rear side of the PTA unit, and a display device according to still another embodiment of the present invention. An example of the electrical connection of the two address electrode driver circuits on the lower back side of the PTA unit is shown.
[図 12]図 12Aおよび 12Bは、図 11の隣接する 2つの PTAユニットの境界において前 面支持基板の内面上の表示電極対から走査パルス回路および Zまたは X電極ドライ バ回路基板への接続線を引き出す方法を示して ヽる。 [FIG. 12] FIGS. 12A and 12B show the connection lines from the display electrode pair on the inner surface of the front support substrate to the scan pulse circuit and the Z or X electrode driver circuit substrate at the boundary between two adjacent PTA units in FIG. Show me how to pull out.
[図 13]図 13は、本発明のさらに別の実施形態による、表示装置の隣接する 4つの PT FIG. 13 shows four adjacent PTs of a display device according to yet another embodiment of the present invention.
Aユニットの背面における 2つの X電極ドライバ回路基板、 2つの Y電極ドライバ回路Two X electrode driver circuit boards on the back of the A unit, two Y electrode driver circuits
、および 4つのアドレス電極ドライバ回路の電気的接続の例を示して 、る。 , And an example of the electrical connection of four address electrode driver circuits.
[図 14]図 14は、本発明のさらに別の実施形態による、表示装置の隣接する 5つの PT [FIG. 14] FIG. 14 shows five adjacent PTs of a display device according to still another embodiment of the present invention.
Aユニットの背面における 2つの X電極ドライバ回路基板、 2つの Y電極ドライバ回路Two X electrode driver circuit boards on the back of the A unit, two Y electrode driver circuits
、および 5つのアドレス電極ドライバ回路の電気的接続の例を示して 、る。 , And an example of the electrical connection of the five address electrode driver circuits.
[図 15]図 15は、本発明のさらに別の実施形態による、表示装置の隣接する 6つの PT [Fig. 15] Fig. 15 is a diagram showing six adjacent PTs of a display device according to still another embodiment of the present invention.
Aユニットの背面における 2つの X電極ドライバ回路基板、 3つの Y電極ドライバ回路Two X electrode driver circuit boards and three Y electrode driver circuits on the back of the A unit
、および 6つのアドレス電極ドライバ回路の電気的接続の例を示して 、る。 , And an example of the electrical connection of the six address electrode driver circuits.
[図 16]図 16は、図 13、 14および 15の 2組以上の走査パルス回路の走査パルスの同
期をとるための走査パルス波形を説明するのに役立つ。
[Fig. 16] Fig. 16 shows the same scan pulse of two or more sets of scan pulse circuits of Figs. 13, 14 and 15. This is useful for explaining the scanning pulse waveform for taking a period.
Claims
[1] 内部に、蛍光体層が形成されると共に放電ガスが封入され、長手方向に複数の発 光点をそれぞれ有する複数のガス放電管が並置され、前記複数のガス放電管の表 示面側に複数対の表示電極が配置され、前記複数のガス放電管の背面側に複数の 信号電極が配置された複数のユニットからなる表示装置であって、 [1] Inside, a phosphor layer is formed and a discharge gas is enclosed, and a plurality of gas discharge tubes each having a plurality of light emitting points in the longitudinal direction are juxtaposed, and a display surface of the plurality of gas discharge tubes A display device comprising a plurality of units, each having a plurality of pairs of display electrodes disposed on a side, and a plurality of signal electrodes disposed on a back side of the plurality of gas discharge tubes;
前記複数のユニットの前記複数対の表示電極は、前記複数のユニット分の長さを 有するように電気的に接続されており、 The plurality of pairs of display electrodes of the plurality of units are electrically connected to have a length corresponding to the plurality of units,
第 1の期間において前記複数のユニットの前記複数対の表示電極の各表示電極 対のうちの一方の表示電極に走査電圧パルスを印加し、第 2の期間において前記一 方の表示電極に維持電圧パルスを印加する少なくとも 1つの走査駆動回路と、 前記第 2の期間において前記複数のユニットの前記複数対の表示電極の各表示 電極対のうちの他方の表示電極に維持電圧パルス用の電位を印加する少なくとも 1 つの維持電圧回路と、 A scan voltage pulse is applied to one display electrode of each of the plurality of display electrode pairs of the plurality of units in the first period, and a sustain voltage is applied to the one display electrode in the second period. At least one scanning drive circuit for applying a pulse; and applying a potential for a sustain voltage pulse to the other display electrode of each of the plurality of display electrode pairs of the plurality of units in the second period At least one sustain voltage circuit to
を具え、 With
前記 1つの走査駆動回路は、前記複数のユニットの中の隣接する 2つのユニットの 間の境界において、前記複数対の表示電極の各表示電極対のうちの前記一方の表 示電極に走査電圧パルスを印加し、前記一方の表示電極に維持電圧パルスを印加 するものであることを特徴とする、表示装置。 The one scanning drive circuit is configured to apply a scanning voltage pulse to the one display electrode of each of the plurality of pairs of display electrodes at a boundary between two adjacent units of the plurality of units. And a sustain voltage pulse is applied to the one display electrode.
[2] 前記 1つの維持電圧回路は、前記複数のユニットの 1つの外側辺において前記他 方の表示電極に維持電圧パルスを印加することを特徴とする、請求項 1に記載の表 示装置。 [2] The display device according to claim 1, wherein the one sustain voltage circuit applies a sustain voltage pulse to the other display electrode on one outer side of the plurality of units.
[3] 前記 1つの維持電圧回路は、前記 2つのユニットの間の境界において前記他方の 表示電極に維持電圧パルスを印加することを特徴とする、請求項 1に記載の表示装 置。 [3] The display device according to [1], wherein the one sustain voltage circuit applies a sustain voltage pulse to the other display electrode at a boundary between the two units.
[4] 前記複数のユニットの中の 1つの外側のユニットは、その背面に、前記 1つの走査 駆動回路と前記 1つの維持電圧回路と、前記 1つの走査駆動回路と前記 1つの維持 電圧回路を制御する制御回路と、を有することを特徴とする、請求項 1乃至 3のいず れかに記載の表示装置。
前記複数の走査駆動回路の中の別の 1つの走査駆動回路は、前記複数のユニット の中の隣接する他の 2つのユニットの間の境界において、前記複数対の表示電極の 各表示電極対のうちの前記一方の表示電極に走査電圧パルスを印加し、前記一方 の表示電極に維持電圧パルスを印加し、 [4] One outer unit among the plurality of units has the one scanning drive circuit, the one sustain voltage circuit, the one scan drive circuit, and the one sustain voltage circuit on the rear surface thereof. 4. The display device according to claim 1, further comprising a control circuit that controls the display device. Another one of the plurality of scan driving circuits is arranged so that each display electrode pair of the plurality of pairs of display electrodes is arranged at a boundary between the other two adjacent units in the plurality of units. Applying a scan voltage pulse to one of the display electrodes, applying a sustain voltage pulse to the one display electrode,
前記 1つの走査駆動回路および前記別の 1つの走査駆動回路の各々の走査電圧 パルスは、他方の走査電圧パルスとの間の同期ずれを防止するための期間を、隣接 走査電圧パルス間に有するものであることを特徴とする、請求項 1に記載の表示装置
Each of the scan voltage pulses of the one scan drive circuit and the other one scan drive circuit has a period between adjacent scan voltage pulses to prevent a synchronization shift with the other scan voltage pulse. The display device according to claim 1, wherein
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