WO2007116437A1

WO2007116437A1 - Display apparatus

Info

Publication number: WO2007116437A1
Application number: PCT/JP2006/306635
Authority: WO
Inventors: Kenji Awamoto; Manabu Ishimoto; Hitoshi Hirakawa; Koji Shinohe
Original assignee: Shinoda Plasma Co., Ltd.
Priority date: 2006-03-30
Filing date: 2006-03-30
Publication date: 2007-10-18
Also published as: JPWO2007116437A1

Abstract

A display apparatus (104) has a first unit (10) and a second unit (12). The first unit (10) has m gas discharge lamps (111), ne pairs of display electrodes (X1-Xne, Y1-Yne), and m signal electrodes (A1-Am). The second unit (12) has m gas discharge lamps (112), nc pairs of display electrodes (X1-Xnc, Y1-Ync), and m signal electrodes (A1-Am). When a first scan voltage is applied to a particular display electrode (Y1) of the nc pairs of display electrodes during a first interval, a second address voltage circuit (402) applies, to the m signal electrodes of the second unit (12), a first set of address voltage pulses having a longer duration than the other address voltage pulses.

Description

Specification

Display device

Technical field

TECHNICAL FIELD [0001] The present invention relates to a large display device having a plurality of partial forces, and more particularly to application of a voltage to a signal electrode in accordance with the position of a display electrode of a plasma 'tube' array in the display device.

Background art

[0002] Plasma display panels (PDPs) emit light by exciting phosphors with ultraviolet light of 147nm, which generates plasma discharge in a closed discharge space of a large number of vertical and horizontal small cells, and discharges plasma power. Let The cell space is formed between two stacked glass sheets. On the other hand, in the plasma tube array (PTA) described in, for example, Japanese Patent Laid-Open No. 2003-92085 (A) (Patent Document 1), a phosphor layer is formed in an elongated glass glass tube. A large number of cell spaces are formed in the tube. By arranging a large number of such plasma tubes, a large display screen of, for example, 6 m x 3 m can be formed. In a normal plasma 'tube' array, the wall voltage due to the address voltage in the cells of the first scan line is often not sufficient, so the cells in the first line may not emit completely during the sustain voltage display period. .

Patent Document 1: Japanese Patent Laid-Open No. 2003-92085

Japanese Patent Laid-Open No. 10-171377 (Patent Document 2) (corresponding to Japanese Patent No. 3624596) describes an image display device. In the image display device, the driving substrate is connected to the display panel via a plurality of wiring substrates, and among the three wiring substrates adjacent to each other, the outermost electrode on the adjacent side of one wiring substrate is positioned outside. A dummy electrode connected to the outermost electrode on the adjacent side of the other wiring board is provided. As a result, even when the drive substrate is connected to the display panel using a plurality of wiring boards, the coupling capacitance between adjacent electrodes can be made uniform.

Japanese Unexamined Patent Publication No. 2003-29705 (Patent Document 3) describes a method of driving a plasma 'display' panel. In the driving method, the discharge space is within the effective display area. When a cell to be displayed is selected by applying a voltage of opposite polarity to the two electrodes facing each other across the electrode, it is constant during the address period in which the cell is selected for the dummy electrode arranged outside the effective display area. Supply voltage. As a result, abnormal discharge occurring at the upper and lower edges of the effective display area of the plasma 'display' panel is prevented. Japanese Patent Application Laid-Open No. 2004-37884 (Patent Document 4) describes a plasma display device. The plasma display device includes a first substrate on which a plurality of first electrodes and second electrodes forming a pair are arranged, and a plurality of third electrodes substantially orthogonal to the first electrode and the second electrode. And a second substrate disposed opposite to each other with the discharge space interposed therebetween. A panel is configured by providing at least one dummy electrode outside the display area on the first substrate so as to be parallel to the first electrode or the second electrode and substantially perpendicular to the third electrode. In the address period of at least one subfield of a plurality of subfields constituting one frame, the address pulse is applied to the dummy electrode prior to the address discharge in the first line, and the dummy electrode and the third electrode are applied. Discharge occurs between electrodes. As a result, the display quality of the plasma display device is improved.

Patent Document 2: Japanese Patent Laid-Open No. 10-171377

Patent Document 3: Japanese Patent Laid-Open No. 2003-29705

Patent Document 4: Japanese Patent Application Laid-Open No. 2004-37884

Disclosure of the invention

Problems to be solved by the invention

For example, a large plasma tube array display with a height of 2 m can be stretched by two plasma 'tube' arrays each having a height of 1 m. However, in the first cell of the address discharge at one end of each one plasma tube, the wall voltage is not sufficiently formed by the address discharge, so that the sustain discharge may not occur. If the first address discharge in one plasma tube array occurs in a cell in a line near the joint between the tube ends of the two plasma tube arrays, many sustain discharge failures or errors occur in that line. This is a nuisance for those who view the display device. To prevent the sustain discharge failure, if the address voltage generation circuit is configured to increase only the address discharge voltage of the first cell in the plasma tube, The cost of the dressing voltage generation circuit increases.

The inventors reduced the number of display electrode pairs in one plasma tube array of two plasma tube arrays to be less than the number of display electrode pairs in the other plasma tube array, and one of them. By increasing the duration of the first address voltage applied to the signal electrode of the cell in the first line adjacent to the other plasma 'tube' array in the other plasma 'tube' array, We realized that sustain discharge failures could be greatly reduced.

[0005] An object of the present invention is to prevent display defects that may occur near the joint between two plasma 'tube' arrays.

Another object of the present invention is to prevent display discharge failures that can occur near the joint of two plasma 'tube' arrays.

Means for solving the problem

[0006] According to a feature of the present invention, a display device includes a plurality of m gas discharge tubes each having a phosphor layer formed therein, a discharge gas sealed therein, and a plurality of light emitting points in the longitudinal direction. The first plurality of ne pair display electrodes are arranged on the display surface side of the plurality of m gas discharge tubes, and the plurality of m signal electrodes are arranged on the back side of the plurality of m gas discharge tubes. A plurality of m gas discharge tubes each having a plurality of light emitting points in the longitudinal direction are arranged side by side, and a phosphor layer is formed and a discharge gas is enclosed therein. A second multi-nc pair of display electrodes is arranged on the display surface side of one gas discharge tube, and a plurality of m signal electrodes are arranged on the back side of the plurality of m gas discharge tubes. Each display electrode of the first plurality of ne pair of display electrodes of the first unit in the first period; A first display electrode driving circuit that sequentially applies a scanning voltage to one of the display electrodes and applies a sustain voltage pulse to the first plurality of ne display electrodes in the second period; A first address voltage circuit for applying an address voltage pulse to the plurality of m signal electrodes in accordance with the scan voltage sequentially applied to the one display electrode of the first unit in a period of one; the first unit; A scanning voltage is sequentially applied to one display electrode of each display electrode pair of the second plurality of nc pairs of the second unit in the second unit, and the second plurality of display electrodes in the second period. Maintenance power to nc pair display electrodes A second display electrode driving circuit for applying a pressure pulse; and an address voltage for the m signal electrodes according to the scanning voltage sequentially applied to the one display electrode of the second unit during the first period. And a second address voltage circuit for applying a pulse. The number of the second multiple nc is less than the number of the first multiple ne. The longitudinal ends of the plurality of m gas discharge tubes of the first unit and the longitudinal ends of the plurality of m gas discharge tubes of the second unit are adjacent to each other along the joint. Are arranged. The second address voltage circuit is configured such that, during the first period, when a first scanning voltage is applied to a certain display electrode of the display electrode pairs of the second plurality of nc pairs, The first set of address voltage pulses having a duration longer than the duration of the other address voltage pulses is applied to the m signal electrodes of the second unit.

The invention's effect

[0007] According to the present invention, it is possible to prevent a discharge failure that may occur near the joint between the two plasma tube arrays, and thereby, near the joint between the two plasma 'tube' arrays. Display defects can be prevented.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention will be described with reference to the drawings. In the drawings, similar components are denoted by the same reference numerals.

[0009] FIG. 1 illustrates a schematic partial structure of a normal plasma 'tube' array unit (hereinafter referred to as a PTA unit) 10 plasma 'tube or gas discharge tubes 11R, 11G and 1 IB arrays is doing. In FIG. 1, the PTA unit 10 is composed of an array of transparent elongated color 'plasma' tubes 11R, 11G and 11B arranged in parallel with each other, a transparent front support sheet or a front support substrate 31 with a thin substrate force, It includes a transparent or non-transparent back support sheet or thin substrate force back support substrate 32, a plurality of display electrode pairs or main electrode pairs 2, and a plurality of signal electrodes or address electrodes 3. In FIG. 1, X indicates a sustain electrode or X electrode of the display electrode 2, and Y indicates a scan electrode or Y electrode of the display electrode 2. R, G, and B indicate red, green, and blue emission colors of the phosphor. The support substrates 31 and 32 are made of, for example, a flexible PET film or glass. Elongated plasma 'tubes 11R, 11G and 11B tubules 20 are made of a transparent insulator, such as borosilicate glass, Pyrex®, soda glass, quartz glass or zerodur, typically The tube diameter is 2 mm or less. For example, the tube has a cross-sectional width of about 1 mm and a height of about 0.55 mm, a length of 300 mm or more, and a tube wall thickness of about 0.1 mm.

Plasma 'tubes 11R, 11G, and 1 IB have support members formed with phosphor layers 4 of red, green, and blue (R, G, B) inserted and arranged on the back side of the inside, respectively. Gas is introduced and both ends are sealed. On the inner surfaces of the plasma tubes 11R, 11G, and 11B, an electron emission film 5 having MgO force is formed. The phosphor layers R, G, B typically have a thickness in the range of about 10 m to about 30 μm.

The support member is made of an insulating material such as borosilicate glass, Neurex (registered trademark), quartz glass, soda glass, lead glass, and the like on the plasma 'tubes 11R, 11G, and 11B. The phosphor layer 4 is formed on the substrate. The support member is an outer portion of the glass tube. After the phosphor paste is applied on the support member and baked to form the phosphor layer 4 on the support member, the support member is inserted into the glass tube. Can be arranged. Various phosphor pastes known in the art can be used as the phosphor paste. The electron emission film 5 generates charged particles by collision with the discharge gas. When a voltage is applied to the display electrode pair 2, the discharge gas sealed in the tube is excited, and vacuum ultraviolet light is generated by the excitation of the excited discharge gas, and the phosphor layer 4 emits visible light by the ultraviolet light. The generated FIG. 2A shows a front support substrate 31 on which a plurality of transparent display electrode pairs 2 are formed. FIG. 2B shows a back side support substrate 32 on which a plurality of signal electrodes 3 are formed. The signal electrode 3 is formed on the front surface, that is, the inner surface of the back-side support substrate 32, and is provided along the longitudinal direction of the plasma tubes 11R, 11G, and 1IB. The pitch between the adjacent signal electrodes 3 is the same as the width of each of the plasma tubes 11R, 11G, and 1IB, for example, lmm. The plurality of display electrode pairs 2 are formed on the back surface, that is, the inner surface of the front-side support substrate 31 in a well-known form, and are arranged in a direction perpendicular to the signal electrode 3. The width of the display electrode 2 is, for example, 0.75 mm, and between the edges of each pair of display electrodes 2 The distance is for example 0.4 mm. Between the display electrode pair 2 and the adjacent display electrode pair 2, a distance or non-discharge gap as a non-discharge region is secured, and the distance is, for example, 1.1 mm.The signal electrode 3 and the display electrode pair 2 have a PTA When the unit 10 is assembled, it is brought into close contact with the lower outer peripheral surface portion and the upper outer peripheral surface portion of the plasma tubes 11R, 11G and 1IB. In order to improve the adhesion, an adhesive may be interposed between each electrode and the plasma tube surface to bond them.

When the PTA unit 10 is viewed from the front, the intersection of the signal electrode 3 and the display electrode pair 2 becomes a unit light emitting region. For display, one of the display electrode pairs 2 is used as a scanning electrode, a selective discharge is generated at the intersection of the scanning electrode and the signal electrode 3, and a light emitting region is selected. Using the wall charges formed on the inner surface of the tube, a display discharge is generated at the display electrode pair 2 and the phosphor layer is caused to emit light. The selective discharge is a counter discharge generated in the plasma tubes 11R, 11G, and 1IB between the scanning Y electrode and the signal electrode 3 opposed in the vertical direction. The display discharge is a surface discharge generated in the plasma tubes 11R, 11G, and 11B between a pair of display electrodes arranged in parallel on a plane.

The display electrode pair 2 and the signal electrode 3 can generate a discharge in the discharge gas inside the tube by applying a voltage. In Fig. 1, the electrode structure of plasma 'tubes 11R, 11G and 11B is a structure in which three electrodes are arranged in one light emitting part, and the display discharge is generated by a pair of display electrodes. A structure in which display discharge is generated between the display electrode 2 and the signal electrode 3 is not limited thereto. That is, the display electrode pair 2 may be one, and the display electrode 2 may be used as a scanning electrode to generate a selective discharge and a display discharge (opposite discharge) between the display electrode 2 and the signal electrode 3.ヽ.

FIG. 3 shows a cross-sectional structure perpendicular to the longitudinal direction of the tubes of the plasma “tube” array 11 of the PTA unit 10. In the PTA unit 10, the plasma tubes 11R, 11G, and 1IB have phosphor layers 4R, 4G, and 4B formed on the inner surfaces of the back support members 6R, 6G, and 6B, and have a cross-sectional width of 1. It consists of thin tubes with Omm, cross-sectional height of 0.55 mm, tube wall thickness of 0.1 mm, and length of lm to 3 m. As an example, the red phosphor 4R Green phosphor 4G containing Zutria ((Y. Ga) BO: Eu) material is zinc silicate (Z

Three

n Phosphorus 4M is a BAM-based (BaMgAl 2 O 3: Eu) material.

2 4 10 17

including.

In FIG. 3, signal electrodes 3R, 3G, and 3B are arranged on the bottom surfaces of the plasma tubes 11R, 11G, and 11B, and a back-side support substrate 32 is bonded via an adhesive layer. The signal electrode pair 2 is disposed on the upper surfaces of the plasma tubes 11R, 11G, and 11B, and the front-side support substrate 31 is adhered via the adhesive layer!

[0012] FIG. 4 shows a conventional plasma tube array type display device 100 comprising a PTA unit 10, an address (A) electrode driver device 400, an X electrode driver device 500 and a Y electrode driver device 600. ing. In the PTA unit 10, the X electrodes in the n pairs of display electrodes 2 (XI, Yl), ..., (Xj, Yj), ... (Xn, Yn) are the X electrodes of the X electrode driver device 500. Is connected to a sustain voltage pulse circuit (SST) 50 for use, and the soot electrode therein is connected to a scan pulse circuit (SCN) 70 of the soot electrode driver device 600. The m signal electrodes 3 Al,..., Ai,... Am are connected to the A electrode driver device 400. The X electrode driver device 500 further includes a reset circuit 51. The Y electrode driver device 600 further includes a sustain voltage pulse circuit 60 and a reset circuit 61. A driver control circuit (CTRL) 42 is connected to the A electrode driver device 400, the X electrode driver device 500, and the Y electrode driver device 600.

Next, an example of a driving method of a general plasma tube array type AC gas discharge display device will be described. One picture (video) is typically composed of one frame period. In interlaced scanning, one frame is composed of two fields, and in progressive scanning, one frame is composed of one field. . In addition, 30 frames per second are required for video display using the normal television system. Therefore, in this type of display device 100, in order to perform color reproduction with gradation by binary light emission control, typically such one field F is replaced with a set of q subfields SF. . Often, the number of display discharges in each subfield SF is set by giving different weights such as 2 °, 2 ¹ , 2 ² , ^... For each color of R, G, and B with a combination of light emission and non-light emission in subfield units N (= l + 2 ¹ + 2 ² + ^... + 2 ^q_1 ) brightness settings can be made. According to such a field configuration, the field period Tf which is a field transfer period is divided into q subfield periods Tsf, and one subfield period Tsf is assigned to each subfield SF. Further, the subfield period Tsf is divided into a reset period TR for initialization, an address period TA for addressing, and a display period TS for light emission by sustain discharge. Typically, the length of the reset period TR and the address period TA is constant regardless of the weight, whereas the number of pulses in the display period TS is larger and the length of the display period TS is The greater the weight, the longer. In this case, the length of the subfield period Tsf is longer as the weight of the corresponding subfield SF is larger.

FIG. 5 illustrates a schematic drive sequence of output drive voltage waveforms of the A electrode driver device 400, the X electrode driver device 500, and the Y electrode driver device 600 in the normal display device 100. The illustrated waveform is an example, and the amplitude, polarity, and timing can be changed in various ways.

The order of the reset period TR, the address period TA, and the sustain period TS is the same in the q subfields SF, and the drive sequence is repeated for each subfield SF. In the reset period TR of each subfield SF, a negative polarity pulse Prxl and a positive polarity pulse Prx2 are sequentially applied to all the display electrodes X, and a positive polarity pulse Pry is applied to all the display electrodes Y. 1 and negative polarity pulse Pry2 are applied in order. Pulses Prxl, P ryl and Pry2 are ramp waveforms or blunt pulses whose amplitude gradually increases with the rate of change at which a microdischarge occurs. The first applied pulses Prxl and Pryl are applied once to generate moderate wall charges of the same polarity in all discharge cells regardless of light emission Z non-light emission in the previous subfield SF. Subsequently, by applying pulses Prx2 and Pry2 to the discharge cells where moderate wall charges are present, the wall charges are adjusted so as to be reduced to a level where they are not redischarged by the sustain pulses (erased state). The drive voltage applied to the cell is a composite voltage representing the difference in the amplitude of the pulses applied to the display electrodes X and Y.

In the address period TA, the wall charge necessary for maintaining the discharge is formed only in the discharge cells that emit light. All the display electrodes Xl to Xn and all the display electrodes Yl to Yn are biased to a predetermined potential and correspond to the selected row for each row selection period (one row scan time). Apply negative scan 'pulse Vyj to display electrode Yj. Simultaneously with this row selection, the address pulse Va is applied only to the address electrode Ai corresponding to the selected cell that is to generate the address discharge. That is, the potentials of the address electrodes A to A are binary-controlled for each scanning line based on the subfield data Dsf for m columns of the selected row j. This allows the selected cell to

1 m

An address discharge is generated in the discharge tube between the display electrode Yj and the address electrode Ai. The display data written by the address discharge is stored in the form of wall charges on the cell inner wall of the discharge tube, and the surface discharge between the display electrodes X and Y is generated by the subsequent application of the sustain pulse. In the sustain period TS, a sustain pulse Ps having a polarity (positive polarity in the example shown in the figure) that is first added to the wall charge generated in the previous address discharge to generate a sustain discharge is applied. Thereafter, the sustain pulse Ps is alternately applied to the display electrode X and the display electrode Y. The amplitude of the sustain pulse Ps is the sustain voltage Vs. By applying the sustain pulse Ps, a surface discharge is generated in the discharge cell in which a predetermined wall charge remains. The number of times that the sustain pulse Ps is applied corresponds to the weight of the subfield SF as described above. In order to prevent unnecessary counter discharge throughout the sustain period TS, the address electrode A is biased to a voltage Vas having the same polarity as the sustain pulse Ps.

[0015] FIGS. 6A and 6B show the address voltage Va and the scan voltage Vy applied to the address electrode A and the scan electrode Y of the cells in one line, and FIG. 6C shows the address discharge generated in response thereto. It shows the change in light emission due to FIG. 6D shows the arrangement of A electrode, X electrode and Y electrode in each cell.

Referring to FIGS. 6A to 6D, in the address period TA, after applying the address voltage pulse Va, the light emission rises with a certain time delay, and further, the light emission falls with a certain time delay. Address voltage pulse strength! ] Is the discharge delay Td. Therefore, the pulse width Twa of the address voltage must be sufficiently longer than the delay Td. If the pulse width Twa is not sufficient, an address discharge failure or error will occur, the required sustain discharge will not occur in the subsequent sustain period TS, and the display image will flicker and become unsightly.

[0016] Figure 7A shows a plasma tube array with one line spacing for one or more lines of 1 line, 2 lines, 4 lines and 8 lines for different scan voltages Vy. The address discharge delay Td when address discharge is generated between the corresponding Y electrode Yj and A electrodes Al to Am is shown. FIG. 7B shows the address discharge delay Td when address discharge is generated between the Y electrode Yj and the A electrodes Al to Am for different address voltages Va.

As can be seen from FIG. 7A, for a certain scanning voltage Vy, when adjacent lines continuously generate an address discharge, the address discharge delay Td is the shortest address discharge line interval between 2 lines, 4 lines, As the value increases, the address discharge delay Td increases. The priming effect of the address discharge about 4 lines before remains somewhat strong, but the effect disappears in the line farther away.

Some display cells are closer, due to the presence of priming particles or space charges due to the address discharge of the adjacent display cell before the position, thereby reducing the display cell address discharge delay Td and the required scanning. The voltage Vy becomes lower, and therefore address discharge is more likely. Accordingly, in the plasma tube, the address discharge is most likely to fail in the cell at the end of the tube at the head position of the scan when there is no previous address discharge in the adjacent adjacent display cell.

7A and 7B that the address voltage Va and the scanning voltage Vy increase and the address discharge delay Td decreases.

FIG. 8 shows a typical display device 102 having two plasma 'tube' arrays. Display device 102 includes PTA unit 10 connected to A electrode driver device 400, X electrode driver device 500, and Y electrode driver device 600, A electrode driver device 408, X electrode driver device 508, and Y electrode driver device 608. Has a PTA unit 18 connected. The PTA units 10 and 18 are arranged so that the lower end of the tube of the PTA unit 10 and the upper end of the tube of the PTA unit 10 are in contact with each other at the joint 183.

The A electrode driver device 400 sequentially applies the address voltage Va in the direction from the upper end 181 of the PTA unit 10 to the joint 183 in accordance with the scanning voltage Vy sequentially applied by the Y electrode driver device 600. At the same time, the A electrode driver device 408 sequentially applies the address voltage Vad in the direction from the joint 183 to the lower end 188 of the PTA unit 18 according to the scanning voltage Vy sequentially applied by the Y electrode driver device 608. According to it, the address The period can be cut in half.

The cells on the top line of the upper end 181 of the PTA unit 10 tend to fail in address discharge, so they are covered with a cover and hidden. It is only necessary to prevent the address discharge failure of the cells in the subsequent lines, thereby preventing the display from becoming unsightly. However, the cell of the top line near the joint 183 of the PTA unit 18 is located in the center of the display screen and cannot be obscured. In the vicinity of the joint 183 of the PTA units 10 and 18, the internal space of both plasma tubes is separated, and the effect of priming particles is interrupted.

In order to solve this, the cell in the lowermost line of the lower end 188 of the PTA unit 18 is covered with a force bar and hidden, and the PTA unit 18 is sequentially applied in the reverse direction by the Y electrode driver device 608 according to the scanning voltage Vy. The address voltage Va may be sequentially applied in the direction from the lower end 188 of 18 to the joint 183. However, in a display device with three PTA units arranged vertically, the central PTA unit cannot cover any end of the tube.

During the address scan of the plasma tube array, the leading line at the end of the tube has less priming charge from the previous line, so the probability of successful address discharge is low, for example about 50%.

The address discharge of a cell in a lie gives a sufficient priming effect to the address discharge of a cell in an adjacent line.

Since the reset voltage of the ramp waveform in the reset period TR generates only a slight discharge so as to suppress background light emission, the priming effect on the address discharge in the address period TA is small.

In order to reduce the normal address discharge delay and prevent address discharge failure, the address voltage is increased, the address voltage pulse width is increased, the address electrode area is increased, and the gap between the address electrode and the scan electrode is decreased. Can be considered. However, it entails an increase in the power supply voltage, an increase in the withstand voltage of the circuit and an increase in power consumption, an increase in the address period, a decrease in light emission efficiency, and an increase in cost.

For example, at a certain driving voltage, the priming charge is generated without address discharge of the previous line. In this case, the address discharge delay time Td is 1.5 s and 1.0 s, respectively, when there is priming charge due to the address discharge of the previous line, and there is a difference of about 1.5 times. . Therefore, address discharge failure can be prevented by increasing the address voltage pulse width when there is no priming charge by a factor of 1.5, for example.

FIG. 9 shows a schematic configuration of a display device 104 having three PTA units 10, 12, and 18 arranged vertically adjacent to each other according to an embodiment of the present invention.

The PTA unit 10 includes m plasma 'tubes 111, m signal electrodes Al to Am arranged on the rear support substrate 320, and ne pair display electrodes (XI, Yl), (Χ2, Υ2),... (Xne, Yne), where ne is a positive integer. The A driver device 400 applies address voltage pulses to the signal electrodes Al to Am of the PTA unit 10. The Y driver device 600 applies scanning voltage pulses to the display electrodes Yl, Υ2,... Yne of the PTA unit 10 in ascending order. Although not shown in FIG. 9, the X driver device 500 of FIG. 8 similar to FIG. 4 is used for the PTA unit 10.

The PTA unit 12 includes m plasma 'tubes 112, m signal electrodes Al to Am arranged on the rear support substrate 322, and nc pairs of display electrodes (XI, Yl), (Χ2, Υ2),... (Xnc, Ync), where nc is a positive integer less than ne. The difference between ne and nc (ne−nc) is preferably 1 to 4. The A driver device 402 applies address voltage pulses to the signal electrodes Al to Am of the PTA unit 12. The Y driver device 602 displays the scanning voltage pulses in ascending order on the display electrodes Yl, Y2,... Ync of the PTA unit 12 as shown in FIG. The same X driver device as in Fig. 4 (502 in Fig. 10) is used. The plasma 'tube 112 may be shorter than the plasma tube 111 to accommodate the difference ne-nc pair electrode.

The PTA unit 18 includes m signal electrodes Al to Am arranged on the rear support substrate 328, and ne pairs of display electrodes (XI, Yl), (Χ2, Υ2) arranged on the front support substrate 318, (Xne, Yne). The A driver device 408 applies address voltage pulses to the signal electrodes Al to Am of the PTA unit 18. The Y driver device 608 applies scanning voltage pulses to the display electrodes Yl, Υ2,... Yne of the PTA unit 18 in descending order. Although not shown in FIG. 9, the PTA unit 18 uses the X driver device 508 shown in FIG. The signal electrodes Al to Am of each set of the PTA units 10, 12 and 18 are electrically separated from each other. In the address period, the A driver device 400 and the Y driver device 600, the A driver device 402 and the Y driver device 602, and the A driver device 408 and the Y driver device 608 operate simultaneously in parallel.

FIG. 10 shows a configuration of the A driver device 402, the X driver device 402, and the Y driver device 502 used for the PTA unit 12 of the display device 104 of FIG.

In FIG. 10, a signal processing circuit 51 receives field data Df indicating the emission intensities of the three primary colors R, G, and B together with a synchronization signal from an external device such as a TV tuner or a computer. The signal processing circuit 51 converts the field data Df into subfield data Dsf for gradation display, and supplies the subfield data Dsf to the driver control circuit 52. The subfield data Dsf is a set of 1-bit display data per cell, and the value of each bit indicates whether or not each cell needs to emit light in the corresponding subfield SF.

The driver control circuit 52 supplies the subfield data Dsf and the control signal CTRL—A to the A driver device 402. The driver control circuit 52 further supplies the scan data and the shift clock pulse cp to the scan circuit 70 of the Y driver device 602, and the control signal

SHIFT

No. CTRL — Y is supplied to the control circuit of Y driver device 602. The driver control circuit 52 further supplies a control signal CTRL_X to the X driver device 502.

[0021] FIGS. 11A to 11D show the shift clock pulse cp from the driver control circuit 52 used in the PTA unit 12 of FIG. 9 in the address period TA and the head of the scan data.

SHIFT

The time chart of the part, the address voltage pulses Val to Vanc from the A driver device 402, and the scanning voltage pulses Vyl to Vync from the Y driver device 502 is shown. Each of the address voltage pulses Val to Vanc represents a set of m voltage pulses of high level (1) and low level (0) applied to the address electrodes Al to Am according to sequential scanning. Fig. 11A ~: First address voltage pulse applied to address electrodes Al ~ Am at L 1D! The width W1 of the pulse Val is the remaining address voltage pulse Va2 ~ applied to the address electrodes Al ~ Am. The width of the remaining address voltage pulses Va2 to Vanc, which is larger than the normal width Wnc of Vanc, preferably has a predetermined width of 1.5 to 2 times Wnc. Therefore, mark the scan electrode Y1. The width Wl of the first scan voltage pulse Vyl applied is larger than the normal width Wnc of the remaining scan voltage pulses Vy2 to Vync applied to the scan electrodes Y2 to Ync (Wl> Wnc), and the remaining scan voltage pulse Vy2 ~ Vync width Wnc preferably has a predetermined width in the range of 1.5 to 2 times. The first address voltage pulse of width W1 can successfully generate an address discharge between the signal electrodes Al to Am of the PTA unit 12 and the first scan electrode Y1.

The A driver device 402 generates the address voltage pulses Val to Vane according to the shift clock pulse cp adjusted to have the widths W1 and Wnc as described above.

SHIFT

The When the Y driver device 502 receives the head scan data, it applies the voltage Vya2 to the scan electrodes Yl to Ync, and the scan voltage pulse at the level Vyal according to the shift clock pulse cp.

SHIFT

Rus Vyl ~ Vync is sequentially applied to the scan electrodes Yl ~ Ync.

FIGS. 12A to 12D show the shift clock pulse cp from the driver control circuit 52 used in the PTA unit 12 of FIG. 9 in the address period TA and the head of the scan data.

SHIFT

7 shows an alternative time chart of the address voltage pulses Val to Vanc from the A driver device 402 and the scanning voltage pulses Vyl to Vync from the Y driver device 502.

Figure 11A ~: The first address voltage pulse applied to the address electrodes Al ~ Am at L1D! The width W1 of the pulse Val is the width W2 of the address voltage pulse Va2 applied to the address electrodes Al ~ Am. The width of the remaining address voltage pulses Va3 to Vanc, which is larger than the normal width Wnc of the remaining address voltage pulses Va3 to Vanc, preferably has a predetermined width of 1.5 to 2 times the width Wnc. The width W2 of the second address voltage pulse Va2 applied to the address electrodes Al to Am is smaller than the width W1 of the address voltage pulse Val applied to the address electrodes Al to Am, and the remaining address voltage pulses Va3 to Vanc. It is larger than the normal width Wnc (W1>W2> Wnc), and has a predetermined width of preferably 1.25 to 1.5 times the width Wnc of the remaining address voltage pulses Va3 to Vanc. Therefore, the width W1 of the first scan voltage pulse Vyl applied to the scan electrode Y1 is larger than the width W2 of the second scan voltage pulse Vy2 applied to the scan electrode Y2, and the remaining scan voltage pulses Vy3 to Vync Preferably, the width W2 of the second scan voltage pulse Vy2 has a predetermined width in the range of 1.5 to 2 times the width Wnc. 查 The width of the remaining scanning voltage pulses Vy3 to Vync, which is larger than the normal width Wnc of the remaining scanning voltage pulses Vy3 to Vync applied to the electrodes Y3 to Ync, preferably in the range of 1.25 times to 1.5 times the width Wnc Having a predetermined width. The first two address voltage pulses Val and Va2 of width W1 and W2 can successfully generate an address discharge between the signal electrodes Al to Am of the PTA unit 12 and the first scanning electrodes Y1 and Y2.

The A driver device 402 applies the address voltage pulses Val to Vanc according to the shift clock pulse cp adjusted to have the intervals of the widths Wl, W2, and Wnc as described above.

SHIFT

appear. When the Y driver device 502 receives the head scan data, it applies the voltage Vya2 to the scan electrodes Yl to Ync, and scans the Revenor Vval according to the shift clock pulse cp.

SHIFT

Voltage pulses Vyl to Vync are sequentially applied to the scan electrodes Yl to Ync.

FIG. 13 shows a schematic configuration of a display device 106 having four PTA units 10, 12, 14 and 18 arranged vertically adjacent to each other according to another embodiment of the present invention. The PTA units 10, 12 and 18 have the same configuration as that of FIG.

Similar to the PTA unit 12, the PTA unit 14 is arranged on the m plasma tubes 114, the m signal electrodes Al to Am arranged on the back side support substrate 324, and the front side support substrate 314. nc pairs of display electrodes (XI, Yl), (Χ2, Υ2), ... (Xnc, Ync). The A driver device 404 applies an address voltage pulse to the signal electrodes Al to Am of the PTA unit 14. The Y driver device 604 applies scanning voltage pulses to the display electrodes Yl, Υ2,... Ync of the PTA unit 12 in ascending order. The PTA unit 14 uses the X driver device 504 shown in FIG.

The signal electrodes Al to Am of each set of the PTA units 10, 12, 14 and 18 are electrically separated from each other. In the address period, A driver device 400 and Y driver device 600, A driver device 402 and Y driver device 602, A driver device 404 and Y driver device 604, A driver device 408 and Y driver device 608 Operate simultaneously in parallel.

As shown in FIG. 10, the A driver device 402, the X driver device 502, and the Y driver device 602 are used for the PTA unit 12, and similarly, the A driver device 404, X A driver device 504 and a Y driver device 604 are used. The time charts of FIGS. 11A-1 ID and FIGS. 12A-12D apply to the A driver device 404 and Y driver device 504 of FIG. 13 as well as the A driver device 402 and the driver device 502. Accordingly, similarly to the PTA unit 12, the address discharge can be successfully generated between the signal electrode Al to Am of the PTA unit 14 and the first scan electrode Y1 or the signal electrode Al to Am and Y1 and Y2. .

[0024] FIG. 14 is a variation of the embodiment of FIG. 9, and includes three PTA units 10 ′, 12 ′ and 18 ′ arranged vertically adjacent, according to yet another embodiment of the invention. 1 shows a schematic configuration of a display device 108 having the display device 108. In this case, PTA units 10 'and 12' share the longer m plasma tubes 111 ', and PTA units 12' and 18 'share the longer V, m plasma' tubes 118 '. And

The PTA unit 10 'includes a large upper portion of m plasma' tubes 111 ', address electrodes Al to Am arranged on the back side support substrate 320, and ne arranged on the front side support substrate 310. A pair of display electrodes (XI, Yl), (Χ2, Υ2),... (Xne, Yne). The PTA unit 18 'includes a large lower part of m plasma' tubes 118 ', address electrodes Al to Am arranged on the back side support substrate 328, and ne arranged on the front side support substrate 318. A pair of display electrodes (XI, Yl), (Χ2, Υ2),... (Xne, Yne). The PTA unit 12 includes the remaining lower part of the m plasma 'tubes 111, the remaining upper part of the m plasma' tubes 118 ', and the address electrodes Al ~ disposed on the rear support substrate 322. Am, and nc pairs of display electrodes (XI, Yl), (Χ2, Υ2),... (Xnc, Ync) disposed on the front support substrate 312. The display electrodes (Xj, Yj) in the jth row pair correspond to the cells in the uppermost row of m plasma 'tubes 118'.

[0025] FIGS. 15A to 15D show the shift clock pulse cp from the driver control circuit 52 used in the PTA unit 12 of FIG. 14 in the address period TA and the head in the scan data.

SHIFT

The time chart of the address voltage pulses Val to Vanc from the A driver device 402 and the scanning voltage pulses Vyl to Vync from the Y driver device 502 is shown in FIG. 15A to 15D! /, The first and jth address voltage pulses applied to the address electrodes Al to Am. The width W1 of Val and Vaj is the remaining address voltage pulse applied to the address electrodes Al to Am. Va2 to Vaj— 1 and Vaj + l to Vanc normal width Wnc The remaining large address voltage pulses Va2 to Vaj—1 and Vaj + 1 to Vanc have a predetermined width of preferably 1.5 to 2 times the width Wnc. Therefore, the width W1 of the first and jth scan voltage pulses Vyl and Vyj applied to the scan electrodes Y1 and Yj is the remaining scan voltage applied to the scan electrodes Y2 to Yj-1 and Yj + l to Ync. Pulses Vy2 to Vyj— 1 and Vyj + l to Vync normal width Wnc greater than Wnc (Wl> Wnc), remaining scan voltage pulses Vy2 to Vyj-1 and Vyj + l to Vync width Wnc preferably 1 It has a predetermined width in the range of 5 to 2 times. Address voltage pulses Val and Vaj of width W1 can generate an address discharge between the signal electrodes Al to Am of the PTA unit 12 and the first and jth scan electrodes Y1.

SHIFT

Rus Vyl ~ Vync is sequentially applied to the scan electrodes Yl ~ Ync. Therefore, the address discharge between the signal electrodes Al ~ Am and the first scan electrodes Y1 and Yj or the signal electrodes A1 ~ Am and Y1 and Yj and Y2 and Yj + 1 of the PTA mute 12 'is successfully performed. Can be generated.

The other operations of the A driver devices ■, 402 and 408, the X driver devices 500, 502 and 508, and the Y driver devices 600, 602 and 608 are the same as those of the embodiment of FIG.

FIGS. 16A to 16D are used for the PTA unit 12 of FIG. 14 in the address period TA, and are shifted from the driver control circuit 52, the clock pulse cp and the head in the scan data.

SHIFT

5 shows another time chart of address voltage pulses Val to Vanc from the A driver device 402 and scanning voltage pulses Vyl to Vync from the Y driver device 502. In FIGS. 16A to 16D, the width W1 of the first and jth address voltage pulses Val applied to the address electrodes Al to Am is the width W2 of the address voltage pulses Va2 and Vaj + 1 applied to the address electrodes Al to Am. And the remaining address voltage pulses Va3 to Vaj— 1 and Vaj + 2 to Vanc normal width Wnc The remaining address voltage pulses Va3 to greater than Wnc The width of Vaj 1 and Vaj + 2 to Vanc preferably has a predetermined width of 1.5 to 2 times Wnc. The width W2 of the second and first address voltage pulses Va2 and Vaj + 1 applied to the address electrodes Al to Am is smaller than the width W1 of the address voltage pulse Val applied to the address electrodes Al to Am. The remaining address voltage pulses Va3 to Vaj—L and Vaj + 2 to Vanc normal width Wnc (Wl>W2> Wnc), remaining address voltage pulses Va3 to Vaj-1 and Vaj + 2 ˜Vanc width Wnc preferably has a predetermined width of 1.25 to 1.5 times. Accordingly, the width W1 of the first and jth scan voltage pulses Vyl and Vyj applied to the scan electrodes Y1 and Yj is equal to the second and j + 1st scan voltage pulses Vy2 and Vyj + applied to the scan electrode Y2. The remaining scan voltage pulse larger than the width W2 of 1 Vy3 to Vaj— 1 and Vaj + 2 to Vync width Wnc preferably has a predetermined width in the range of 1.5 times to 2 times, and the second And j + 1st scan voltage pulse Vy2 and Vyj + 1 width W2 is determined by the remaining scan voltage pulses Vy3 to Vaj-1 and Vaj applied to scan electrodes Y3 to Yj—1 and Yj + l to Ync. + 2 to Vync normal width Wnc greater than the remaining scan voltage pulse Vy3 to Vaj— 1 and Vaj + 2 to Vync width Wnc preferably with a predetermined width in the range of 1.25 to 1.5 times Have. Address discharge pulses of width W1 and W2 Val and Va2 and Vaj and Vaj + 1 enable address discharge between PTA unit 12 signal electrodes Al to Am and scan electrodes Yl, Y2, Yj and Yj + 1. Can be generated.

SHIFT

appear. When the Y driver device 502 receives the first scan data, it applies the voltage Vya2 to the scan electrodes Yl to Ync and scans the Revenor Vyal according to the shift clock pulse cp.

SHIFT

In FIGS. 15C and 15D and FIGS. 16C and 16D, as an alternative configuration, the application sequence of the address voltage pulses Val to Vaj-1 and Vaj to Vanc is Vaj to Vane and Val. ~ Vaj—1 and scan voltage pulses Vyl ~ Vyj—1 and Vyj ~ Vync applied from Vyj ~ Vync and Vyl ~ Vyj-1 starting from the top of plasma 'tube 118. Anyway!

[0027] FIG. 17 is a variation of the embodiment of FIG. 13 and includes four PTA units 10 ′, 12 ′, 14 ′ and 18 arranged vertically adjacent, according to yet another embodiment of the invention. 1 shows a schematic configuration of a display device 110 having '. In this case, PTA units 10 'and 12' share a longer m plasma 'tube 111, and PTA units 12 and 14 share a longer m plasma' tube 113. The PTA units 14 'and 18' are longer! They share m plasma tubes 118 '.

PTA units 10 and 18 are the same as in FIG.

The PTA unit 12 includes m plasma 'tubes 111, the lower part, m plasmas' tube 113 upper part, address electrodes A1 to Am arranged on the rear support substrate 322, and the front surface. Nc pairs of display electrodes (XI, Yl), (Χ2, Υ2),... (Xnc, Ync) arranged on the side support substrate 312. The display electrodes (Xj, Yj) in the j-th row pair correspond to the cells in the uppermost row of m plasma 'tubes 113.

PTA unit 14 includes m plasma 'tube 113 lower part, m plasma' tube 118 'upper part, address electrodes Al to Am arranged on back support substrate 322, front side Nc pairs of display electrodes (XI, Yl), (Χ2, Υ2),... (Xnc, Ync) disposed on the support substrate 312. The display electrodes (Xj, Yj) in the jth row pair correspond to the cells in the uppermost row of m plasma tubes 118 '.

The time charts of FIGS. 15A to 15D and FIGS. 16A to 16D apply to the A driver device 404 and the Y driver device 504 as well as the A driver device 402 and the driver device 502. Therefore, the address discharge between the signal electrodes Al to Am of the PTA unit 14 'and the first scan electrodes Y1 and Yj or the signal electrodes Al to Am and Y1 and Yj and Y2 and Yj + 1 can be successfully generated. Can do.

[0028] In the embodiment of FIGS. 14 and 17, the number of plasma 'tube' arrays is less than the number of PTA units, but the number of plasma 'tube' arrays may be greater than the number of SPTA units. [0029] In the above-described embodiment, the force obtained by increasing the pulse widths Wl and W2 of the first and Z or second address voltage pulses from the scan start and the tube end, and the number from the start from the scan start and the tube end. The pulse width of the kth address voltage pulse may be increased.

[0030] The embodiment described above is merely given as a typical example, and it is obvious to those skilled in the art to combine the constituent elements of each embodiment, and variations and variations thereof. Obviously, various modifications can be made to the embodiments without departing from the scope of the invention as set forth in the principles and claims.

Brief Description of Drawings

[0031] FIG. 1 illustrates a schematic partial structure of an array of plasma 'tubes or gas discharge tubes of a conventional plasma' tube 'array unit (PTA unit).

FIG. 2A shows a front-side support substrate on which a plurality of transparent display electrode pairs are formed. FIG. 2B shows a backside support substrate on which a plurality of signal electrodes or signal electrodes are formed.

[FIG. 3] FIG. 3 shows the structure of a cross section perpendicular to the longitudinal direction of the tubes of the plasma 'tube' array of the PTA unit.

[FIG. 4] FIG. 4 shows a conventional plasma tube array type display device including a PTA unit, an A electrode driver device, an X electrode driver device, and a Y electrode driver device.

FIG. 5 illustrates a schematic drive sequence of output drive voltage waveforms of an A electrode driver device, an X electrode driver device, and a Y electrode driver device in a normal display device.

[FIG. 6] FIGS. 6A and 6B show the address voltage and scan voltage applied to the address electrode A and the scan electrode Y of the cell in one line, and FIG. 6C shows the address discharge generated in response thereto. The change in luminescence is shown. FIG. 6D shows the arrangement of the A, X, and Y electrodes in each cell.

[Fig. 7] Fig. 7A shows an address discharge between the corresponding Y electrode and A electrode in the plasma tube array at intervals of 1 line for each number of lines of 1 or more for different scanning voltages. The address discharge delay in the case of being performed is shown. Figure 7B shows different address voltages In contrast, the address discharge delay when address discharge is generated between the Y electrode and the A electrode is shown.

[Figure 8] Figure 8 shows a typical display device with two plasma tube arrays! /

FIG. 9 shows a schematic configuration of a display device having three PTA units arranged adjacent to each other in the vertical direction according to an embodiment of the present invention.

[FIG. 10] FIG. 10 shows configurations of an A driver device, an X driver device, and a Y driver device used in the PTA unit of the display device of FIG.

[FIG. 11] FIGS. 11A to 11D show the shift clock pulse from the driver control circuit used in the PTA unit of FIG. 9 in the address period and the head part in the scan data, the address voltage pulse from the A driver device. , And show a time chart of the scanning voltage pulse from the Y driver device!

[FIG. 12] FIGS. 12A to 12D show the shift clock pulse from the driver control circuit used in the PTA unit of FIG. 9 during the address period and the head part of the scan data, the address voltage pulse from the A driver device. And an alternative time chart of scan voltage pulses from the Y driver device.

FIG. 13 shows a schematic configuration of a display device having four PTA units arranged adjacent to each other in the vertical direction according to another embodiment of the present invention.

FIG. 14 is a modification of the embodiment of FIG. 9, and shows a schematic configuration of a display device having three PTA units arranged vertically adjacent to each other according to still another embodiment of the present invention. Show.

[FIG. 15] FIGS. 15A to 15D show a shift clock pulse from the driver control circuit used in the PTA unit of FIG. 14 in the address period and the head part in the scan data, an address voltage pulse from the A driver device. , And show a time chart of the scanning voltage pulse from the Y driver device!

[FIG. 16] FIGS. 16A to 16D show the shift clock pulse from the driver control circuit used in the PTA unit of FIG. 14 in the address period and the head part in the scan data, the address voltage pulse from the A driver device. , And scan voltage pulse from Y driver device Show another time chart.

FIG. 17 is a modification of the embodiment of FIG. 13, and shows a schematic configuration of a display device having four PTA units arranged adjacent to each other in the vertical direction according to still another embodiment of the present invention. Show.

Claims

The scope of the claims

Inside, a phosphor layer is formed and a discharge gas is enclosed, and a first set of a plurality of m gas discharge tubes each having a plurality of emission points in the longitudinal direction are juxtaposed, and the plurality of the first set The first plurality of ne pairs of display electrodes are arranged on the display surface side of the m gas discharge tubes, and the plurality of m signal electrodes are arranged on the back side of the first set of the plurality of m gas discharge tubes. The first unit,

Inside, a phosphor layer is formed and a discharge gas is enclosed, and a second set of a plurality of m gas discharge tubes each having a plurality of emission points in the longitudinal direction are juxtaposed, and the plurality of the second set A second plurality of nc pairs of display electrodes are arranged on the display surface side of the m gas discharge tubes, and a plurality of m signal electrodes are arranged on the back side of the second set of the plurality of m gas discharge tubes. A second unit,

During the first period, a scanning voltage is sequentially applied to one display electrode of each display electrode pair of the first plurality of ne display electrodes of the first unit, and in the second period, A first display electrode driving circuit for applying a sustain voltage pulse to the first plurality of ne pair of display electrodes;

A first address voltage circuit for applying an address voltage pulse to the plurality of m signal electrodes in accordance with the scan voltage sequentially applied to the one display electrode of the first unit in the first period;

In the first period, a scan voltage is sequentially applied to one display electrode of each display electrode pair of the second plurality of nc pairs of display electrodes of the second unit, and the second period includes the second display electrode. A second display electrode driving circuit for applying a sustain voltage pulse to the display electrodes of the plurality of two nc pairs;

A second address voltage circuit for applying an address voltage pulse to the plurality of m signal electrodes in accordance with the scan voltage sequentially applied to the one display electrode of the second unit in the first period;

With

The number of the second plurality of ncs is less than the number of the first plurality of ne

Ends of the first set of multiple m gas discharge tubes and the second set of multiple m gas discharge tubes Are arranged adjacent to each other along the joint,

The second address voltage circuit is configured to apply an initial scanning voltage to a certain display electrode of the display electrode pairs of the second plurality of nc pairs in the first period. A display device, wherein a first address voltage pulse having a duration longer than that of other address voltage pulses is applied to the plurality of m signal electrodes of the second unit.

[2] In the second address voltage circuit, the first and second scanning voltages are applied to a display electrode of the display electrode pairs of the second plurality of nc pairs in the first period. When applied, the first and second sets of address voltage pulses having a duration longer than the duration of the other address voltage pulses are applied to the plurality of m signal electrodes of the second unit. The display device according to claim 1, wherein the display device is characterized.

[3] In the first period, the second address voltage circuit applies a scanning voltage to the first display electrode at the tube end of each display electrode pair of the second plurality of nc pairs of display electrodes. When a set of address voltage pulses having a duration longer than that of other address voltage pulses is applied to the plurality of m signal electrodes of the second unit. The display device according to claim 1.

[4] Sarakoko, a third set of a plurality of m gas discharge tubes each having a phosphor layer formed therein and filled with a discharge gas, each having a first plurality of ne luminous points in the longitudinal direction Are arranged side by side, and the first plurality of ne pairs of display electrodes are arranged on the display surface side of the third set of the plurality of m gas discharge tubes, and the rear side of the third set of the plurality of m gas discharge tubes 2. The display device according to claim 1, further comprising a third unit in which a plurality of m signal electrodes are arranged.

[5] Inside, a phosphor layer is formed and a discharge gas is enclosed, and a part of the first set of a plurality of m gas discharge tubes each having a plurality of light emitting points in the longitudinal direction are juxtaposed, A first plurality of ne pairs of display electrodes are arranged on the display surface side of the first set of the plurality of m gas discharge tubes, and a plurality of m pieces of display electrodes are arranged on the back side of the first set of the plurality of m gas discharge tubes. A first unit with signal electrodes,

Inside, a phosphor layer is formed and a discharge gas is sealed, and the remaining part of the first set of the plurality of m gas discharge tubes is juxtaposed, and the first set of the plurality of m gas discharge tubes The rest of A portion of the second set of the plurality of m gas discharge tubes each having a plurality of light emitting points in the longitudinal direction adjacent to the end of a portion of the first set of the plurality of gas discharge tubes is juxtaposed. A second plurality of nc pairs of display electrodes are arranged on the display surface side of the remaining part of the discharge tube and a part of the second set of the plurality of m gas discharge tubes, and the plurality of m sets of the first set. A second unit in which a plurality of m signal electrodes are arranged on the back side of the remaining part of the gas discharge tube and a part of the second set of the plurality of m gas discharge tubes;

With

The remaining part of the first set of the plurality of m gas discharge tubes and the end of the second set of the plurality of m gas discharge tubes are adjacent to each other along a joint. Arranged,

In the first period, the second address voltage circuit includes a part of the second set of the plurality of m gas discharge tubes of the display electrode pairs of the second plurality of nc pairs of display electrodes. When a scanning voltage is applied to the first display electrode at the end, one set of address voltage pulses having a duration longer than the duration of other address voltage pulses is applied to the plurality of _m signal electrodes of the second unit. A display device characterized by being applied to the display.