WO2007125519A2 - solution de resynchronisation optimisée de latence pour un chemin de lecture de sdram ddr/ddr2 - Google Patents

solution de resynchronisation optimisée de latence pour un chemin de lecture de sdram ddr/ddr2 Download PDF

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Publication number
WO2007125519A2
WO2007125519A2 PCT/IB2007/051617 IB2007051617W WO2007125519A2 WO 2007125519 A2 WO2007125519 A2 WO 2007125519A2 IB 2007051617 W IB2007051617 W IB 2007051617W WO 2007125519 A2 WO2007125519 A2 WO 2007125519A2
Authority
WO
WIPO (PCT)
Prior art keywords
domain
data
signal
random access
dynamic random
Prior art date
Application number
PCT/IB2007/051617
Other languages
English (en)
Other versions
WO2007125519A3 (fr
Inventor
Jan Vink
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2007125519A2 publication Critical patent/WO2007125519A2/fr
Publication of WO2007125519A3 publication Critical patent/WO2007125519A3/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)

Abstract

L'invention concerne un appareil pour synchroniser des signaux de données de mémoire. L'appareil comprend un premier circuit d'interface (110) qui est configuré pour générer un signal d'horloge différentiel dans un domaine de sélecteur de signaux et pour transporter un signal de données à un bus de données (110), un second circuit d'interface (120) dans un domaine d'horloge qui est configuré pour recevoir le signal de données (170) provenant du bus de données et un circuit de synchronisation qui est configuré pour régler le signal de données (170) entre le domaine de sélecteur de signaux et le domaine d'horloge de telle sorte que l'intégrité des informations codées par le signal de données est préservée. L'invention concerne également des procédés d'utilisation de l'appareil.
PCT/IB2007/051617 2006-05-03 2007-05-02 solution de resynchronisation optimisée de latence pour un chemin de lecture de sdram ddr/ddr2 WO2007125519A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US79747206P 2006-05-03 2006-05-03
US60/797,472 2006-05-03

Publications (2)

Publication Number Publication Date
WO2007125519A2 true WO2007125519A2 (fr) 2007-11-08
WO2007125519A3 WO2007125519A3 (fr) 2008-01-10

Family

ID=38529487

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2007/051617 WO2007125519A2 (fr) 2006-05-03 2007-05-02 solution de resynchronisation optimisée de latence pour un chemin de lecture de sdram ddr/ddr2

Country Status (1)

Country Link
WO (1) WO2007125519A2 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2500818A (en) * 2012-03-30 2013-10-02 Spansion Llc Reduced pin count (RPC) memory bus interface including a read data strobe signal
US20140330994A1 (en) * 2013-05-06 2014-11-06 Qualcomm Incorporated Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation
US9515817B2 (en) 2014-06-30 2016-12-06 International Business Machines Corporation Latency-optimized physical coding sublayer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5999458A (en) * 1997-12-10 1999-12-07 Fujitsu Limited Latch circuit, data output circuit and semiconductor device having the circuits
WO2001024184A1 (fr) * 1999-09-30 2001-04-05 Silicon Graphics, Inc. Synchroniseur configurable pour ensemble de memoire vive dynamique synchrone a double vitesse de transfert
US6920526B1 (en) * 2000-07-20 2005-07-19 Silicon Graphics, Inc. Dual-bank FIFO for synchronization of read data in DDR SDRAM

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5999458A (en) * 1997-12-10 1999-12-07 Fujitsu Limited Latch circuit, data output circuit and semiconductor device having the circuits
WO2001024184A1 (fr) * 1999-09-30 2001-04-05 Silicon Graphics, Inc. Synchroniseur configurable pour ensemble de memoire vive dynamique synchrone a double vitesse de transfert
US6920526B1 (en) * 2000-07-20 2005-07-19 Silicon Graphics, Inc. Dual-bank FIFO for synchronization of read data in DDR SDRAM

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2500818A (en) * 2012-03-30 2013-10-02 Spansion Llc Reduced pin count (RPC) memory bus interface including a read data strobe signal
US20130262907A1 (en) * 2012-03-30 2013-10-03 Clifford Alan Zitlaw Apparatus and method for a reduced pin count (rpc) memory bus interface including a read data strobe signal
US8966151B2 (en) * 2012-03-30 2015-02-24 Spansion Llc Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal
GB2500818B (en) * 2012-03-30 2015-12-23 Cypress Semiconductor Corp Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal
TWI547807B (zh) * 2012-03-30 2016-09-01 賽普拉斯半導體公司 用於包含讀取資料選通訊號的減少接腳數（ｒｐｃ）記憶體匯流排介面的裝置及方法
US20140330994A1 (en) * 2013-05-06 2014-11-06 Qualcomm Incorporated Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation
US9875209B2 (en) * 2013-05-06 2018-01-23 Qualcomm Incorporated Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation
US9515817B2 (en) 2014-06-30 2016-12-06 International Business Machines Corporation Latency-optimized physical coding sublayer
US9515816B2 (en) 2014-06-30 2016-12-06 International Business Machines Corporation Latency-optimized physical coding sublayer
US10103830B2 (en) 2014-06-30 2018-10-16 International Business Machines Corporation Latency-optimized physical coding sublayer
US10110335B2 (en) 2014-06-30 2018-10-23 International Business Machines Corporation Latency-optimized physical coding sublayer

Also Published As

Publication number Publication date
WO2007125519A3 (fr) 2008-01-10

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