WO2007108400A1 - Appareil et procede de test et dispositif de memoire - Google Patents

Appareil et procede de test et dispositif de memoire Download PDF

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Publication number
WO2007108400A1
WO2007108400A1 PCT/JP2007/055267 JP2007055267W WO2007108400A1 WO 2007108400 A1 WO2007108400 A1 WO 2007108400A1 JP 2007055267 W JP2007055267 W JP 2007055267W WO 2007108400 A1 WO2007108400 A1 WO 2007108400A1
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WIPO (PCT)
Prior art keywords
test
self
memory
semiconductor device
circuit
Prior art date
Application number
PCT/JP2007/055267
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English (en)
Japanese (ja)
Inventor
Yuya Watanabe
Original Assignee
Advantest Corporation
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Publication of WO2007108400A1 publication Critical patent/WO2007108400A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3187—Built-in tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Definitions

  • Test apparatus memory device, and test method
  • the present invention relates to a test apparatus, a memory device, and a test method.
  • the present invention relates to a test apparatus that detects defects using a self-test circuit, a memory device that includes a self-test circuit, and a test method that detects defects using a self-test circuit.
  • This application is related to the following Japanese application. For designated countries where incorporation by reference is allowed, the contents described in the following application are incorporated into this application by reference and made a part of this application.
  • Memory devices such as DRAMs can increase data transfer speed by expanding the bus width and improving the frequency of the operation clock. However, if the frequency of the memory device is increased or the bus width is expanded, high performance is also required for the test apparatus for testing the memory device. For example, if the bus width is expanded, the number of terminals required for the test apparatus increases, or the number of memory devices that can be tested simultaneously decreases.
  • Patent Document 1 Japanese Patent Laid-Open No. 2001-236797
  • the manufacturing process of a memory device may be frequently improved to improve its yield. As the manufacturing process is improved, the types of defects that are likely to occur also change. For this reason, For efficient detection, it is desirable to change the test method as the manufacturing process is improved. However, since the self-test circuit is built into the memory device and cannot be changed, it is difficult to flexibly change the test method as the manufacturing process is improved.
  • an object of the present invention is to provide a test apparatus, a memory device, and a test method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
  • the dependent claims define further advantageous specific examples of the present invention.
  • a test apparatus for testing a semiconductor device, wherein the programmable logic included in the semiconductor device operates as a self-test circuit that tests a memory area in the semiconductor device. Based on the test result obtained by the test unit by the program unit for programming and the test processing unit for testing the memory area in the semiconductor device by acquiring the test result by operating the self-test circuit, and the self-test circuit, A test apparatus is provided that includes a determination unit that determines the quality of the semiconductor device.
  • the semiconductor device may be a memory under test!
  • the program unit programs the programmable logic to thereby access the memory area in the self test by the self test circuit, and data to be written to the memory area in the self test. Set at least one of the values.
  • the program unit sequentially programs a plurality of types of self-test circuits that perform different self-tests into the programmable logic, and the test processing unit programs each of the self-test circuits into the programmable logic.
  • the test processing unit programs each of the self-test circuits into the programmable logic.
  • the memory area is tested, and the determination unit determines the quality of the semiconductor device based on the test results of a plurality of types of self-test circuits.
  • the semiconductor device includes two or more of the programmable logic, and in parallel with the self test by the first self test circuit programmed in the first programmable logic, the program unit includes: The second self-test circuit is programmed in the second programmable logic, and the test processing unit is configured to transmit the first self-test circuit.
  • the memory region may be tested by operating the second self-test circuit in response to completion of the test according to the above and completion of the program of the second self-test circuit.
  • a test apparatus includes a plurality of types of self-test circuits that perform different self-tests according to a test result of the first self-test circuit, and then to the programmable logic.
  • a selection unit for selecting the second self-test circuit to be programmed may be further provided.
  • the program unit programs the first self-test circuit, which performs a read / write test for testing whether or not the written data is read out, into the memory area in the semiconductor device in the programmable logic. Then, as a result of the test by the first self-test circuit, when a defect is detected in the first partial area which is a part of the memory area, the defect position in the first partial area is The second self-test circuit to be recorded in the second partial area that is a part of the memory area and in which no defect is detected is programmed in the programmable logic, and the test processing unit is configured to perform the second self-test.
  • the second partial region may be read by issuing a memory read command to the semiconductor device after the operation of the circuit is completed.
  • the program unit may program the programmable logic that records the bit map indicating the quality of each bit in the first partial area in the second partial area as the second self-test circuit. .
  • the test processing unit issues a memory write command to the semiconductor device after the self-test circuit is programmed, thereby providing another to the first partial region that is a part of the memory region.
  • a self-test for writing the basic data pattern to the memory area other than the first partial area is performed. It may be done.
  • the test processing unit starts the operation of the self-test circuit through a scan interface provided separately from a memory interface used for memory access in the normal operation of the semiconductor device, and acquires a test result. May be.
  • the program unit externally transmits one of fail information indicating whether or not a force is detected by a self test and fail content information indicating a defect position in the semiconductor device.
  • the self-test circuit which is selected according to a force instruction and is output via the scan interface, is programmed into the programmable logic, and the test processing unit outputs the semiconductor device force and the fail presence / absence information, and the fail When the presence / absence information indicates that a failure is detected, the semiconductor device device may further output the fail content information.
  • the program unit may program the programmable logic so that the semiconductor device normally operates when the determination unit determines that the semiconductor device is a non-defective product.
  • a memory unit for storing write data and a self-test circuit for testing a memory area in the memory unit are externally provided.
  • a programmable logic device that is programmed by the test apparatus and tests the memory area in accordance with an instruction from the test apparatus and outputs a test result to the test apparatus.
  • the memory device inputs a memory interface used for memory access in a normal operation of the memory device and an instruction to start the operation of the self-test circuit from the test device, and a test result is input to the test device. And a first scan interface that outputs to the.
  • the memory device is connected to another memory device, outputs an input signal from the test apparatus to the first scan interface to the other memory device, and inputs an input signal of the other memory device power.
  • a second scan interface for outputting to the test apparatus via the first scan interface may be further provided.
  • a test method for testing a semiconductor device with a test apparatus wherein the programmable logic included in the semiconductor device is used as a self-test circuit for testing a memory area in the semiconductor device.
  • FIG. 1 shows a test apparatus 10 according to the present embodiment and memory under test 20-1 to N connected to the test apparatus 10 to be tested.
  • FIG. 4 shows a functional configuration of the test apparatus 10.
  • FIG. 5 shows a first example of processing in which the memory under test 20-1 is tested by the test apparatus 10.
  • FIG. 6 is a time chart showing the state change of the memory under test 20-1 in the test of the first example.
  • FIG. 7 shows a second example of processing in which the memory under test 20-1 is tested by the test apparatus 10.
  • FIG. 8 shows a configuration of a memory under test 20-1 according to a modification of the present embodiment.
  • FIG. 9 shows a configuration of a programmable logic 200-2 according to a modification of the present embodiment.
  • FIG. 10 shows a first example of processing in which the memory under test 20-1 is tested by the test apparatus 10 according to the modification of the present embodiment.
  • FIG. 11 shows a second example of a process in which the memory under test 20-1 is tested by the test apparatus 10 according to the modification of the present embodiment.
  • FIG. 1 shows a test apparatus 10 according to the present embodiment and memory under test 20-1 to 20-N connected to the test apparatus 10 and being tested.
  • the test apparatus 10 is connected to the memory under test 20-1 via a scan interface.
  • the memory under test 20-1 is a memory device that may have logic circuits and multiple registers for force testing. The values of these registers are set from the test apparatus 10 via the scan interface. Further, the memory under test 20-1 has another scan interface different from the scan interface connected to the test apparatus 10, and is connected to the memory under test 20-2 via the other scan interface.
  • the register value of the memory under test 20-2 is set from the test apparatus 10 via the scan interface and the memory under test 20-1.
  • the memory under test 20-2 has another scan interface that is different from the scan interface connected to the memory under test 20-1, and the memory under test 20-3 and the device under test 20-2 are connected via the other scan interface. Connected to memory 20-4. Similarly to the memory under test 20-2, the memory under test 20-3 and the memory under test 20-4 are also indirectly connected to the test apparatus 10 via the memory under test 20-1 and the test apparatus 10 Receive the register value setting. In this way, a value is set in each register of the memory under test, and a test according to the set value is performed.
  • Each memory under test has programmable logic such as FPGA (Field Programmable Gate Array).
  • the test apparatus 10 programs a self-test circuit (Built In Self Test) in the programmable logic of each memory under test via a scan interface, and the self-test circuit determines whether each device is good or bad. Judgment. This aims to eliminate the need for high-speed signal exchange with each memory device.
  • FIG. 2 shows a configuration of the memory under test 20-1.
  • the memory under test 20-1 has two or more programmable logic, for example, programmable logic 200-1 and 2. Further, the memory under test 20-1 includes a memory unit 210, a first scan interface 220, a second scan interface 230, a memory interface 240, and a configuration interface 250.
  • a self-test circuit for testing a memory area in the memory unit 210 is programmed by the external test apparatus 10. Then, the programmable logic 200-1 tests the memory area by this self-test circuit in accordance with an instruction from the test apparatus 10 and outputs a test result to the test apparatus 10.
  • Programmable logic 200-2 is almost identical to programmable logic 200-1. However, the programmable logic 200-2 may be programmed with a different type of self-test circuit from the self-test circuit programmed in the programmable logic 200-1.
  • the memory unit 210 is a memory area for storing data acquired by an external force or outputting the data in response to an external request. That is, for example, the memory unit 210 stores write data in response to receiving a memory write command from the outside.
  • the memory interface 240 is used for memory access in the normal operation of the memory under test 20-1.
  • the first scan interface 220 inputs an instruction to start the operation of the self-test circuit from the test apparatus 10 and outputs a test result to the test apparatus 10.
  • the second scan interface 230 is connected to another memory device (for example, the memory under test 20-2).
  • the second scan interface 230 outputs an input signal from the test apparatus 10 to the first scan interface 2 20 to the memory under test 20-2, and inputs an input signal from the memory under test 20-2 to the first scan interface. Output to the test apparatus 10 via 220.
  • FIG. 3 shows the configuration of the programmable logic 200-1.
  • the programmable logic 200 — 1 inputs a scan input data signal (SIN) and a scan enable signal (SE) from the test apparatus 10 via the first scan interface 220. These signals are input to one end of the scan chain in the memory unit 210. The signal from which the other end of the scan chain is also output is output to the memory under test 20-2 via the second scan interface 230. Data input / output to / from the scan chain is performed in synchronization with the reference clock signal (SCLK) of the scan chain.
  • Programmable logic 200 — 1 receives self-test circuit program via configuration interface 250.
  • a self-test circuit is programmed by a program process by a program unit 400 described later.
  • This self-test circuit includes an AND gate 300, a PLL circuit 310, a pattern generation circuit 320, a fail information recording unit 385, a compression circuit 390, and an output selection circuit 395.
  • the AND gate 300 is supplied with a reference clock signal (SCLK) for the scan chain and a reference clock signal (CLK) for operating the programmable logic.
  • the AND gate 300 supplies the logical product of these reference clocks to the output selection circuit 395. As a result, the operation of the output selection circuit 395 is synchronized with the reference clock signal of the scan chain and the reference clock signal of the programmable logic.
  • the PLL circuit 310 multiplies the reference clock signal (CLK) so as to have a higher frequency to obtain a memory clock signal (MCLK), and supplies the memory clock signal (MCLK) to the pattern generation circuit 320. More specifically, the PLL circuit 310 starts to multiply the reference clock signal (SCLK) when the input data signal (SIN) of the scan interface is input as the PLLENABLE signal. When the multiplied signal becomes stable, the PLL circuit 310 outputs a PLLEND signal to the pattern generation circuit 320.
  • CLK reference clock signal
  • MCLK memory clock signal
  • the pattern generation circuit 320 includes an AND gate 315, a counter 325, a state machine 330, an address register 340, a command register 350, a data register 360, an I / O buffer 370, and a comparator 380.
  • the AND gate 315 outputs a logical product of the PLLEND signal and the reference clock signal (MCLK) to the counter 325. That is, the counter 325 starts counting the number of clock cycles of the reference clock signal (MCLK) when the reference clock signal (MCLK) is stabilized.
  • the state machine 330 operates based on the counter value of the counter 325, and tests the memory unit 210.
  • the state machine 330 includes multiple logic circuits, each for performing a different type of self-test. Specifically, one logic circuit performs a test to write a predetermined data string in the column direction of the memory unit 210, and the other logic circuit performs a test in the row direction of the memory unit 210. A test for writing a predetermined data string may be performed. In any test, the state machine 330 is set with at least one of an address order for accessing the memory unit 210 in the self-test by the self-test circuit and a data value to be written in the memory unit 210 in the self-test.
  • the address register 340 sequentially acquires a plurality of address values from the state machine 330 and stores them.
  • the command register 350 sequentially acquires a plurality of commands from the state machine 330 and stores them.
  • the data register 360 sequentially acquires and stores a plurality of data values by the state machine 330.
  • the IZO buffer 370 outputs the data value stored in the data register 360 to the memory unit 210. As a result, data is written into the memory unit 210. Further, after completion of the data writing, the I / O buffer 370 reads the data from the memory unit 210 and outputs it to the comparator 380.
  • the comparator 380 compares the data value stored in the data register 360 (ie, the value of the written data) with the data value stored in the buffer 370 (ie, the value of the read data). When the values of these data are different, the comparator 380 outputs a logical value of true as a fail presence / absence signal indicating whether or not a failure is detected by the self-test.
  • the fail information recording unit 385 When the fail information recording unit 385 inputs a logical value true as a fail presence / absence signal, the address value is read from the address register 340, the written data value is read from the data register 360, and the read data value is read. ⁇ ⁇ ⁇ ⁇ Read from Noffer 370. As a result, each time an error occurs, the address of the memory cell in which the error has occurred and the status of the error can be recorded.
  • the compression circuit 390 reads these recorded address values and data values from the fail information recording unit 385, and performs data compression such as serialization. Then, the compression circuit 390 outputs these address values and data values subjected to data compression to the output selection circuit 395 as fail content information indicating a defective position in the memory under test 20-1.
  • the output selection circuit 395 operates in synchronization with the reference clock signal (SCLK) and the reference clock signal (CLK). Then, the output selection circuit 395 selects one of the fail content information and the fail presence / absence information according to an instruction from an external force, and outputs it as a scan output signal (SOUT) via the first scan interface 220.
  • This instruction may be input as a scan enable signal (SE).
  • SE scan enable signal
  • the output selection circuit 395 scans When the enable signal (SE) is logically true and the pattern end signal is received from the counter 325, fail content information is output, and in other cases, fail presence / absence information is output. May be.
  • the test apparatus 10 can select the type of information to be acquired by changing the value of the scan enable signal (SE).
  • the configuration of the programmable logic 200-2 and the programmable logic included in the memories under test 20-2-N is substantially the same as the configuration of the programmable logic 200-1 illustrated in FIG.
  • FIG. 4 shows a functional configuration of the test apparatus 10.
  • the test apparatus 10 includes a program unit 400, a test processing unit 410, a determination unit 420, and a selection unit 430.
  • the program unit 400 programs the programmable logic 200-1 included in the memory under test 20-1 so as to operate as a self-test circuit that tests the memory unit 210 within the memory under test 20-1.
  • the configuration interface 250 is used to program the self-test circuit.
  • the program process performed by the program unit 400 is a process of building a logic circuit in the programmable logic 200-1 that performs a predetermined process rather than simply writing a value to a register.
  • the program unit 400 may sequentially program a plurality of types of self-test circuits that perform different self-tests into the programmable logic 200-1 or the programmable logic 200-2.
  • the test processing unit 410 operates the self-test circuit to test the memory unit 210 in the memory under test 20-1, and obtains a test result. For example, the test processing unit 410 outputs fail information from the memory under test 20-1, and if the fail presence information indicates that a failure has been detected, the test processing unit 410 further outputs the fail content information from the memory under test 20-1. It may be output.
  • the first scan interface 220 is used to select information to be output and obtain test results.
  • the determination unit 420 determines pass / fail of the memory under test 20-1 based on the test result by the self-test circuit.
  • the selection unit 430 is a second self-test circuit to be programmed in the programmable logic 200-1 next, among a plurality of types of self-test circuits that perform different self-tests according to the test result of the first self-test circuit. May be selected.
  • the program unit 400 converts the selected second self-test circuit into the first self-test circuit. Instead, it is programmed to the programmable logic 200-1.
  • the programmed circuit is used for the test by the test processing unit 410 as described above.
  • the communication between the test apparatus 10 and the memory under test 20-1 uses a relatively low-speed scan interface. If used, it will be sufficient. As a result, not only a test apparatus capable of high-speed operation exclusively for memory, but also a logic tester operating at a relatively low speed can be used as the test apparatus 10.
  • FIG. 5 shows a first example of processing in which the memory under test 20-1 is tested by the test apparatus 10.
  • the program unit 400 programs the programmable logic 200-1 so as to operate as a first self-test circuit (S500).
  • the test processing unit 410 tests the memory unit 210 by operating the programmed self-test circuit every time the self-test circuit is programmed into the programmable logic 200-1 and 2 (S510).
  • the test processing unit 410 may send an instruction to start the test to the programmable logic 200-1, for example, by setting the scan input data signal (SIN) to a logical value true!
  • SIN scan input data signal
  • the test processing unit 410 determines whether or not the test is completed by monitoring the scan output data signal (SOUT) (S520). When the test is completed (S520: YES), the test processing unit 410 acquires the test result from the programmable logic 200-1 (S530). The determination unit 420 determines pass / fail of the memory under test 20-1 based on the test result by the first self-test circuit (S540). The selection unit 430 selects the second self-test circuit to be programmed next in the programmable logic 200-1 among the plurality of types of self-test circuits that perform different self-tests according to the test result of the first self-test circuit. Select the test circuit (S55 0).
  • the program unit 400 programs the second self-test circuit into the programmable logic 200-1 (S560).
  • the test processing unit 410 tests the memory under test 20-1 by operating the second self-test circuit (S570).
  • the determination unit 420 obtains the test result from the programmable logic 200-1 (S590). Then, the determination unit 420 determines pass / fail of the memory under test 20-1 based on the test result (S595).
  • the determination unit 420 can obtain test results from a plurality of types of self-test circuits. The quality of the memory under test 20-1 can be determined based on the above. Furthermore, the type of the next self-test can be determined based on the test result of the first self-test circuit, and an efficient and effective test schedule can be set.
  • FIG. 6 is a time chart showing the state change of the memory under test 20-1 in the test of the first example.
  • the programmable logic 200-1 receives the program of the self-test circuit.
  • the programmable logic 200-1 starts operating upon receiving the scan enable signal (SE), and first sets the value of each register on the scan chain based on the scan input data signal (SI). To do.
  • the programmable logic 200-1 uses the PLL circuit 310 to generate a reference clock signal (MCLK).
  • MCLK reference clock signal
  • the state machine 330 sequentially performs multiple types of self-tests.
  • the self test (X-March) is a test in which a predetermined data string (for example, a series of 010101) is written in the column direction of the memory cell and the written data string is read.
  • the self test (Y-March) is a test in which a predetermined data string is written in the memory cell row direction and the written data string is read.
  • the self-test (Disturb) is a test that determines whether or not the write power of a memory cell affects the value of its surrounding memory cells.
  • FIG. 7 shows a second example of a process in which the memory under test 20-1 is tested by the test apparatus 10.
  • the type of circuit to be programmed as the second self-test circuit does not depend on the result of the test by the first self-test circuit. Therefore, the second self-test circuit can be programmed without waiting for the completion of the test by the first self-test circuit. The purpose is to improve the efficiency of the test by reducing the time required for the entire test.
  • the program unit 400 programs the first self-test circuit into the programmable logic 200-1 (S700).
  • the test processing unit 410 is a test unit that operates the first self-test circuit.
  • An instruction to start the test is sent to the programmable logic 200-1 (S710).
  • the program unit 400 programs the second self-test circuit in the programmable logic 200-2. (S720).
  • the test processing unit 410 operates the second self-test circuit.
  • the memory unit 210 is tested (S740).
  • the test processing unit 410 obtains the results of the first and second self tests from the programmable logic 200-1 and the programmable logic 200-2. (S760). Then, the determination unit 420 determines pass / fail of the memory under test 20-1 based on these test results (S770).
  • the second self-test circuit can be programmed while the test of the first self-test circuit is in progress, and the time required for the entire test can be shortened.
  • FIG. 8 shows a configuration of a memory under test 20-1 according to a modification of the present embodiment.
  • the memory unit 210 is divided into a plurality of partial areas, and each is used for different purposes. For example, a partial area determined as having no defect may be used as an area for recording fail content information of other partial areas.
  • a partial area determined as having no defect may be used as an area for recording fail content information of other partial areas.
  • data written in one partial area is duplicated in another partial area, it may be tested whether there is a failure in the duplication processing.
  • modified examples will be described.
  • the memory unit 210 includes a first partial region 215-1 and a second partial region 215-2. Each of these partial areas may be a memory bank of the memory under test 20-1, which is a memory device. That is, a memory 'bank in which no defect is detected may be used to test another memory' bank. Other configurations are substantially the same as the memory under test 20-1 illustrated in FIG. Further, the functional configuration of the test apparatus 10 according to the present modification is substantially the same as the functional configuration of the test apparatus 10 shown in FIG.
  • FIG. 9 shows a configuration of the programmable logic 200-2 according to a modification of the present embodiment.
  • the programmable logic 200-2 is programmed with a second self-test circuit that is different from the first self-test circuit programmed in the programmable logic 200-1.
  • the configuration of the second self-test circuit will be described with reference to FIG.
  • the logic 200-2 does not have to include the fail information recording unit 385, the compression circuit 390, and the output selection circuit 395.
  • the logic circuit included in the state machine 330 is different from the logic circuit included in the state machine 330 of FIG.
  • the programmable logic 200-2 outputs the pattern end signal output from the counter 325 as a scan output data signal (SOUT).
  • FIG. 10 shows a first example of a process in which the memory under test 20-1 is tested by the test apparatus 10 according to the modification of the present embodiment.
  • the program unit 400 programs the first self-test circuit for performing the read / write test into the programmable logic 200-1 (S1000).
  • the test processing unit 410 performs a read / write test by operating the first self-test circuit (S1010).
  • the determination unit 420 determines whether or not the first partial region 215-1 has a force detected as a result of the read / write test (S1030). In response to the detection of a defect (S1030: YES), the program unit 400 assigns the defect position of the first partial area 215-1 to the second part of the memory unit 210 where no defect is detected.
  • the second self-test circuit recorded in area 215-2 is programmed into programmable logic 200-2 (S1040). This program is a program for recording a bit map indicating the quality of each bit in the first partial area 215-1 in the second partial area 215-2.
  • the test processing unit 410 operates the second self-test circuit (S1050). After the operation of the second self-test circuit is completed (S1060: YES), the test processing unit 410 issues a memory read command to the memory under test 20-1 via the memory interface 240, thereby The area 215 2 is read (S 1070). The data read from the second partial area 215-2 can be used as fail content information.
  • the processing described with reference to FIG. 10 eliminates the need for a storage area for recording the fail content information in the programmable logic 200-1 and reduces the necessary capacity of the programmable logic 200-1 to reduce the program. Can be shortened.
  • FIG. 11 shows a second example of a process in which the memory under test 20-1 is tested by the test apparatus 10 according to the modification of the present embodiment.
  • Data written to a partial area with reference to the second example Explains the process to test whether the duplication process is faulty when duplicating the file in other partial areas.
  • the program unit 400 programs a self-test circuit in the programmable logic 200-1 (S1100).
  • the test processing unit 410 issues a memory write command to the memory under test 20-1, so that it is used for the read / write test of the second partial area 215-2 with respect to the first partial area 215-1.
  • the basic data pattern to be written is written (S 1110). This basic data pattern is transferred at high speed via the memory interface 240.
  • the test processing unit 410 starts the operation of the self-test circuit (S1120). As a result, the test processing unit 410 causes a self-test to write a basic data pattern to a memory area (for example, the second partial area 215-2) other than the first partial area 215-1.
  • the test processing unit 410 acquires the test result from the second partial area 215-2 of the memory under test 20-1 (1140).
  • the determination unit 420 determines pass / fail of the memory under test 20-1 based on the acquired test result (S 1150).
  • a memory device having a wide bus width and a high speed can be efficiently tested.

Abstract

La présente invention concerne un appareil de test prévu pour tester un dispositif à semi-conducteurs ayant une zone de mémoire. L'appareil de test est muni d'une section de programme pour programmer une logique programmable prévue dans le dispositif à semi-conducteurs pour fonctionner comme circuit d'auto-test afin de tester la zone de mémoire du dispositif à semi-conducteurs, d'une section de traitement du test pour tester la zone de mémoire dans le dispositif à semi-conducteurs en faisant fonctionner le circuit d'auto-test et en acquérant les résultats du test, ainsi que d'une section d'évaluation pour évaluer la conformité du dispositif à semi-conducteurs en fonction des résultats de test du circuit d'auto-test.
PCT/JP2007/055267 2006-03-22 2007-03-15 Appareil et procede de test et dispositif de memoire WO2007108400A1 (fr)

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JP2010040085A (ja) * 2008-08-01 2010-02-18 Fujitsu Microelectronics Ltd 集積回路および試験方法

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WO2000062339A1 (fr) * 1999-04-14 2000-10-19 Hitachi, Ltd. Circuit integre semi-conducteur, procede de verification et procede de fabrication d'un tel circuit
JP2002197900A (ja) * 2000-12-25 2002-07-12 Matsushita Electric Ind Co Ltd 半導体集積回路および半導体集積回路のメモリテスト方法

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Publication number Priority date Publication date Assignee Title
WO2000062339A1 (fr) * 1999-04-14 2000-10-19 Hitachi, Ltd. Circuit integre semi-conducteur, procede de verification et procede de fabrication d'un tel circuit
JP2002197900A (ja) * 2000-12-25 2002-07-12 Matsushita Electric Ind Co Ltd 半導体集積回路および半導体集積回路のメモリテスト方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010040085A (ja) * 2008-08-01 2010-02-18 Fujitsu Microelectronics Ltd 集積回路および試験方法

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