WO2007094044A1

WO2007094044A1 - Semiconductor device manufacturing method and semiconductor manufacturing apparatus

Info

Publication number: WO2007094044A1
Application number: PCT/JP2006/302524
Authority: WO
Inventors: Yoshiyuki Nakao; Noriyoshi Shimizu
Original assignee: Fujitsu Limited
Priority date: 2006-02-14
Filing date: 2006-02-14
Publication date: 2007-08-23
Also published as: JPWO2007094044A1

Abstract

[PROBLEMS] To provide a method for manufacturing a semiconductor device having a cap layer having high barrier characteristics and to provide a semiconductor manufacturing apparatus which can form the cap layer having the high barrier characteristics. [MEANS FOR SOLVING PROBLEMS] A semiconductor device manufacturing method is provided with a step of forming a third interlayer insulating film (10) above a silicon substrate (1); a step of forming a first wiring groove (10a) or a first hole on the third interlayer insulating film (10); a step of forming a first copper wiring (12a) by embedding copper in the first wiring groove (10a) and the first hole; a step of forming a zirconium nitride film as a cap layer (13) on the third interlayer insulating film (10) and the first copper wiring (12a); and a step of annealing the cap layer (13) in the atmosphere containing nitrogen.

Description

Specification

Semiconductor device manufacturing method and semiconductor manufacturing apparatus

Technical field

The present invention relates to a semiconductor device manufacturing method and a semiconductor manufacturing apparatus.

Background art

[0002] With the high integration of semiconductor devices and the reduction in chip size, miniaturization of wiring and multilayer wiring have been accelerated! / Speak. In a logic device having such a multilayer wiring structure, in order to reduce wiring resistance, it has been put into practical use to form wiring using copper, which is a low-resistance metal.

[0003] Since a copper film is very difficult to pattern compared to an aluminum film, it is extremely difficult to form a copper wiring by patterning the copper film. Therefore, the damascene method is usually adopted in which copper wiring is formed by embedding a copper film in the holes and grooves of the insulating film.

[0004] The upper and lower copper wirings are connected to each other by copper plugs. If the surface of the lower copper wiring is contaminated, corroded, or oxidized during the process, a connection failure occurs between the copper plug and the copper wiring. There is a fear. Therefore, when manufacturing a semiconductor device provided with copper wiring, a cap layer for protecting the copper wiring is required.

Among the cap layers, the zirconium nitride (ZrN) film has an insulating property on the insulating film and conductivity on the copper wiring. Even if no hole is formed, there is an advantage that the upper and lower copper wirings are electrically connected via the cap layer.

[0006] Patent Document 1 discloses that the zirconium nitride film is formed as a cap layer in this way.

[0007] On the other hand, according to Patent Document 2, it is considered that the zirconium nitride film formed by the conventional method is nitrogen-rich, and ammonia (NH 3) is added to the deposition gas for the zirconium nitride film.

Therefore, nitrogen in the film is supposed to be reduced.

[0008] The zirconium nitride film formed as the cap layer has a role of protecting the copper wiring. It also serves as a barrier layer that prevents copper in the wiring from diffusing into the surrounding insulating film and prevents electrical shorting between adjacent copper wirings. Furthermore, as with the formation of other films such as interlayer insulation films and copper films, when forming a zirconium nitride film, the generation of particulates should be suppressed, device defects caused by particles can be reduced, and yields can be improved. It is necessary to let

Patent Document 1: Japanese Patent Application Laid-Open No. 2003-17496

Patent Document 2: JP 2002-146535 A

Disclosure of the invention

An object of the present invention is to provide a method for manufacturing a semiconductor device provided with a cap layer having a high noria property, and a semiconductor manufacturing apparatus capable of forming a cap layer having a high barrier property.

[0010] According to one aspect of the present invention, a step of forming a first insulating film above a semiconductor substrate, a step of forming a first groove or a first hole in the first insulating film, and the first Forming a first copper wiring by burying copper in the trench or the first hole; forming a zirconium nitride film as a cap layer on the first insulating film and the first copper wiring; There is provided a method for manufacturing a semiconductor device, comprising the step of annealing the cap layer in a nitrogen-containing atmosphere.

According to the present invention, since the cap layer is annealed in a nitrogen-containing atmosphere, the nitrogen concentration in the zirconium nitride film constituting the cap layer is increased, and the barrier property of the cap layer against copper is improved.

[0012] Further, in the step of forming the cap layer, TDE AZ (Zr [N (C H)]) gas is used as a raw material gas for zirconium nitride, and ammonia gas is not added to the raw material gas.

2 5 2 4

The cap layer is preferably formed by a CVD (Chemical Vapor Deposition) method.

[0013] By not using ammonia gas in this way, the number of particles generated during the formation of the cap layer can be reduced, and device defects associated with particles can be prevented.

Furthermore, since the zirconium nitride film formed without using ammonia has a poor film quality, nitrogen easily enters the film during the annealing process in a nitrogen-containing atmosphere. As a result, it becomes possible to obtain a cap layer having a high nitrogen concentration and excellent copper noria properties.

[0015] Preferably, the step of forming the cap layer and the step of annealing the cap layer are performed in the same chamber.

By performing these steps in the same chamber, the cap layer is not exposed to an oxygen-containing atmosphere before annealing, so that it is difficult for oxygen to be taken into the cap layer, the oxygen concentration is low, and the underlying first copper wiring is formed. It becomes possible to form a cap layer that is difficult to oxidize.

[0017] Further, according to another aspect of the present invention, a chamber, a substrate mounting table provided in the chamber and on which a semiconductor substrate is mounted, a heater provided on the substrate mounting table, A shower head provided above the substrate mounting table in the chamber and having a hollow inside and a gas dispersion hole communicating with the hollow is formed, and a microwave is applied to the cavity inside the shower head. A magnetron to be supplied; a nitrogen gas pipe and a zirconium nitride raw material gas pipe communicating with a cavity inside the shower head; a nitrogen gas flow rate adjusting unit provided in the nitrogen gas pipe; and the zirconium nitride raw material A raw material gas flow rate adjusting unit provided in the gas pipe, a magnetron, the nitrogen gas flow rate adjusting unit, and a control unit for controlling the raw material gas flow rate adjusting unit. When the zirconium nitride film is formed in the chamber, the raw material gas flow rate control unit is controlled to introduce the zirconium raw material gas into the shower head, and in the chamber, the nitrogen annealing gas is introduced into the chamber. A semiconductor manufacturing apparatus that controls the nitrogen gas flow rate control unit to introduce nitrogen gas into the shower head and controls the magnetron to introduce microwaves into the cavity of the shower head. The

[0018] According to the present invention, it is possible to continuously perform the formation of a zirconium nitride film and the annealing of the zirconium nitride film in a nitrogen-containing atmosphere in one chamber. Therefore, annealing can be performed before the zirconium nitride film is exposed to the oxygen-containing atmosphere. Therefore, it is difficult to oxidize copper wiring or the like with a low oxygen concentration. Annealing can increase the nitrogen concentration of the zirconium nitride film and improve the barrier property against copper.

Brief Description of Drawings FIG. 1 (a) and (b) are cross-sectional views (part 1) showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIGS. 2 (a) and 2 (b) are cross-sectional views (part 2) showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

3 (a) and 3 (b) are cross-sectional views (part 3) showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view (part 4) showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a graph showing the relationship between the flow rate of ammonia gas added to the deposition gas for the zirconium nitride film and the particles.

FIGS. 6 (a) and 6 (b) are enlarged cross-sectional views schematically showing the mechanism of nitrogen annealing in the first embodiment of the present invention.

[Fig. 7] Fig. 7 is a diagram summarizing the advantages obtained by the first embodiment of the present invention.

FIG. 8 is a diagram obtained by investigating the diffusion of copper into the cap layers of the first embodiment and the comparative example of the present invention by XPS (X-ray Photoelectron Spectroscopy) method.

FIG. 9 is a top view of a semiconductor manufacturing apparatus used in the second embodiment of the present invention.

FIG. 10 is a configuration diagram of a nitrogen annealing chamber provided in the semiconductor manufacturing apparatus used in the second embodiment of the present invention.

FIG. 11 is a configuration diagram of a processing chamber provided in a semiconductor manufacturing apparatus used in the third embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0021] (1) First embodiment

1 to 3 are cross-sectional views showing manufacturing steps of the semiconductor device according to the first embodiment of the present invention.

First, the cross-sectional structure shown in FIG. 1 (a) will be described. On the p-type silicon (semiconductor) substrate 1, an element isolation insulating layer 2 surrounding the active element region is formed. A MOS transistor 3 is formed in the active element region. The MOS transistor 3 includes a gate electrode 3b formed on the silicon substrate 1 via a gate insulating film 3a, and a first LDD (Lightly Doped Drain) structure formed in the silicon substrate 1 on both sides of the gate electrode 3b. 1. It has second n-type impurity diffusion layers 3c and 3d. Insulating sidewalls 3e are formed on the side surfaces of the gate electrode 3b.

On the silicon substrate 1, a first made of silicon oxide (SiO 2) covering the MOS transistor 3 is formed.

2

An interlayer insulating film 4 is formed. Of the first interlayer insulating film 4, a first contact hole 4a and a second contact hole 4b are formed on the first n-type impurity diffusion layer 3c and the second n-type impurity diffusion layer 3d, respectively. Te!

[0025] A first conductive plug 5a and a second conductive plug 5b are embedded in the first and second contact holes 4a and 4b, respectively. The first and second conductive plugs 5a and 5b have a two-layer structure of a titanium nitride film and a tungsten film, respectively.

[0026] On the first interlayer insulating film 4, a first layer wiring 7 made of aluminum connected to the second conductive plug 5b is formed. On the first interlayer insulating film 4 and the first-layer wiring 7, a second interlayer insulating film 8 made of any of silicon oxide, BPSG, PSG, etc. is formed. A contact hole 8a is formed on the first conductive plug 5a in the second interlayer insulating film 8, and a third conductive film having a two-layer structure of a titanium nitride film and a tungsten film is formed therein. Plug 9 is embedded.

The second interlayer insulating film 8 and the third conductive plug 9 are covered with a third interlayer insulating film 10 made of 350 nm thick silicon oxide. In the third interlayer insulating film 10, a first wiring groove 10a and a second wiring groove 10b are formed.

[0028] The first wiring groove 10a has a shape in which a part thereof overlaps the third conductive plug 9.

In the first wiring trench 10a, a first copper wiring 12a having a multilayer structure composed of a noria metal layer 1la such as tantalum, tantalum nitride, and titanium nitride and 1 lb of a copper layer is formed. A second copper wiring 12b having the same layer structure as the first copper wiring 12a is formed in the second wiring groove 10b.

Next, steps required until a sectional structure shown in FIG. [0030] First, the silicon substrate 1 is placed in a CVD chamber (not shown), and the substrate temperature is stabilized at about 300 ° C. Then, tetrakisjetylaminozirconium (Zr [N (CH

twenty five

]]: TDEAZ) was vaporized at a temperature of 110 ° C to 140 ° C in a vaporizer, and the vaporized TDEAZ was

twenty four

Supply to chamber with carrier gas. As the carrier gas, nitrogen gas having a flow rate of 200 to 500 sccm, more preferably 300 sccm is employed in the present embodiment. Further, the supply amount of the vaporized TDEAZ is not particularly limited, but in this embodiment, the supply amount is set to 0.01 to 0.1 lgZmin, more preferably 0.05 gZmin.

[0031] Then, after the pressure is stabilized at about 4 Pa, this state is maintained for about 1 minute, whereby FIG.

As shown in (b), a cap layer 13 made of zirconium nitride is formed on each of the first and second copper wirings 12a, 12b and the third interlayer insulating film 10 to a thickness of about lOnm by the CVD method. It is done.

[0032] The ZrN cap layer 13 formed in this way becomes a conductive layer 13a having a specific resistance of about 100 Ω'cm or less in the region in contact with the first and second wirings 12a and 12b. In the region in contact with the third interlayer insulating film 10, the insulating layer 13 b having a specific resistance value of approximately infinite is obtained.

[0033] Here, if the thickness of the ZrN cap layer 13 is greater than 20 nm, the resistance of the conductive layer 13a increases, and the contact resistance with the copper wiring formed later on the conductive layer 13a becomes too high. Therefore, the ZrN cap layer 13 is preferably formed to a thickness of 20 nm or less! /.

[0034] Furthermore, if the substrate temperature when forming the ZrN cap layer 13 is too low, the film formation rate drops considerably. Therefore, it is preferable to form the ZrN cap layer 13 at a substrate temperature of 200 ° C or higher.

[0035] If the substrate temperature is too high, the already formed copper wirings 12a, 12b and the like are deteriorated by heat. Therefore, it is preferable to form the ZrN cap layer 13 at a substrate temperature of 400 ° C or lower. Good.

[0036] Furthermore, if the deposition pressure of the ZrN cap layer 13 is too high, the formation reaction of zirconium nitride is promoted in the deposition atmosphere, and there is a possibility that particles composed of zirconium nitride lumps are generated. Therefore, the deposition pressure of the ZrN cap layer 13 is preferably a low pressure of about 2 to 50 Pa.

[0037] Next, steps required until a sectional structure shown in FIG. [0038] First, the residual gas in the chamber is exhausted without removing the silicon substrate 1 from the chamber. At this time, the silicon substrate 1 is heated to about 400 ° C.

Next, as shown in FIG. 2 (a), the ZrN cap layer 13 is annealed by introducing nitrogen into the chamber while the substrate is heated to this temperature. Thereby, nitrogen is taken into the film of the ZrN cap layer 13 and the nitrogen concentration of the ZrN cap layer 13 is increased. During the annealing, the pressure of the nitrogen atmosphere is set to lkPa to lMPa, for example lOOkPa. If this nitrogen annealing is performed at a pressure higher than atmospheric pressure, transfer the substrate 1 to the pressurized chamber and perform annealing.

In addition, if the substrate temperature is too low in this nitrogen anneal, the reactivity between nitrogen and the ZrN cap layer 13 becomes low, and it is difficult for nitrogen to be taken into the ZrN cap layer 13. Therefore, the substrate temperature of the nitrogen anneal is preferably 200 ° C or higher.

[0041] When the substrate temperature exceeds 400 ° C, the copper wirings 12a, 12b, etc. may be deteriorated by heat. Therefore, it is preferable to perform nitrogen annealing on the ZrN cap layer 13 at a substrate temperature of 400 ° C. or lower.

Next, as shown in FIG. 2 (b), a fourth interlayer insulating film 14 made of silicon oxide having a thickness of 300, a silicon nitride film 15 having a thickness of 50, and a thickness of 350 A fifth interlayer insulating film 16 made of silicon oxide silicon is sequentially formed on the ZrN cap layer 13 by the CVD method. Instead of the silicon nitride film 15, a zirconium nitride film having a thickness of 20 or less may be used.

Subsequently, as shown in FIG. 3 (a), by patterning the fifth interlayer insulating film 16, a third wiring groove 16a partially overlapping the first copper wiring 12a is formed, and at the same time A fourth wiring groove 16b that partially overlaps the second copper wiring 12b is formed. Also, by patterning the fourth interlayer insulating film 14, the first via hole 14a is formed in the portion where the third wiring groove 16a and the first copper wiring 12a overlap, and at the same time, the fourth wiring groove 16b and the second copper wiring 14a are formed. A second via hole 14b is formed where the wiring 12b overlaps.

[0044] The order of the formation of the first and second via holes 14a, 14b and the formation of the third and fourth wiring grooves 16a, 16b may be the third and fourth wiring grooves 16a, whichever comes first. When forming 16b, the silicon nitride film 15 functions as an etching stop layer. When forming the first and second via holes 14a and 14b, the ZrN cap layer 13 is used as an etching stop layer. Function.

The via holes 14a and 14b are formed on the first-layer copper wirings 12a and 12b, respectively, and expose the conductive layer 13a of the ZrN cap layer 13 (see FIG. 1B).

Next, as shown in FIG. 3B, the inner and bottom surfaces of the first and second via holes 14a, 14b and the third and fourth wiring grooves 16a, 16b, and the fifth A barrier metal layer 17 is formed on the upper surface of the interlayer insulating film 16 to a thickness of 5 to 10 nm. The noria metal layer 17 is formed by a sputtering method. For example, the tantalum (Ta), the tantalum nitride (TaN), or a laminated film of these layers, or a titanium nitride (ΉΝ) force is also formed.

Further, a copper seed layer 18 is formed on the noria metal layer 17 to a thickness of 30 to 100 nm by sputtering.

Next, a copper layer 19 is formed on the copper seed layer 18 by an electrolytic plating method, whereby the third and fourth wiring grooves 16a and 16b and the first and second via holes 14a and 14b are completely formed. Embed. Here, the copper seed layer 18 becomes a part of the copper layer 19.

Thereafter, as shown in FIG. 4, the copper layer 19 and the barrier metal layer 17 formed on the upper surface of the fifth interlayer insulating film 16 are removed by a CMP (Chemical Mechanical Polishing) method. As a result, the copper layer 19, the copper seed layer 18 and the noria metal layer 17 remaining in each of the first and second via holes 14a and 14b are used as the first and second vias 20a and 20b. The copper layer 19 and the noria metal layer 17 remaining in the third and fourth wiring grooves 16a and 16b are used as the third and fourth copper wirings 21a and 21b.

[0050] The third copper wiring 21a is electrically connected to the first copper wiring 12a via the first via 20a and the ZrN cap layer 13. The fourth copper wiring 21b is electrically connected to the second copper wiring 12b through the second via 20b and the ZrN cap layer 13.

[0051] Further, a second cap layer having a thickness of 20 nm or less made of the same material as the ZrN cap layer 13 on the third and fourth copper wirings 21a, 21b and the fifth interlayer insulating film 16 ( After forming the interlayer insulating film, the copper wiring and the via according to the above-described process, a copper wiring having a multilayer structure is formed on the second interlayer insulating film 8. become.

Incidentally, the first and second via holes 20a, 20b are formed in the low resistance layer 13 of the ZrN cap layer 13. They are electrically connected to the first and second copper wirings 12a and 12b through a (see FIG. 1 (b)). In this case, since the first ZrN cap layer 13 becomes the high resistance layer 13b on the second interlayer insulating film 10 made of oxide silicon, the third copper wiring 21a and the fourth copper wiring 21b There is no short circuit through the 1 Zr N cap layer 13. However, since zirconium nitride is chemically stable and is less susceptible to oxidation than copper, there is no risk of oxidation or corrosion due to exposure through via holes or wiring trenches. Conductive Z-insulating protective film that prevents oxidation and corrosion.

[0053] According to the present embodiment described above, in forming the cap layer 13 made of zirconium nitride in the step of FIG. 1 (b), only TDEAZ and a carrier gas (nitrogen) are used as the deposition gas, As shown in Patent Document 2, ammonia gas is used.

The inventor of the present application investigated what inconvenience occurs when ammonia is added to the deposition gas of the zirconium nitride film as in Patent Document 2. The results are shown in Fig. 5.

[0055] In this investigation, after a zirconium nitride film was directly formed on a silicon wafer having a diameter of 8 inches, the number of particles having a size of 0.15 m or more adhered on the zirconium nitride film was examined. .

As shown in FIG. 5, particles are not generated if the flow rate of ammonia added to the film forming gas is 5 sccm or less. However, when the flow rate of ammonia is increased above 5 sccm, the number of particles increases rapidly. This is thought to be because the reactivity between TDEAZ and ammonia is extremely high, so the flow rate of ammonia is large, and a block of zirconium nitride is formed in the gas phase, and the block becomes particles.

In view of this point, in the present embodiment, ammonia is not used when the ZrN cap layer 13 is formed, so that device failure due to particles can be prevented. However, as shown in FIG. 5, since particles are not generated when the flow rate of ammonia is 5 sccm or less, ammonia having this flow rate or less may be added to the deposition gas for the ZrN cap layer 13. In the present embodiment, as described above, the flow rate of nitrogen, which is a carrier gas of TDEAZ, is set to 200 to 500 sccm. Therefore, the ammonia having a flow rate of 5 sccm or less has a flow rate of 1Z40 or less of the carrier gas. [0058] By the way, if ammonia gas is added to the film forming gas as described above or the amount of addition is reduced, the nitrogen concentration in the ZrN cap layer 13 is reduced, and the ZrN cap layer is reduced. There is a risk that the acid resistance of 13 will decrease the copper noriability.

Therefore, in this embodiment, as shown in FIG. 2 (a), annealing is performed on the ZrN cap layer 13 in a nitrogen atmosphere to compensate for the lack of nitrogen in the ZrN cap layer 13. did.

[0060] FIGS. 6 (a) and 6 (b) are enlarged cross-sectional views schematically showing the mechanism of this nitrogen annealing, FIG. 6 (a) is before annealing, and FIG. 6 (b) is the ZrN cap in annealing. FIG. 4 is an enlarged sectional view of a layer 13.

[0061] As shown in Fig. 6 (a), the ZrN cap layer 13 before annealing is formed without using ammonia gas which is a nitrogen supply source, so that nitrogen (N) is deficient in the film and sparse. The film quality is excellent.

On the other hand, in the annealing, as shown in FIG. 6 (b), nitrogen easily diffuses into the sparse ZrN cap layer 13, and the cap is made of dense zirconium nitride with a high nitrogen concentration. Layer 13 is obtained.

As described above, the ZrN cap layer 13 is formed by forming the ZrN cap layer 13 by adding the ammonia gas to the film forming gas or by reducing the amount of the applied force. Nitrogen can be easily diffused into the ZrN cap layer 13 by annealing in a nitrogen atmosphere while suppressing the generation of particles during the formation of the layers.

FIG. 7 is a diagram summarizing the advantages obtained by the present embodiment by investigating.

Of the samples in FIG. 7, Embodiments A and B do not add ammonia to the deposition gas of the ZrN cap layer 13 and anneal in a nitrogen-containing atmosphere after the deposition of the ZrN cap layer 13. The sample which performed is shown. In the embodiment A, the ZrN cap layer 13 was directly formed on an 8-inch silicon wafer in order to count the number of particles. On the other hand, in Embodiment B, the ZrN cap layer 13 was formed on the copper film in order to see the copper diffusion.

[0066] As shown in the figure, in Embodiment A, the number of particles is zero.

[0067] On the other hand, ammonia was added to the deposition gas for the ZrN cap layer 13 and the atmosphere was nitrogen-containing. In Comparative Example B where annealing was not performed, 2057 particles were generated.

[0068] Further, in Comparative Example A in which no ammonia is used, no particles are generated.

It was confirmed once again that the cause of particle generation is ammonia.

FIG. 8 shows a ZrN cap layer using the sample of Embodiment B and Comparative Examples C and D in FIG.

FIG. 6 is a diagram obtained by investigating the diffusion of copper into 13 by XPS (X-ray Photoelectron Spectroscopy).

[0070] In this investigation, in addition to the composition of the ZrN cap layer 13 immediately after film formation (after nitrogen annealing in this embodiment B), Zr after annealing in vacuum to accelerate copper diffusion was used. The composition of the N cap layer 13 was also investigated. The vacuum annealing was performed for 30 minutes at a substrate temperature of 450 ° C.

In Embodiment B immediately after film formation, the nitrogen concentration in the film is 40% or more, whereas in Comparative Example C, which does not perform nitrogen annealing, the nitrogen concentration is less than 10%. As a result, it was confirmed that the nitrogen concentration of the ZrN cap layer 13 was increased by the nitrogen annealing.

[0072] Further, in Embodiment B immediately after film formation, the oxygen concentration is as low as about 10%, whereas in Comparative Example C immediately after film formation, oxygen is 40% or more and the acid resistance is low. I understand that it is a trap. This is because, in Comparative Example C, the ZrN cap layer 13 was formed without using ammonia, so the film quality of the ZrN cap layer 13 became sparse, and oxygen easily penetrated into the film and zirconium was oxidized. It is believed that there is. On the other hand, the low oxygen concentration in Embodiment B is that the oxygen concentration of the ZrN cap layer 13 is improved by increasing the nitrogen concentration with nitrogen annealing, and oxygen is not easily taken into the ZrN cap layer 13. It is thought that this is because of summer.

[0073] Furthermore, in Comparative Example C after vacuum annealing, a large amount of copper of 90% or more diffuses, whereas in Embodiment B after vacuum annealing, the composition ratio is almost the same as that immediately after film formation. And copper is not diffusing. As a result, it was confirmed that the ZrN cap layer 13 whose nitrogen concentration was increased by annealing in a nitrogen atmosphere was very good in terms of noriality with respect to copper.

As described above, the ZrN cap layer 13 formed in the present embodiment is a dense film having an extremely small number of particles when forming it and a nitrogen concentration of 40% or more. As a result, it is possible to obtain a highly reliable copper wiring with a high withstand voltage of the insulating layer 13b. It becomes ability. Further, since the oxygen concentration of the ZrN cap layer 13 is low, the copper wiring 12a, the copper wiring 12a,

It can prevent 12b from becoming high resistance.

[0075] (2) Second embodiment

In the first embodiment, after forming the ZrN cap layer 13 of FIG. 1B using a CVD chamber, the CVD chamber was used continuously to perform nitrogen annealing of FIG. 2A.

In contrast, in the present embodiment, the nitrogen annealing is performed in a mixed atmosphere of nitrogen ions and nitrogen radicals.

FIG. 9 is a top view of the semiconductor manufacturing apparatus 100 used in the present embodiment.

The semiconductor manufacturing apparatus 100 includes a load lock chamber 101 for waiting a plurality of silicon substrates 1, a CVD chamber 102 for forming a zirconium nitride film, and a nitrogen chamber 103.

These chambers 101 to 103 are arranged around a transfer channel 104 in which the inside is a nitrogen atmosphere, and delivery of the silicon substrate 1 to each chamber 101 to 103 is performed by a robot 105.

Further, a slit valve 10 is provided between each of the chambers 101 to 103 and the transfer chamber 104.

6-108 are provided. The slit valves 106 to 108 are opened when the silicon substrate 1 is delivered by the robot 105, and are closed when processing is performed in the chambers 102 and 103, and the chambers are hermetically sealed.

FIG. 10 is a configuration diagram of the nitrogen annealing chamber 103.

As shown in FIG. 10, this chamber 103 has a gas inlet 203 for introducing nitrogen at the upper part and an exhaust outlet 204 for exhausting nitrogen at the lower part. The exhaust port 204 is connected to an exhaust pump (not shown), and the interior of the chamber 103 is reduced to a predetermined pressure by the exhaust pump.

In addition, a substrate mounting table 205 with a built-in heater 206 is provided on the bottom surface of the chamber 103, and the silicon substrate 1 on the substrate mounting table 205 is heated to a predetermined temperature by the heater 206.

[0084] Further, a magnetron 20 for generating a microwave is formed on the upper side surface of the chamber 103. 4 is connected. Note that the frequency of the microwave is not particularly limited, but a microwave of 2 GHz to 5 GHz, preferably 2.5 GHz is generated in the magnetron 204.

[0085] Then, a shield plate 205 made of metal having a plurality of holes 205a is disposed at an intermediate height of the chamber 103. The shield plate 205 is electrically connected to the chamber 103 that is at ground potential. The chamber 103 is partitioned into a plasma generation chamber 103a and a nitriding chamber 103b by the shield plate 205.

[0086] In the chamber 103 configured as described above, plasma is generated by microwaves in the nitrogen power plasma generation chamber 103a introduced from the gas introduction port 203. Plasma generation chamber 1

Since the plasma component in 03a does not enter the nitriding chamber 103b by the action of the shield plate 205, the silicon substrate 1 is in a state where the plasma atmosphere force is also isolated.

On the other hand, the nitrogen radicals and nitrogen ions generated in the plasma generation chamber 103a

It passes through 205, reaches the nitriding chamber 103b, and reaches the silicon substrate 1.

As described above, in this chamber 103, only nitrogen radicals and nitrogen ions are selectively guided to the silicon substrate 1 side, and the ZrN cap layer 13 on the silicon substrate 1 is directed to the silicon substrate 1 side by these nitrogen radicals and nitrogen ions. Nitrogen annealing is performed.

Next, a method for manufacturing a semiconductor device using a semiconductor manufacturing apparatus using such a semiconductor manufacturing apparatus will be described.

First, after obtaining the cross-sectional structure of FIG. 1A described in the first embodiment, the CVD chamber 1 of FIG.

The! /, ZrN cap layer 13 (see Fig. 1 (b)) is formed in 02.

Next, the silicon substrate 1 is taken out from the CVD chamber 102 and transferred to the nitrogen annealing chamber 103 via the transfer chamber 104.

At this time, the transfer chamber 104 has a nitrogen atmosphere and does not contain oxygen. Therefore, the silicon substrate 1 is not exposed to an oxygen-containing atmosphere.

02 will be transferred to the nitrogen annealing chamber 103.

Subsequently, the nitrogen annealing step shown in FIG. 2 (a) is performed in the nitrogen annealing chamber 103.

The conditions of the nitrogen annealing are not particularly limited, but in this embodiment, the nitrogen gas flow rate is 500 sccm, the pressure is 700 Pa, the microwave frequency is 2.5 GHz, the microwave power is 700 W, the basic Nitrogen annealing is performed at a plate temperature of 100 ° C to 400 ° C, for example, 200 ° C.

In this embodiment, nitrogen annealing is performed with nitrogen radicals or nitrogen ions because of the reactivity with the cap layer 13, so even if the lower limit of the substrate temperature is set to 100 ° C. lower than that of the first embodiment, the cap is used. A sufficient amount of nitrogen can be diffused into layer 13.

Thereafter, the basic structure of the semiconductor device according to the present embodiment is completed by performing the steps of FIGS. 2B to 4 described in the first embodiment.

In the present embodiment described above, the ZrN cap layer 13 is exposed to an atmosphere containing nitrogen radicals and nitrogen ions for nitriding. According to this, as in the first embodiment, the ZrN cap layer

Nitrogen diffuses into the layer 13, and a ZrN cap layer 13 having a high nitrogen concentration and a high copper noriality can be obtained.

[0098] As described with reference to FIG. 9, after forming the ZrN cap layer 13 in the CVD chamber 102, the silicon force is transferred to the nitrogen annealing chamber 103 via the transfer chamber 104 in a nitrogen atmosphere. Since the substrate 1 is transferred, the ZrN cap layer 13 is not exposed to the oxygen-containing atmosphere. As a result, oxygen can be prevented from being taken into the ZrN cap layer 13 before the nitrogen annealing is performed after the ZrN cap layer 13 is formed, and an increase in the oxygen content in the ZrN cap layer 13 can be suppressed. . As a result, it is possible to prevent the copper wirings 12a and 12b (see FIG. 1 (b)) under the ZrN cap layer 13 from being oxidized, and to obtain low-resistance and high-reliability copper wirings 12a and 12b. It becomes possible.

[0099] (3) Third Embodiment

In the second embodiment, deposition of the ZrN cap layer 13 and nitrogen annealing using nitrogen radicals or nitrogen ions were performed in separate chambers 102 and 103 (see FIG. 9).

[0100] On the other hand, in the present embodiment, these are performed in the same chamber.

[0101] FIG. 11 is a configuration diagram of a processing chamber 301 provided in the semiconductor manufacturing apparatus used in the present embodiment.

[0102] On the bottom surface of the processing chamber 301, a substrate mounting table 305 incorporating a heater 306 is provided, and an exhaust port 309 for exhausting the gas in the chamber 301 is provided. The silicon substrate 1 on the substrate mounting table 305 is heated to a predetermined temperature by the heater 306. The exhaust port 309 is connected to an exhaust pump (not shown), and the exhaust pump 309 No. 301 is depressurized to a predetermined pressure.

Then, a shower head 305 that also serves as a shield plate against microwaves is provided on the upper portion of the processing chamber 301 so as to face the substrate mounting table 305. The shower head 305 is made of metal and is maintained at the ground potential. Further, the interior of the shower head 305 is a cavity 305b, and a nitrogen gas pipe 307 and a zirconium nitride source gas pipe 308 are provided in communication with the cavity 305b.

[0104] Each of the pipes 307, 308 is provided with a nitrogen gas mass flow controller (nitrogen gas flow control unit) 311 and a raw material gas mass flow controller (raw material gas flow control unit) 312. The gas flow rate in 308 is adjusted by these mass flow controllers 311, 312. Each of the mass flow controllers 311 and 312 also has a function of cutting off the gas flow just by adjusting the gas flow rate.

[0105] Microwaves are supplied from the magnetron 304 to the cavity 305b inside the shower head 305.

The magnetron 304 and the mass flow controllers 311 and 312 are controlled by control signals S 1 to S 3 output from the control unit 315. The following processing performed in the processing chamber 301 is performed under the control of the control unit 315.

Next, a method for manufacturing a semiconductor device using the chamber 301 will be described.

First, after obtaining the cross-sectional structure of FIG. 1A described in the first embodiment, the silicon substrate 1 is put into the chamber 301 of FIG.

[0109] Next, TDEAZ vaporized at a temperature of 110 ° C to 140 ° C in the vaporizer is introduced into the shower head 305 from the raw gas piping 308 together with the carrier gas. The carrier gas is a nitrogen gas having a flow rate of S200 to 500 sccm, more preferably 300 sccm. The supply amount of vaporized TDEAZ is, for example, 0.01 to 0.1 lg / min, and more preferably 0.05 gZmin.

[0110] The TDEAZ and the carrier gas supplied in this manner are uniformly dispersed on the surface of the silicon substrate 1 by a plurality of gas dispersion holes 305a provided in the shower head 305.

[0111] Then, by stabilizing the pressure in the chamber 301 at about 4 Pa and maintaining this state for about 1 minute, the cap layer 13 made of zirconium nitride (see FIG. 1B) has a thickness of about 10 nm. Shape Will be made. When the ZrN cap layer 13 is formed, the magnetron 304 is turned off and nitrogen is not supplied from the nitrogen pipe 307.

Next, the supply of gas from the raw material gas pipe 308 is stopped, and the residual gas in the chamber 301 is sufficiently exhausted from the exhaust port 309.

[0113] Thereafter, nitrogen is supplied into the chamber 301 from the nitrogen gas pipe 307 at a flow rate of about 500 sccm. At the same time, the power of the magnetron 304 is turned on, and a microwave having a power of 700 W and a frequency of 2 GHz to 5 GHz, preferably 2.5 GHz is supplied to the cavity 305 b of the shower head 305.

[0114] Thereby, the force that generates nitrogen plasma in the cavity 305b of the shower head 305. Since the head 305 is at ground potential, the plasma component cannot pass through the hole 305a, and only nitrogen radicals and nitrogen ions are present. Is led to the substrate 1.

Then, a nitrogen annealing process (see FIG. 2 (a)) is performed on the ZrN cap layer 13 under the conditions that the substrate temperature is 200 ° C. and the pressure is 700 Pa, and the ZrN cap layer 13 is nitrided. The substrate temperature in this nitrogen annealing process is not particularly limited, and a substrate temperature of 100 ° C. to 400 ° C. may be adopted as in the second embodiment!

[0117] According to the present embodiment described above, annealing is performed on the ZrN cap layer 13 in an atmosphere containing nitrogen radicals and nitrogen ions, as in the second embodiment. Therefore, similarly to the first embodiment, it is possible to obtain the ZrN cap layer 13 having a high nitrogen concentration and rich in copper noria.

Furthermore, in the present embodiment, as described with reference to FIG. 11, the film formation of the ZrN cap layer 13 and the nitrogen annealing are performed in the same chamber 301, so that the ZrN cap layer 13 is in an oxygen-containing atmosphere. Nitrogen annealing can be performed on the ZrN cap layer 13 while preventing exposure to. Therefore, oxygen can be prevented from being taken into the ZrN cap layer 13 before nitrogen annealing, and the oxygen concentration in the ZrN cap layer 13 can be reduced. As a result, the copper wiring 12a, 12b can be prevented from being oxidized by oxygen contained in the ZrN cap layer 13, and the copper wiring 12a, 12b can be prevented from oxidizing and becoming high resistance. Can do.

Claims

The scope of the claims

[1] forming a first insulating film above the semiconductor substrate;

Forming a first groove or a first hole in the first insulating film;

Forming a first copper wiring by burying copper in the first trench or the first hole; forming a zirconium nitride film as a cap layer on the first insulating film and the first copper wiring; ,

Annealing the cap layer in a nitrogen-containing atmosphere;

A method for manufacturing a semiconductor device, comprising:

[2] In the step of forming the cap layer, TDE AZ (Zr [N (C H)]) gas is used as a raw material gas for zirconium nitride, and without adding ammonia gas to the raw material gas,

2 5 2 4

2. The method of manufacturing a semiconductor device according to claim 1, wherein the cap layer is formed by a CVD method.

[3] In the step of forming the cap layer, TDEAZ (Zr [N (C H)]) gas, carrier gas

2 5 2 4

2. The method of manufacturing a semiconductor device according to claim 1, wherein the cap layer is formed by a CDV method using a mixed gas of the carrier gas with ammonia gas having a flow rate of 1Z40 or less.

4. The method for manufacturing a semiconductor device according to claim 3, wherein nitrogen is used as the carrier gas.

5. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the cap layer, the cap layer is formed to a thickness of 20 nm or less.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the step of annealing the cap layer is performed at a substrate temperature of 200 ° C. or higher and 400 ° C. or lower.

[7] The method for manufacturing a semiconductor device according to [1], wherein the step of annealing the cap layer is performed at a pressure of not less than lkPa and not more than IMPa.

8. The method of manufacturing a semiconductor device according to claim 1, wherein the step of annealing the cap layer is performed by exposing the cap layer to an atmosphere containing nitrogen radicals or nitrogen ions.

[9] The step of annealing the cap layer is performed at a substrate temperature of 100 ° C to 400 ° C. The method for manufacturing a semiconductor device according to claim 8, wherein:

10. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the cap layer and the step of annealing the cap layer are performed in the same chamber.

11. The method of manufacturing a semiconductor device according to claim 1, wherein after the step of forming the cap layer, the step of annealing the cap layer is performed without exposing the cap layer to an oxygen-containing atmosphere. .

[12] forming a second insulating film on the cap layer;

Forming a second groove or a second hole above the first copper wiring in the second insulating film;

Forming a second copper wiring electrically connected to the first copper wiring through the cap layer by embedding copper in the second groove or the second hole. The method of manufacturing a semiconductor device according to claim 1.

[13] a chamber;

A substrate mounting table provided in the chamber and on which a semiconductor substrate is mounted;

A heater provided on the substrate mounting table;

A shower head provided above the substrate mounting table in the chamber, the inside of which is a cavity, and a gas dispersion hole communicating with the cavity is formed;

A magnetron for supplying microwaves to the cavity inside the shower head; a nitrogen gas pipe and a zirconium nitride source gas pipe communicating with the cavity inside the shower head;

A nitrogen gas flow rate controller provided in the nitrogen gas pipe;

A raw material gas flow rate adjusting unit provided in the zirconium nitride raw material gas pipe; and a control unit for controlling the magnetron, the nitrogen gas flow rate adjusting unit, and the raw material gas flow rate adjusting unit,

When the control unit forms a zirconium nitride film in the chamber, the control unit controls the source gas flow rate control unit to introduce the zirconium source gas into the shower head;

When performing nitrogen annealing in the chamber, the nitrogen gas flow rate adjusting unit is A semiconductor manufacturing apparatus, wherein nitrogen gas is controlled to be introduced into the shower head and microwaves are introduced into the cavity of the shower head by controlling the magnetron.

14. The semiconductor manufacturing apparatus according to claim 13, wherein the shower head is set to a ground potential.

[15] TDEAZ (Zr [N (C H)]) gas is fed from the zirconium source gas pipe into the chamber.

The semiconductor manufacturing apparatus according to claim 13, wherein the semiconductor manufacturing apparatus is supplied.