JP5362029B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP5362029B2
JP5362029B2 JP2011540538A JP2011540538A JP5362029B2 JP 5362029 B2 JP5362029 B2 JP 5362029B2 JP 2011540538 A JP2011540538 A JP 2011540538A JP 2011540538 A JP2011540538 A JP 2011540538A JP 5362029 B2 JP5362029 B2 JP 5362029B2
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zirconium
zrbn
boronitride
copper seed
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正信 畠中
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Ulvac Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76823—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. transforming an insulating layer into a conductive layer
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

本発明は、半導体装置の製造方法、特に絶縁膜が有する凹部の内側にめっき法によって銅めっき膜が充填されてなる半導体装置の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a copper plating film is filled inside a recess of an insulating film by a plating method.

半導体装置の配線技術では、配線構造の微細化や多層化が進むにつれて、電流密度の増加に伴うエレクトロマイクレーション（ＥＭ）がより深刻化する。高いＥＭ耐性を有する銅（Ｃｕ）配線の多層配線構造は、こうした問題を回避するために必要とされている。そしてエッチング法を利用した加工方法に代わるダマシン法やデュアルダマシン法は、化学的なエッチングが困難であるＣｕ配線の多層配線技術に不可欠である。   In the wiring technology of a semiconductor device, as the wiring structure is miniaturized and multilayered, electromylation (EM) accompanying an increase in current density becomes more serious. A multilayer wiring structure of copper (Cu) wiring having high EM resistance is required to avoid such problems. A damascene method or a dual damascene method, which is an alternative to a processing method using an etching method, is indispensable for multilayer wiring technology for Cu wiring, which is difficult to chemically etch.

ダマシン法やデュアルダマシン法ではまず、配線形状に合った凹部が予め層間絶縁膜に形成されて、次いでその凹部の内側を埋める配線がＣｕ膜をバルクとしたかたちに形成される。そして層間絶縁膜上に形成されたＣｕ膜等、凹部の外側に形成されたＣｕ膜が化学機械研磨により除去されることにより、Ｃｕ膜を主とした配線構造が形成される。   In the damascene method or the dual damascene method, first, a concave portion matching the wiring shape is formed in the interlayer insulating film in advance, and then a wiring filling the inside of the concave portion is formed in the form of the Cu film as a bulk. Then, a Cu film formed on the outer side of the recess, such as a Cu film formed on the interlayer insulating film, is removed by chemical mechanical polishing, thereby forming a wiring structure mainly including the Cu film.

上述した配線の形成工程ではまず、配線溝や接続孔等の凹部を有する層間絶縁膜に対してスパッタ法等が適用されて、層間絶縁膜中へのＣｕ拡散を抑止するためのバリア膜により、凹部の内側を含む層間絶縁膜の表面全体が被覆される。次いでバリア膜が形成された半導体基板に対してスパッタ法等が適用されて、Ｃｕ膜を成長させるための銅シード膜により、上記バリア膜の表面全体、すなわち凹部の内側全体を含む基板表面が被覆される。そして銅シード膜が形成された半導体基板に対してめっき法が適用されて、凹部の内側を埋めるかたちにＣｕ膜が形成される。こうした各種の成膜工程が実行されることにより、バリア膜、銅シード膜、及びＣｕ層からなるＣｕ配線が形成される。   In the wiring formation process described above, first, a sputtering method or the like is applied to an interlayer insulating film having a recess such as a wiring groove or a connection hole, and a barrier film for suppressing Cu diffusion into the interlayer insulating film, The entire surface of the interlayer insulating film including the inside of the recess is covered. Next, a sputtering method or the like is applied to the semiconductor substrate on which the barrier film is formed, and the copper seed film for growing the Cu film covers the entire surface of the barrier film, that is, the entire substrate surface including the inside of the recess. Is done. Then, a plating method is applied to the semiconductor substrate on which the copper seed film is formed, and a Cu film is formed so as to fill the inside of the recess. By performing these various film forming steps, a Cu wiring composed of a barrier film, a copper seed film, and a Cu layer is formed.

Ｃｕ拡散を抑止するバリア膜の構成材料には、例えばタンタル（Ｔａ）や硼窒化ジルコニウム（ＺｒＢＮ）が知られている。これらのＴａ膜やＺｒＢＮ膜はいずれも優れたバリア性を発現する一方、各々が有する電気伝導性の下地依存性には大きな差異がある。つまり、下地が導電性であるか否かに関わらず導電性を有するＴａ膜に対して、ＺｒＢＮ膜は下地となる膜が導電性であれば導電性を発現し、下地となる膜が絶縁性であれば絶縁性を発現する（例えば、特許文献１）。そのため、こうしたバリア膜を有するＣｕ配線では、バリア膜の構成材料がＴａであるか、あるいはＺｒＢＮであるかに応じて、バリア膜の成膜工程に続く後工程の内容が異なることになる。   For example, tantalum (Ta) or zirconium boronitride (ZrBN) is known as a constituent material of the barrier film that suppresses Cu diffusion. While these Ta films and ZrBN films all exhibit excellent barrier properties, there is a large difference in the grounding dependency of the electrical conductivity of each. In other words, regardless of whether the base is conductive or not, the ZrBN film exhibits conductivity if the base film is conductive, while the base film is insulative. If so, an insulating property is exhibited (for example, Patent Document 1). Therefore, in the Cu wiring having such a barrier film, the contents of the post-process following the barrier film forming process differ depending on whether the constituent material of the barrier film is Ta or ZrBN.

例えばＴａ膜がバリア膜として凹部に適用されるとすれば、凹部の内側全体に加えて層間絶縁膜上にもＴａ膜が堆積することになる。それゆえ、層間の絶縁性が確保されるためには、層間絶縁膜上に堆積したこうしたＴａ膜を化学機械研磨により完全に除去する必要がある。それに対して、ＺｒＢＮ膜がバリア膜として凹部に適用されるとすれば、凹部の底に堆積するＺｒＢＮ膜が導電性を有し、層間絶縁膜上に堆積するＺｒＢＮ膜が絶縁性を有することになる。それゆえ、層間の絶縁性が確保されること、その点においては、層間絶縁膜上に堆積したこうしたＺｒＢＮ膜を完全に除去する必要もない。そこで、Ｃｕ配線に関わるバリア膜については、こうした後工程における利便性を図るために、上述するようなＺｒＢＮ膜が鋭意検討されるに至っている。   For example, if a Ta film is applied to the recess as a barrier film, the Ta film is deposited on the interlayer insulating film in addition to the entire inside of the recess. Therefore, in order to ensure insulation between layers, it is necessary to completely remove such Ta film deposited on the interlayer insulation film by chemical mechanical polishing. On the other hand, if the ZrBN film is applied to the recess as a barrier film, the ZrBN film deposited on the bottom of the recess has conductivity, and the ZrBN film deposited on the interlayer insulating film has insulation. Become. Therefore, it is not necessary to completely remove the ZrBN film deposited on the interlayer insulating film in that the insulating property between the layers is ensured. Therefore, as for the barrier film related to the Cu wiring, the ZrBN film as described above has been intensively studied for the purpose of convenience in such a post-process.

特開２００８−２１１０７９号公報JP 2008-211079 A

上述するようにＺｒＢＮ膜がバリア膜であるとき、このバリア膜と接する下地が導電体であればバリア膜（ＺｒＢＮ膜）も導電体となり、反対に、このバリア膜と接する下地が絶縁体であればバリア膜（ＺｒＢＮ膜）も絶縁体となる。そして、このような電気伝導度の分布を有したＺｒＢＮ膜上にＰＶＤ法を利用した銅シード膜が形成されることになり、さらに、めっき法を利用したＣｕ膜がこの銅シード膜上に形成されることになる。図４（ａ）（ｂ）を参照して、ＺｒＢＮ膜、銅シード膜、及びＣｕ層について説明する。   As described above, when the ZrBN film is a barrier film, if the base in contact with the barrier film is a conductor, the barrier film (ZrBN film) is also a conductor, and conversely, the base in contact with the barrier film is an insulator. For example, the barrier film (ZrBN film) also becomes an insulator. Then, a copper seed film using the PVD method is formed on the ZrBN film having such electric conductivity distribution, and further, a Cu film using the plating method is formed on the copper seed film. Will be. With reference to FIGS. 4A and 4B, the ZrBN film, the copper seed film, and the Cu layer will be described.

図４（ａ）に示されるように、基板に形成された第１層間絶縁膜Ｄ１上には、バリア膜ＢＭとエッチングストッパ膜ＥＳａとに挟まれた第１配線膜Ｍ１が積層されている。この第１配線膜Ｍ１上には、エッチングストッパ膜ＥＳａ，ＥＳｂに挟まれた第２層間絶縁膜Ｄ２が積層されており、また第２層間絶縁膜Ｄ２上には、エッチングストッパ膜ＥＳｂ，ＥＳＣに挟まれた第３層間絶縁膜Ｄ３が積層されている。第２層間絶縁膜Ｄ２及びこれを挟む一対のエッチングストッパ膜ＥＳａ，ＥＳｂには、これらを貫通するかたちに積層方向に延びる接続孔ＣＨが穿設されている。また第３層間絶縁膜Ｄ３及びこれに積層されたエッチングストッパ膜ＥＳＣには、これらを貫通する配線溝ＬＧが接続孔ＣＨから拡開するかたちに穿設されている。そして、これら接続孔ＣＨの内側、配線溝ＬＧの内側、及び配線溝ＬＧの開口外側には、これらの全体を覆うようにＺｒＢＮ膜５１が積層されている。   As shown in FIG. 4A, the first wiring film M1 sandwiched between the barrier film BM and the etching stopper film ESa is stacked on the first interlayer insulating film D1 formed on the substrate. A second interlayer insulating film D2 sandwiched between etching stopper films ESa and ESb is laminated on the first wiring film M1, and the etching stopper films ESb and ESC are stacked on the second interlayer insulating film D2. A sandwiched third interlayer insulating film D3 is stacked. The second interlayer insulating film D2 and the pair of etching stopper films ESa and ESb sandwiching the second interlayer insulating film D2 are provided with connection holes CH extending in the stacking direction so as to penetrate these films. In addition, the third interlayer insulating film D3 and the etching stopper film ESC laminated thereon are provided with a wiring groove LG penetrating therethrough so as to expand from the connection hole CH. A ZrBN film 51 is laminated on the inside of the connection hole CH, the inside of the wiring groove LG, and the outside of the opening of the wiring groove LG so as to cover the whole.

このように構成されたＺｒＢＮ膜５１のうちで第１配線膜Ｍ１の一部でもある接続孔ＣＨの底部に接する部分では、ＺｒＢＮ膜５１が導電体として機能することになる。他方、接続孔ＣＨの周面及び配線溝ＬＧの溝側面に接する部分では、ＺｒＢＮ膜５１が絶縁体として機能することになる。ここで、このような電気伝導度の分布を有したＺｒＢＮ膜に対してＰＶＤ法を利用した銅シード膜が積層されるとなると、絶縁体に対する銅シード膜の密着性が乏しいために、特に成膜速度が遅くなる接続孔ＣＨの底部の周りでは、Ｃｕ粒子が底部側壁を中心に凝集して銅シード膜が粒状の成膜状態となってしまう（図４（ａ）参照）。このような粒状の成膜状態にある銅シード膜に対してめっき法が適用されるものなら、Ｃｕ粒子の間、さらには接続孔ＣＨとＣｕ粒子との間に表面処理用の酸性液が進入してしまい、粒状の成膜状態にある部分でエッチング速度が大きくなってしまう。その結果、図４（ｂ）に示されるように、接続孔ＣＨの底部の周りでは、めっき法によるＣｕ膜５３が成長し難くなるために、Ｃｕ膜５３と第１配線膜Ｍ１との間における接触抵抗が増加して、終には電気的な接続さえも得られ難くなってしまう。配線構造の微細化が進む近年にあっては、銅シード膜の薄膜化も要求されることになるために、上述する問題がさらに顕在化しつつある。   In the ZrBN film 51 configured as described above, the ZrBN film 51 functions as a conductor in a portion in contact with the bottom of the connection hole CH that is also a part of the first wiring film M1. On the other hand, the ZrBN film 51 functions as an insulator in the portion in contact with the peripheral surface of the connection hole CH and the groove side surface of the wiring groove LG. Here, when a copper seed film using the PVD method is laminated on the ZrBN film having such an electric conductivity distribution, the adhesion of the copper seed film to the insulator is particularly poor. Around the bottom of the connection hole CH where the film speed becomes slow, the Cu particles aggregate around the bottom side wall and the copper seed film is in a granular film formation state (see FIG. 4A). If the plating method is applied to the copper seed film in such a granular film formation state, an acidic solution for surface treatment enters between the Cu particles and further between the connection hole CH and the Cu particles. As a result, the etching rate is increased in the granular film-formed state. As a result, as shown in FIG. 4B, the Cu film 53 is not easily grown around the bottom of the connection hole CH, and therefore, between the Cu film 53 and the first wiring film M1. The contact resistance increases, and eventually even an electrical connection becomes difficult to obtain. In recent years, when the miniaturization of the wiring structure is progressing, the copper seed film is also required to be thinned, and thus the above-mentioned problems are becoming more apparent.

本発明は、上記問題に鑑みてなされたものであり、その目的は、絶縁膜が有する凹部の内側にめっき法により充填される銅めっき膜の埋め込み性を向上させた半導体装置の製造方法を提供することである。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device in which the embedding property of a copper plating film filled by a plating method inside a recess of an insulating film is improved. It is to be.

上記課題を解決するための手段及びその作用効果を以下に記載する。
本発明の第１の態様に従う半導体装置の製造方法は、基板上の絶縁膜が有する凹部の内側を硼窒化ジルコニウム膜で被覆する工程と、前記硼窒化ジルコニウム膜の表面をＰＶＤ法により銅シード膜で被覆する工程と、前記銅シード膜で被覆された前記凹部の内側をめっき法により銅めっき膜で充填する工程と、前記硼窒化ジルコニウム膜を前記銅シード膜で被覆する前に、前記硼窒化ジルコニウム膜の表面から、少なくとも窒素を取り除いて当該表面を導体化させる工程とを備え、前記導体化される前記硼窒化ジルコニウム膜の厚さが目標の厚さに到達するまでの目標処理時間を予め取得し、前記窒素を取り除く処理を当該目標時間だけ実行する。 Means for solving the above-described problems and their effects are described below.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a step of coating a concave portion of an insulating film on a substrate with a zirconium boronitride film; and a surface of the zirconium boronitride film by a PVD method. Coating with a copper plating film by plating, and before coating the zirconium boronitride film with the copper seed film, the boron nitride. A step of removing at least nitrogen from the surface of the zirconium film to make the surface a conductor, and the target processing time until the thickness of the zirconium boronitride film to be made conductive reaches a target thickness in advance get, the process of removing the nitrogen to run only the target time.

導電体である銅シード膜の構成材料とこれと異なる絶縁体との間の密着性は、導電体同士の間の密着性あるいは絶縁体同士の間の密着性と比較して一般に低くなる。そのため、ＰＶＤ法による銅シード膜が絶縁体上に形成されるとなれば、こうした銅シード膜が導電体上に形成される場合と比較して、銅シード膜における凝集が容易に発生するようになる。特に絶縁膜が有する凹部の内側にＰＶＤ法により銅シード膜が被覆されるとなれば、絶縁膜が有する凹部が深くなるにつれて、銅シード膜の構成元素が凹部の底に到達し難くなり、そこでの銅シード膜の成長速度が遅くなるため、上述するような凝集がさらに容易に発生するようになる。   The adhesion between the constituent material of the copper seed film, which is a conductor, and a different insulator is generally lower than the adhesion between the conductors or the adhesion between the insulators. Therefore, if a copper seed film by PVD is formed on an insulator, compared with a case where such a copper seed film is formed on a conductor, aggregation in the copper seed film is easily generated. Become. In particular, if the copper seed film is coated inside the concave portion of the insulating film by the PVD method, the constituent elements of the copper seed film are difficult to reach the bottom of the concave portion as the concave portion of the insulating film is deepened. Since the growth rate of the copper seed film becomes slow, the agglomeration as described above occurs more easily.

この点、第１の態様によれば、表面が導体化された硼窒化ジルコニウム膜上に、ＰＶＤ法による銅シード膜が形成されることになる。つまり、絶縁膜が有する凹部の内側においても、硼窒化ジルコニウム膜の表面が導体化されて、こうして導体化された硼窒化ジルコニウム膜上に銅シード膜が形成されることになる。それゆえに、絶縁膜が有する凹部の内側の全体において、バリア膜となる硼窒化ジルコニウム膜と銅シード膜との密着性が向上されることになり、上述した銅シード膜における凝集が凹部の内側の全体で抑制されることになる。   In this regard, according to the first aspect, the copper seed film is formed by the PVD method on the zirconium boronitride film whose surface is made conductive. In other words, the surface of the zirconium boronitride film is made conductive even inside the concave portion of the insulating film, and a copper seed film is formed on the zirconium boronitride film thus made conductive. Therefore, the adhesion between the zirconium boronitride film serving as the barrier film and the copper seed film is improved over the entire inner side of the concave portion of the insulating film, and the aggregation in the copper seed film described above is caused to occur inside the concave portion. It will be suppressed as a whole.

その結果、銅シード膜が形成された後のめっき工程では、銅シード膜における粒状体そのものの成長が抑制されているために、こうした粒状体の間にめっき液が染み込み難くなる。そして、めっき膜の成長速度よりもめっき液によるエッチング速度が大きくなること、それ自体が抑制されることになる。したがって、絶縁膜が有する凹部に対して銅めっき膜の埋め込み性を向上させることが可能になる。そのうえ、硼窒化ジルコニウム膜の表面のみが導体化される構成であれば、こうした表面を研磨して除去することも容易である。そのため、絶縁膜上を被う硼窒化ジルコニウム膜に対し絶縁性が必要となる場合であっても、硼窒化ジルコニウム膜の本来有する電気伝導度の選択性が容易に引き出されることも可能である。
また、上述するような窒素を取り除く処理が過剰に行われるものなら、硼窒化ジルコニウム膜が本来有する電気伝導度の選択性も消失してしまう。反対に、窒素を取り除く処理が不足しようものなら、硼窒化ジルコニウム膜の表面における導体化の不足によって所望する銅めっき膜の埋め込み性が得られ難くなってしまう。この点、窒素を取り除く処理を目標処理時間だけ実行することにより、導体化の過不足が抑制可能となる。 As a result, in the plating step after the copper seed film is formed, the growth of the granular material itself in the copper seed film is suppressed, so that it is difficult for the plating solution to penetrate between the granular materials. And the etching rate by a plating solution becomes larger than the growth rate of a plating film, and itself is suppressed. Therefore, it becomes possible to improve the embedding property of the copper plating film with respect to the concave portion of the insulating film. Moreover, if only the surface of the zirconium boronitride film is made into a conductor, it is easy to polish and remove such a surface. Therefore, even when the insulating property is required for the zirconium boronitride film covering the insulating film, the selectivity of the electrical conductivity inherent in the zirconium boronitride film can be easily derived.
Further, if the treatment for removing nitrogen as described above is performed excessively, the electrical conductivity selectivity inherent in the zirconium boronitride film is lost. On the other hand, if the treatment for removing nitrogen is insufficient, it becomes difficult to obtain the desired embeddability of the copper plating film due to insufficient conductivity on the surface of the zirconium boronitride film. In this regard, by performing the process of removing nitrogen only for the target processing time, it is possible to suppress excessive or insufficient conductorization.

一例では、前記硼窒化ジルコニウム膜の表面に水素ラジカルを照射して当該表面を導体化させる。
硼窒化ジルコニウム膜の表面から窒素を取り除く処理としては、例えば軽元素である窒素のみを硼窒化ジルコニウム膜からスパッタする物理的な表面処理や、硼窒化ジルコニウム膜の表面における窒素のみを熱反応で還元して反応生成物として気化させる化学的な表面処理等が挙げられる。水素ラジカルの照射は、上述するような物理的又は化学的な表面処理の中でも、硼窒化ジルコニウム膜に対する電気的及び熱的なダメージを軽減させることが可能である。In one example, the surface of the zirconium boronitride film is irradiated with hydrogen radicals to make the surface conductive.
As a process for removing nitrogen from the surface of the zirconium boronitride film, for example, a physical surface treatment in which only light element nitrogen is sputtered from the zirconium boronitride film, or only nitrogen on the surface of the zirconium boronitride film is reduced by a thermal reaction. Then, a chemical surface treatment that vaporizes as a reaction product can be used. Irradiation with hydrogen radicals can reduce electrical and thermal damage to the zirconium boronitride film among physical or chemical surface treatments as described above.

一例では、前記絶縁膜上に形成された銅めっき膜、銅シード膜及び前記硼窒化ジルコニウム膜をＣＭＰ法により研削して前記基板上を平坦化する工程を更に備え、前記研削する工程では前記硼窒化ジルコニウム膜を前記目標となる厚さだけ研削する。   In one example, the method further comprises a step of grinding the copper plating film, the copper seed film and the zirconium boronitride film formed on the insulating film by a CMP method to planarize the substrate, and the grinding step includes the step of grinding the boron. The zirconium nitride film is ground by the target thickness.

絶縁膜上に形成された硼窒化ジルコニウム膜からは、導体化された分だけが研削されることにため、平坦化された基板上に硼窒化ジルコニウム膜が残るとしても、こうした硼窒化ジルコニウム膜が絶縁性を有する。よって、硼窒化ジルコニウム膜が本来有する電気伝導度の選択性がより確実に実現可能になる。   Since the zirconium boronitride film formed on the insulating film is ground only for the amount of the conductor, even if the zirconium boronitride film remains on the flattened substrate, the zirconium boronitride film Has insulation. Therefore, the electrical conductivity selectivity inherent in the zirconium boronitride film can be realized more reliably.

一例では、前記絶縁膜が有する凹部が、前記絶縁膜の下地である導電膜に接続された接続孔であり、前記絶縁膜が有する接続孔の内側を前記硼窒化ジルコニウム膜で被覆する前に、前記絶縁膜及び前記導電膜の表面に水素ラジカルを照射する。一例では、前記凹部は、配線溝と接続孔とを含むデュアルダマシンパターンであり、
前記配線溝と接続孔を前記硼窒化ジルコニウム膜で被覆し、水素ラジカルの照射により前記配線溝と接続孔を被覆する前記硼窒化ジルコニウム膜の表面から少なくとも窒素を取り除いて当該表面を導体化させ、その後、前記配線溝と接続孔を被覆する前記硼窒化ジルコニウム膜を前記銅シード膜で被覆する。In one example, the concave portion of the insulating film is a connection hole connected to the conductive film that is a base of the insulating film, and before the inside of the connection hole of the insulating film is covered with the zirconium boronitride film, The surface of the insulating film and the conductive film is irradiated with hydrogen radicals. In one example, the recess is a dual damascene pattern including a wiring groove and a connection hole,
The wiring groove and the connection hole are covered with the zirconium boronitride film, and at least nitrogen is removed from the surface of the zirconium boronitride film covering the wiring groove and the connection hole by irradiation with hydrogen radicals, and the surface is made into a conductor. Thereafter, the zirconium boronitride film covering the wiring groove and the connection hole is covered with the copper seed film.

硼窒化ジルコニウム膜の下地である絶縁膜及び導電膜の表面に水素ラジカルによる還元処理が施されるため、これら絶縁膜及び導電膜の表面に有機物等の絶縁性の異物が存在する場合であっても、これらの異物を取り除くことが可能となる。その結果、硼窒化ジルコニウム膜と絶縁膜との間の密着性が向上可能になる。さらに、硼窒化ジルコニウム膜と導電膜との間の電気的な接続がより確実に得られることになるため、絶縁膜が有する接続孔に充填される銅めっき膜と導電膜との間の電気的な接続がより確実に得られることになる。   The surface of the insulating film and the conductive film, which are the bases of the zirconium boronitride film, is subjected to a reduction treatment with hydrogen radicals, so that there are insulating foreign substances such as organic substances on the surfaces of the insulating film and the conductive film. However, these foreign substances can be removed. As a result, the adhesion between the zirconium boronitride film and the insulating film can be improved. Further, since the electrical connection between the zirconium boronitride film and the conductive film can be obtained more reliably, the electrical connection between the copper plating film filled in the connection hole of the insulating film and the conductive film is achieved. Connection can be obtained more reliably.

本実施形態にかかる半導体装置の製造方法を構成するＣｕ配線の形成方法を示すフローチャート。6 is a flowchart showing a method for forming a Cu wiring constituting the method for manufacturing a semiconductor device according to the embodiment. （ａ）は絶縁膜に形成されたデュアルダマシンパターンの平面図、（ｂ）は（ａ）のＡ−Ａ線断面図。(A) is a top view of the dual damascene pattern formed in the insulating film, (b) is the sectional view on the AA line of (a). （ａ）（ｂ）（ｃ）はＣｕ配線の形成方法における各工程を示す工程図。(A), (b), (c) is process drawing which shows each process in the formation method of Cu wiring. （ａ）（ｂ）は従来例のＣｕ配線の形成方法における各工程を示す工程図。(A) (b) is process drawing which shows each process in the formation method of Cu wiring of a prior art example.

以下、本発明を具体化した一実施形態について図面を参照して説明する。図１に示されるように、半導体装置の製造方法を構成するＣｕ配線の形成方法では、基板上の絶縁膜に凹部としてのデュアルダマシンパターンを形成する工程（ステップＳ１）と、その凹部に前処理を施す工程（ステップＳ２）と、同凹部の内側を硼窒化ジルコニウム膜（ＺｒＢＮ膜）で被覆する工程（ステップＳ３）とが、この順に実行される。続いて、ＺｒＢＮ膜に後処理を施す工程（ステップＳ４）と、ＺｒＢＮ膜の表面をＰＶＤ法により銅シード膜で被覆する工程（ステップＳ５）と、銅シード膜で被覆された凹部の内側をめっき法により銅めっき膜で充填する工程（ステップＳ６）と、絶縁膜上を平坦化するＣＭＰ工程（ステップＳ７）とが順に実行される。   Hereinafter, an embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, in a Cu wiring forming method constituting a semiconductor device manufacturing method, a step of forming a dual damascene pattern as a recess in an insulating film on a substrate (step S1), and pre-processing in the recess The step of applying (Step S2) and the step of covering the inside of the recess with a zirconium boronitride film (ZrBN film) (Step S3) are performed in this order. Subsequently, a step of post-processing the ZrBN film (step S4), a step of coating the surface of the ZrBN film with a copper seed film by the PVD method (step S5), and plating the inside of the concave portion covered with the copper seed film A step of filling with a copper plating film by a method (step S6) and a CMP step of planarizing the insulating film (step S7) are sequentially performed.

上記凹部の形成工程に先立ち、基板上には、図２（ａ）（ｂ）に示されるように、第１層間絶縁膜１１が形成されている。この第１層間絶縁膜１１上には、バリア膜１２とエッチングストッパ膜１３ａとに挟まれた配線膜１４が積層されている。この配線膜１４上には、エッチングストッパ膜１３ａ，１３ｂに挟まれた第２層間絶縁膜１５が積層されており、また第２層間絶縁膜１５上には、エッチングストッパ膜１３ｂ，１３ｃに挟まれた第３層間絶縁膜１６が積層されている。   Prior to the step of forming the recess, a first interlayer insulating film 11 is formed on the substrate as shown in FIGS. On the first interlayer insulating film 11, a wiring film 14 sandwiched between a barrier film 12 and an etching stopper film 13a is laminated. On the wiring film 14, a second interlayer insulating film 15 sandwiched between etching stopper films 13a and 13b is laminated. On the second interlayer insulating film 15, sandwiched between etching stopper films 13b and 13c. A third interlayer insulating film 16 is laminated.

なお、各層間絶縁膜１１，１５，１６は、例えばシリコン酸化物や炭素含有シリコン酸化物等から構成される絶縁膜であって、化学的気相成長法（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ法：ＣＶＤ法）やスピンコート法等の成膜方法により形成される。配線膜１４は、例えばアルミニウムやチタン、銅やタンタル等から構成される多層の導電膜であって、物理的気相成長法（Ｐｈｙｓｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ法：ＰＶＤ法）やＣＶＤ法等の成膜方法により形成される。第１層間絶縁膜１１と配線膜１４とに挟まれるバリア膜１２は、配線膜１４の構成材料が層間絶縁膜に拡散することを抑制する機能を有して金属窒化物やシリコン炭化物等から構成される薄膜であって、ＣＶＤ法やＰＶＤ法、スピンコート法等の成膜方法により形成される。各エッチングストッパ膜１３ａ，１３ｂ，１３ｃは、層間絶縁膜に対する適正なエッチング選択性と、配線膜１４の構成材料が層間絶縁膜に拡散することを抑える機能とを有してシリコン炭化物やシリコン酸窒化物等から構成されており、ＣＶＤ法やスピンコート法等の成膜方法により形成される。   Each of the interlayer insulating films 11, 15, and 16 is an insulating film made of, for example, silicon oxide, carbon-containing silicon oxide, or the like, and may be a chemical vapor deposition method (Chemical Vapor Deposition method: CVD method) or the like. It is formed by a film forming method such as a spin coating method. The wiring film 14 is a multi-layered conductive film made of, for example, aluminum, titanium, copper, tantalum or the like, and is formed by a film forming method such as a physical vapor deposition method (PVD method) or a CVD method. It is formed. The barrier film 12 sandwiched between the first interlayer insulating film 11 and the wiring film 14 has a function of preventing the constituent material of the wiring film 14 from diffusing into the interlayer insulating film, and is made of metal nitride, silicon carbide, or the like. The thin film is formed by a film forming method such as a CVD method, a PVD method, or a spin coating method. Each of the etching stopper films 13a, 13b, and 13c has an appropriate etching selectivity with respect to the interlayer insulating film and a function of suppressing the constituent material of the wiring film 14 from diffusing into the interlayer insulating film. The film is formed by a film forming method such as a CVD method or a spin coating method.

上記凹部の形成工程（ステップＳ１）では、図２に示されるように、第３層間絶縁膜１６及びこれに積層されたエッチングストッパ膜１３ｃに、これらを貫通して接続孔１７から拡開するかたの配線溝１８がドライエッチング法により形成される。また第２層間絶縁膜１５及びこれを挟む一対のエッチングストッパ膜１３ａ，１３ｂに、これらを貫通するかたちの接続孔１７がドライエッチング法により形成される。そして、配線膜１４の一部が外側に露出されるかたちに、これら接続孔（ビア）１７及び配線溝１８から構成される凹部２０が形成される。   In the step of forming the recess (step S1), as shown in FIG. 2, the third interlayer insulating film 16 and the etching stopper film 13c laminated thereon are penetrated and expanded from the connection hole 17 Another wiring groove 18 is formed by a dry etching method. A connection hole 17 is formed in the second interlayer insulating film 15 and the pair of etching stopper films 13a and 13b sandwiching the second interlayer insulating film 15 by a dry etching method. Then, a recess 20 composed of the connection hole (via) 17 and the wiring groove 18 is formed in a form in which a part of the wiring film 14 is exposed to the outside.

なお、上述のようにして凹部２０を形成する過程では、炭素を含有する有機系のフォトレジストが用いられるために、凹部２０の内部やエッチングストッパ膜１３ｃ上に、こうしたフォトレジストの残渣が異物として付着し易くなる。また、炭素を含有する構成材料でエッチングストッパ膜１３ａ，１３ｂ，１３ｃが形成される場合にも、こうした炭素を含有する異物が凹部２０の内部に付着し易くなる。   In the process of forming the recess 20 as described above, since an organic photoresist containing carbon is used, the residue of the photoresist as a foreign matter is formed inside the recess 20 or on the etching stopper film 13c. It becomes easy to adhere. Further, even when the etching stopper films 13 a, 13 b, and 13 c are formed of a constituent material containing carbon, such foreign matters containing carbon are likely to adhere to the inside of the recess 20.

上記凹部２０に対して前処理を施す工程（ステップＳ２）では、同凹部２０を含む基板表面の全体に水素ラジカルが照射される。このように基板表面の全体に水素ラジカルが照射されると、水素ラジカルによる炭素の還元処理が凹部２０を含む基板表面の全体で進行することになる。その結果、凹部２０の底を構成する配線膜１４の一部、凹部２０の側面を構成する第２層間絶縁膜１５や第３層間絶縁膜１６の一部、さらにはエッチングストッパ膜１３ｂ，１３ｃ等、これらの表面に付着した有機系の異物が、同表面から取り除かれることとなる。   In the step of performing the pretreatment on the recess 20 (step S2), the entire surface of the substrate including the recess 20 is irradiated with hydrogen radicals. Thus, when hydrogen radicals are irradiated to the whole substrate surface, carbon reduction treatment by hydrogen radicals proceeds on the whole substrate surface including the recess 20. As a result, a part of the wiring film 14 constituting the bottom of the recess 20, a part of the second interlayer insulating film 15 and the third interlayer insulating film 16 constituting the side surface of the recess 20, and etching stopper films 13 b and 13 c, etc. The organic foreign matters adhering to these surfaces are removed from the surfaces.

このような前処理の態様の一例としては、例えばマイクロ波を受ける水素ガスが水素ラジカルを生成して、基板が収容される真空チャンバー内にこの水素ラジカルが供給される、そのような態様がある。このようにマイクロ波と水素ガスとを用いた前処理における処理条件の一例を以下に示す。
・基板温度：１００℃〜２５０℃
・水素ガス流量：２００ｓｃｃｍ
・アルゴンガス流量：３０ｓｃｃｍ
・処理圧力：５０〜５００Ｐａ
・マイクロ波出力：１００Ｗ
上記凹部２０をＺｒＢＮ膜で被覆する工程（ステップＳ３）では、ＣＶＤ法やＰＶＤ法等の成膜方法によって、凹部２０を含む基板表面の全体にＺｒＢＮ膜２１が形成される。このようなＺｒＢＮ膜２１が形成されると、ＺｒＢＮ膜２１の下地が導電体であれば当該ＺｒＢＮ膜２１が導電性を発現し、ＺｒＢＮ膜２１の下地が絶縁体であれば当該ＺｒＢＮ膜２１が絶縁性を発現する。例えば凹部２０の底を構成する配線膜１４と接するＺｒＢＮ膜２１の部分は、５〜８μΩ・ｃｍの比抵抗値を有した導電体となり、凹部２０の内側面を構成する第２層間絶縁膜１５や第３層間絶縁膜１６と接するＺｒＢＮ膜２１の部分は、１０２Ω・ｃｍ以上の比抵抗値を有した絶縁体となる。As an example of such a pretreatment mode, for example, there is such a mode in which hydrogen gas that receives microwaves generates hydrogen radicals, and the hydrogen radicals are supplied into a vacuum chamber in which the substrate is accommodated. . An example of processing conditions in the pretreatment using microwaves and hydrogen gas in this way is shown below.
-Substrate temperature: 100 ° C to 250 ° C
・ Hydrogen gas flow rate: 200sccm
Argon gas flow rate: 30sccm
・ Processing pressure: 50-500Pa
・ Microwave output: 100W
In the step of covering the concave portion 20 with the ZrBN film (step S3), the ZrBN film 21 is formed on the entire substrate surface including the concave portion 20 by a film forming method such as a CVD method or a PVD method. When such a ZrBN film 21 is formed, if the base of the ZrBN film 21 is a conductor, the ZrBN film 21 exhibits conductivity, and if the base of the ZrBN film 21 is an insulator, the ZrBN film 21 is Insulates. For example, the portion of the ZrBN film 21 in contact with the wiring film 14 that forms the bottom of the recess 20 becomes a conductor having a specific resistance value of 5 to 8 μΩ · cm, and the second interlayer insulating film 15 that forms the inner surface of the recess 20. The portion of the ZrBN film 21 in contact with the third interlayer insulating film 16 becomes an insulator having a specific resistance value of 10 2 Ω · cm or more.

このようなＺｒＢＮ膜２１の成膜態様の一例としては、例えばマイクロ波を受ける窒素ガスが窒素ラジカルを生成して、基板が収容される真空チャンバー内にこの窒素ラジカルとテトラヒドロボレートジルコニウム（Ｚｒ（ＢＨ４）４）とが供給される、そのような態様が挙げられる。このように窒素ラジカルとテトラヒドロボレートジルコニウムとを用いた成膜条件の一例を以下に示す。
・基板温度：２２０℃
・Ｚｒ（ＢＨ４）４：５５ｓｃｃｍ
・窒素ガス流量（ＭＦＣ２）：５０ｓｃｃｍ
・マイクロ波出力：１００Ｗ
・処理圧力：４００Ｐａ
なおＺｒＢＮ膜２１の成膜態様の一例には、例えばジルコニウム（Ｚｒ）を主成分とするターゲットと、窒化硼素（ＢＮ）を主成分とするターゲットとが基板上で同時にスパッタされる、そのような態様も挙げられる。As an example of such a film formation mode of the ZrBN film 21, for example, nitrogen gas receiving microwaves generates nitrogen radicals, and the nitrogen radicals and tetrahydroborate zirconium (Zr (BH 4 ) and 4 ) are provided. An example of film forming conditions using nitrogen radicals and tetrahydroborate zirconium as described above is shown below.
-Substrate temperature: 220 ° C
・ Zr (BH 4 ) 4 : 55 sccm
・ Nitrogen gas flow rate (MFC2): 50 sccm
・ Microwave output: 100W
・ Processing pressure: 400Pa
As an example of the film formation mode of the ZrBN film 21, for example, a target mainly composed of zirconium (Zr) and a target mainly composed of boron nitride (BN) are simultaneously sputtered on the substrate. An embodiment is also mentioned.

このようにしてＺｒＢＮ膜が形成されるとき、ＺｒＢＮ膜の下地である層間絶縁膜及び配線膜１４の表面では、先行する前処理によって有機系の異物が取り除かれている。それゆえに、こうした異物が下地に存在する場合と比較して、ＺｒＢＮ膜２１と各層間絶縁膜との間の密着性、及びＺｒＢＮ膜２１とエッチングストッパ膜との間の密着性が向上可能になる。   When the ZrBN film is formed in this manner, organic foreign matters are removed from the surface of the interlayer insulating film and the wiring film 14 which are the bases of the ZrBN film by the preceding pretreatment. Therefore, the adhesion between the ZrBN film 21 and each interlayer insulating film and the adhesion between the ZrBN film 21 and the etching stopper film can be improved as compared with the case where such a foreign substance exists in the base. .

上記ＺｒＢＮ膜２１に後処理を施す工程では、同ＺｒＢＮ膜２１を含む基板表面の全体に水素ラジカルが照射される。図３（ａ）は、この後処理後におけるＺｒＢＮ膜の断面構造を示す。図３（ａ）に示されるように、ＺｒＢＮ膜の表面の全体に水素ラジカルが照射されると、水素ラジカルによる窒素の還元処理がＺｒＢＮ膜２１の表面２１ａの全体で進行することになる。そして、ＺｒＢＮ膜２１の表面２１ａから少なくとも窒素がアンモニア等の揮発性ガスとして取り除かれて、当該表面２１ａが金属Ｚｒあるいは導電性の硼化ジルコニウム（ＺｒＢ）になる。その結果、凹部２０の底を構成する配線膜１４と接するＺｒＢＮ膜２１の部分は、その導電性を維持することとなり、凹部２０の内側面を構成する第２層間絶縁膜１５や第３層間絶縁膜１６と接するＺｒＢＮ膜２１の部分は、その表面２１ａ（図３（ａ）においてドットを付した領域）が絶縁性から導電性へと改質される。   In the step of post-processing the ZrBN film 21, the entire surface of the substrate including the ZrBN film 21 is irradiated with hydrogen radicals. FIG. 3A shows the cross-sectional structure of the ZrBN film after this post-processing. As shown in FIG. 3A, when hydrogen radicals are irradiated on the entire surface of the ZrBN film, the reduction treatment of nitrogen by the hydrogen radicals proceeds on the entire surface 21a of the ZrBN film 21. Then, at least nitrogen is removed from the surface 21a of the ZrBN film 21 as a volatile gas such as ammonia, and the surface 21a becomes metal Zr or conductive zirconium boride (ZrB). As a result, the portion of the ZrBN film 21 in contact with the wiring film 14 that forms the bottom of the recess 20 maintains its conductivity, and the second interlayer insulating film 15 and the third interlayer insulating film that configure the inner surface of the recess 20 are maintained. The portion of the ZrBN film 21 in contact with the film 16 has its surface 21a (the region marked with dots in FIG. 3A) modified from insulating to conductive.

なお、こうした後処理の処理時間としては、上述のようにして導体化される厚さが目標となる厚さ（目標厚さＴ１）に到達するまでの目標処理時間を予め取得して、当該目標処理時間だけ実行される構成が好ましい。窒素を取り除く処理が過剰に行われるものなら、ＺｒＢＮ膜２１が本来有する電気伝導度の選択性も消失してしまう。反対に、窒素を取り除く処理が不足しようものなら、ＺｒＢＮ膜２１の表面２１ａにおける導体化の不足によって所望する銅めっき膜の埋め込み性が得られ難くなってしまう。この点、目標処理時間だけ後処理を実施する構成であれば、導体化されるＺｒＢＮ膜の厚さが目標とする厚さで実現可能となり、上述するような導体化の過不足が抑制可能となる。   In addition, as the processing time of such post-processing, a target processing time until the thickness of the conductor as described above reaches a target thickness (target thickness T1) is acquired in advance, and the target A configuration that is executed only for the processing time is preferable. If the process of removing nitrogen is performed excessively, the selectivity of the electrical conductivity inherent in the ZrBN film 21 is lost. On the other hand, if the treatment for removing nitrogen is insufficient, it becomes difficult to obtain the desired embeddability of the copper plating film due to insufficient conduction on the surface 21a of the ZrBN film 21. In this regard, if the post-processing is performed only for the target processing time, the thickness of the ZrBN film to be made conductive can be realized with the target thickness, and the above-described excess and shortage of the conductor can be suppressed. Become.

また、ＺｒＢＮ膜２１の表面２１ａが導電性を有するためには、最低一原子層のＺｒＢＮがＺｒあるいは導電性のＺｒＢに改質される必要がある。このように導体化されるＺｒＢＮ膜２１の厚さは、凹部２０の構造や上記後処理の条件に応じても異なる場合がある。それだけに、上述する目標処理時間も、凹部２０における何処の部分で目標厚さＴ１を実現するかによって異なる場合がある。このような場合にあっては、凹部２０の底の周辺における部位で目標厚さＴ１が実現されるように、上記目標処理時間が設定される構成が好ましい。こうした構成であれば、少なくとも凹部２０の底の周辺においてＺｒＢＮ膜２１の導体化が担保されることになる。   Further, in order for the surface 21a of the ZrBN film 21 to be conductive, it is necessary to modify ZrBN of at least one atomic layer to Zr or conductive ZrB. The thickness of the ZrBN film 21 thus made conductive may differ depending on the structure of the recess 20 and the conditions of the post-treatment. For that reason, the target processing time described above may vary depending on where in the recess 20 the target thickness T1 is realized. In such a case, a configuration in which the target processing time is set so that the target thickness T1 is realized at a portion around the bottom of the recess 20 is preferable. With such a configuration, the ZrBN film 21 is ensured to be conductive at least around the bottom of the recess 20.

このような後処理の態様の一例としては、上述した前処理の態様と同じく、例えばマイクロ波を受ける水素ガスが水素ラジカルを生成して、基板が収容される真空チャンバー内にこの水素ラジカルが供給される、そのような態様がある。このようにマイクロ波と水素ガスとを用いた前処理における処理条件の一例を以下に示す。
・基板温度：１００℃〜２５０℃
・水素ガス流量：２００ｓｃｃｍ
・アルゴンガス流量：３０ｓｃｃｍ
・処理圧力：５０〜５００Ｐａ
・マイクロ波出力：１００Ｗ
凹部２０の内側を銅シード膜２２で被覆する工程（ステップＳ５）では、図３（ｂ）に示されるように、上記ＺｒＢＮ膜２１の表面２１ａの全体に、銅めっき膜２３の給電膜としての機能と、ＺｒＢＮ膜２１と銅めっき膜２３との間の密着性を向上させる機能とを有する銅シード１８が、銅ターゲットを用いるＰＶＤ法により形成される。導電体である銅シード膜２２の構成材料とこれと異なる絶縁体との間の密着性は、導電体同士の間の密着性あるいは絶縁体同士の間の密着性と比較して一般に低くなる。そのため、ＰＶＤ法による銅シード膜２２が絶縁体上に形成されるとなれば、こうした銅シード膜２２が導電体上に形成される場合と比較して、銅シード膜２２の構成材料が粒状に凝集し易くなる。特に絶縁性を有する凹部２０の底周辺にＰＶＤ法により銅シード膜２２が被覆されるとなれば、凹部２０が深くなるにつれて銅シード膜２２の構成元素が凹部２０の底に到達し難くなり、そこでの銅シード膜２２の成長速度が遅くなるため、上述するような凝集がさらに容易に発生するようになる。As an example of such a post-processing mode, as in the above-described pre-processing mode, for example, hydrogen gas that receives microwaves generates hydrogen radicals, and the hydrogen radicals are supplied into a vacuum chamber in which the substrate is accommodated. There are such aspects. An example of processing conditions in the pretreatment using microwaves and hydrogen gas in this way is shown below.
-Substrate temperature: 100 ° C to 250 ° C
・ Hydrogen gas flow rate: 200sccm
Argon gas flow rate: 30sccm
・ Processing pressure: 50-500Pa
・ Microwave output: 100W
In the step of covering the inside of the recess 20 with the copper seed film 22 (step S5), as shown in FIG. 3B, the entire surface 21a of the ZrBN film 21 is applied as a power feeding film of the copper plating film 23. A copper seed 18 having a function and a function of improving the adhesion between the ZrBN film 21 and the copper plating film 23 is formed by a PVD method using a copper target. The adhesion between the constituent material of the copper seed film 22 which is a conductor and an insulator different from this is generally lower than the adhesion between conductors or the adhesion between insulators. Therefore, if the copper seed film 22 is formed on the insulator by the PVD method, the constituent material of the copper seed film 22 is granular compared to the case where the copper seed film 22 is formed on the conductor. Aggregates easily. In particular, if the copper seed film 22 is coated around the bottom of the insulating recess 20 by the PVD method, it becomes difficult for the constituent elements of the copper seed film 22 to reach the bottom of the recess 20 as the recess 20 becomes deeper. Since the growth rate of the copper seed film 22 is slowed down there, the agglomeration as described above occurs more easily.

一方、上述のような構成であれば、銅シード膜２２が形成されるときに、銅シード膜２２の下地であるＺｒＢＮ膜２１の表面２１ａ、特に凹部２０の底周辺には、先行する上記後処理によって導電性が付与されている。それゆえに、上記後処理が施されていないＺｒＢＮ膜２１上に銅シード膜２２を形成する場合と比較して、すなわち絶縁性を有するＺｒＢＮ膜２１上に銅シード膜２２を形成する場合と比較して、ＺｒＢＮ膜２１と銅シード膜２２との間の密着性が向上可能になる。よって、凹部２０の側壁であれ、成膜速度が遅くなる凹部２０の底周辺であれ、銅シード膜２２における凝集が抑制可能となる。   On the other hand, with the configuration as described above, when the copper seed film 22 is formed, the surface 21 a of the ZrBN film 21 that is the base of the copper seed film 22, particularly the bottom periphery of the recess 20, is preceded by the preceding Conductivity is imparted by the treatment. Therefore, compared with the case where the copper seed film 22 is formed on the ZrBN film 21 not subjected to the post-treatment, that is, compared with the case where the copper seed film 22 is formed on the insulating ZrBN film 21. Thus, the adhesion between the ZrBN film 21 and the copper seed film 22 can be improved. Therefore, it is possible to suppress aggregation in the copper seed film 22 regardless of the side wall of the recess 20 or the vicinity of the bottom of the recess 20 where the deposition rate is slow.

凹部２０の内側をめっき法により銅めっき膜２３で充填する工程（ステップＳ６）では、図３（ｃ）に示されるように、上記銅シード膜２２の表面の全体に、凹部２０の内側を埋めるかたちの銅めっき膜２３が電解めっき法により形成される。この際、凝集状態にある銅シード膜２２に対して電解めっき法が適用されるものなら、Ｃｕ粒子の間に酸性のめっき液が染み込むことになり、銅めっき膜２３の成長速度よりもめっき液によるエッチング速度が大きくなってしまう。その結果、めっき法による銅めっき膜２３が成長し難くなってしまう。   In the step of filling the inside of the recess 20 with the copper plating film 23 by the plating method (step S6), as shown in FIG. 3C, the entire surface of the copper seed film 22 is filled with the inside of the recess 20. A copper plating film 23 is formed by electrolytic plating. At this time, if the electroplating method is applied to the copper seed film 22 in an agglomerated state, an acidic plating solution permeates between the Cu particles, and the plating solution is more than the growth rate of the copper plating film 23. The etching rate due to this increases. As a result, the copper plating film 23 by the plating method is difficult to grow.

この点、上記銅シード膜２２が形成された後のめっき工程では、銅シード膜２２における粒状体そのものの成長が抑制されているために、こうした粒状体の間にめっき液が染み込むこともない。それゆえ、銅めっき膜の成長速度よりもめっき液によるエッチング速度が大きくなること、それ自体が抑制されることになる。したがって、図３（ｃ）に示されるように、凹部２０の全体にわたり、銅めっき膜２３の埋め込み性を向上させることが可能になる。   In this regard, in the plating step after the copper seed film 22 is formed, the growth of the granular body itself in the copper seed film 22 is suppressed, so that the plating solution does not penetrate between the granular bodies. Therefore, the etching rate by the plating solution becomes higher than the growth rate of the copper plating film, and the per se is suppressed. Therefore, as shown in FIG. 3C, it is possible to improve the embedding property of the copper plating film 23 over the entire recess 20.

エッチングストッパ膜１３ｃ上に積層された各膜を研削する工程（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｋｉｓｈｉｎｇ工程：ＣＭＰ工程（ステップＳ７））では、例えばアルミナを主材とするスラリーを用いたＣＭＰ法により、エッチングストッパ膜１３ｃ上に堆積した余剰の膜である、銅めっき膜２３、銅シード膜２２、及びＺｒＢＮ膜２１が、この順に研削される。この際、第３層間絶縁膜１６上に他の配線構造が形成される場合、層間の絶縁性が確保されるためには、第３層間絶縁膜１６上に堆積した導電体を完全に除去する必要がある。   In the step of grinding each film laminated on the etching stopper film 13c (Chemical Mechanical Polishing step: CMP step (step S7)), for example, the CMP method using a slurry containing alumina as a main material is performed on the etching stopper film 13c. The copper plating film 23, the copper seed film 22, and the ZrBN film 21, which are surplus films deposited on, are ground in this order. At this time, when another wiring structure is formed on the third interlayer insulating film 16, the conductor deposited on the third interlayer insulating film 16 is completely removed in order to ensure interlayer insulation. There is a need.

上述するようにＺｒＢＮ膜２１の表面２１ａのみが導体化される構成であれば、ＺｒＢＮ膜２１の全てを除去する構成と比較して、こうした表面２１ａを研磨して除去することも容易である。そのため、エッチングストッパ膜１３ｃ上のＺｒＢＮ膜２１に対し絶縁性が必要となる場合であっても、ＺｒＢＮ膜２１の本来有する電気伝導度の選択性が同ＺｒＢＮ膜２１の下層部２１ｂで容易に引き出し可能となる。そのうえ、導体化されるＺｒＢＮ膜２１の厚さが目標厚さＴ１で規格化されるとなれば、ＣＭＰ法により研削する膜厚も、銅めっき膜２３の膜厚と銅シード膜２２の膜厚とを積算した膜厚Ｔ２と、これに目標厚さＴ１とを加えた膜厚として規格化されることになる。そのため、ＣＭＰ法により研削する膜厚の過不足が抑えられるために、上記電気伝導度の選択性がより確実に実現可能となる。   As described above, if only the surface 21a of the ZrBN film 21 is made to be a conductor, it is easier to polish and remove the surface 21a as compared with a structure in which the entire ZrBN film 21 is removed. Therefore, even when the ZrBN film 21 on the etching stopper film 13c needs to be insulated, the selectivity of the electrical conductivity inherent in the ZrBN film 21 can be easily extracted by the lower layer portion 21b of the ZrBN film 21. It becomes possible. In addition, if the thickness of the ZrBN film 21 to be conductorized is normalized by the target thickness T1, the film thickness ground by the CMP method is the same as the film thickness of the copper plating film 23 and the film thickness of the copper seed film 22. Is normalized as a film thickness obtained by adding the target thickness T1 to the film thickness T2. Therefore, since the excess or deficiency of the film thickness ground by the CMP method can be suppressed, the selectivity of the electric conductivity can be realized more reliably.

以上説明したように、上記実施形態によれば以下の効果を得ることができる。
（１）表面が導体化されたＺｒＢＮ膜２１上に、ＰＶＤ法による銅シード膜２２が形成されることから、凹部２０の底周辺においても、ＺｒＢＮ膜２１の表面が導体化されて、こうして導体化されたＺｒＢＮ膜２１上に銅シード膜２２が形成されることになる。それゆえに、凹部２０の内側の全体において、ＺｒＢＮ膜２１と銅シード膜２２との密着性が向上されることになり、銅シード膜２２における凝集が凹部２０の内側の全体で抑制されることになる。As described above, according to the above embodiment, the following effects can be obtained.
(1) Since the copper seed film 22 is formed by the PVD method on the ZrBN film 21 whose surface is made conductive, the surface of the ZrBN film 21 is made conductive even in the vicinity of the bottom of the recess 20, thus A copper seed film 22 is formed on the converted ZrBN film 21. Therefore, the adhesion between the ZrBN film 21 and the copper seed film 22 is improved in the entire inside of the recess 20, and aggregation in the copper seed film 22 is suppressed in the entire inside of the recess 20. Become.

その結果、銅シード膜２２が形成された後のめっき工程では、銅シード膜２２における粒状体そのものの成長が抑制されているために、こうした粒状体の間にめっき液が染み込み難くなる。そして、銅めっき膜２３の成長速度よりもめっき液によるエッチング速度が大きくなること、それ自体が抑制されることになる。したがって、凹部２０の全体に対して銅めっき膜２３の埋め込み性を向上させることが可能になる。   As a result, in the plating step after the copper seed film 22 is formed, the growth of the granular material itself in the copper seed film 22 is suppressed, so that it is difficult for the plating solution to penetrate between the granular materials. And the etching rate by a plating solution becomes larger than the growth rate of the copper plating film 23, and itself is suppressed. Therefore, it is possible to improve the embedding property of the copper plating film 23 with respect to the entire recess 20.

（２）そのうえ、銅シード膜２２とＺｒＢＮ膜２１との間の密着性がこれらの全体で向上されることから、めっき液の染み込みを抑えるために銅シード膜２２の膜厚を不要に厚くすることも抑えることが可能となり、ひいては銅シード膜２２の膜厚自体を薄くすることも可能となる。   (2) In addition, since the adhesion between the copper seed film 22 and the ZrBN film 21 is improved as a whole, the film thickness of the copper seed film 22 is increased unnecessarily in order to suppress the penetration of the plating solution. This also makes it possible to reduce the thickness of the copper seed film 22 itself.

（３）水素ラジカルの照射によりＺｒＢＮ膜２１の表面を導体化させるために、このような導体化が実現可能な様々な物理的又は化学的な表面処理の中でも、ＺｒＢＮ膜２１に対する電気的及び熱的なダメージを軽減させることが可能になる。   (3) In order to make the surface of the ZrBN film 21 into a conductor by irradiation with hydrogen radicals, among various physical or chemical surface treatments capable of realizing such a conductor, the electrical and thermal properties of the ZrBN film 21 It becomes possible to reduce the damage.

（４）ＺｒＢＮ膜２１の表面から窒素を取り除く処理が目標処理時間だけ実行されるだけに、導体化される厚さが目標厚さＴ１で実現されることとなり、ＺｒＢＮ膜２１における導体化の過不足が抑制可能となる。   (4) Since the process of removing nitrogen from the surface of the ZrBN film 21 is executed only for the target processing time, the thickness to be made into a conductor is realized at the target thickness T1, and the ZrBN film 21 is excessively made conductive. The shortage can be suppressed.

（５）エッチングストッパ膜１３ｃ上に形成された余剰のＺｒＢＮ膜２１からは、導体化された分だけが研削されることになる。そのため、平坦化された基板上にＺｒＢＮ膜２１が残るとしても、こうしたＺｒＢＮ膜２１が絶縁性を有することになるため、ＺｒＢＮ膜２１が本来有する電気伝導度の選択性がより確実に実現可能になる。   (5) From the surplus ZrBN film 21 formed on the etching stopper film 13c, only the portion made conductive is ground. Therefore, even if the ZrBN film 21 remains on the planarized substrate, since the ZrBN film 21 has an insulating property, the selectivity of the electrical conductivity inherent in the ZrBN film 21 can be more reliably realized. Become.

（６）ＺｒＢＮ膜２１の下地の表面に水素ラジカルによる還元処理が施されるため、当該下地の表面に有機物等の絶縁性の異物が存在する場合であっても、これらの異物を取り除くことが可能となる。その結果、ＺｒＢＮ膜２１とそれの下地との間の密着性が向上可能になる。   (6) Since the surface of the underlayer of the ZrBN film 21 is subjected to reduction treatment with hydrogen radicals, even if there are insulating foreign substances such as organic substances on the underlayer surface, these foreign substances can be removed. It becomes possible. As a result, the adhesion between the ZrBN film 21 and the underlying layer can be improved.

（７）ＺｒＢＮ膜２１の前処理とＺｒＢＮ膜２１の後処理とが、共通する水素ラジカルの照射処理であることから、これら前処理及び後処理を実施する上では、共通する水素ラジカル照射機構が使用可能となる。そのため、半導体装置における製造システムの観点からすれば、上述する前処理と後処理とを実施するための装置について共通化を図ることが可能となり、こうした半導体装置を製造する上において、装置占有面積の拡大を抑えることが可能にもなる。   (7) Since the pretreatment of the ZrBN film 21 and the posttreatment of the ZrBN film 21 are common hydrogen radical irradiation treatments, the common hydrogen radical irradiation mechanism is used in performing these pretreatments and posttreatments. Can be used. Therefore, from the viewpoint of a manufacturing system in a semiconductor device, it is possible to share the devices for performing the above-described pre-processing and post-processing. In manufacturing such a semiconductor device, the area occupied by the device It becomes possible to suppress expansion.

なお、上記実施形態は以下のように変更して実施することもできる。
・凹部２０の内側に付着した残渣がＺｒＢＮ膜２１を形成する前に取り除かれる処理であれば、上述するような水素ラジカルの照射処理に代わり、還元性の雰囲気下で基板を熱処理する構成であってもよい。このような構成であっても、ＺｒＢＮ膜２１とその下地との密着性が向上可能である。In addition, the said embodiment can also be changed and implemented as follows.
If the residue adhered to the inside of the recess 20 is removed before the ZrBN film 21 is formed, the substrate is heat-treated in a reducing atmosphere instead of the hydrogen radical irradiation treatment as described above. May be. Even with such a configuration, the adhesion between the ZrBN film 21 and the underlying layer can be improved.

・エッチングストッパ膜１３ｃ上に積層された各膜を除去する方法としては、上述したＣＭＰ法の他、物理的なエッチング法が適用可能である。こうした構成であれば、エッチングストッパ膜１３ｃ上に積層された各膜の一部を除去することが可能となる。   As a method of removing each film laminated on the etching stopper film 13c, a physical etching method can be applied in addition to the CMP method described above. With such a configuration, it is possible to remove a part of each film laminated on the etching stopper film 13c.

・凹部２０の内側に残渣が付着していない構成、あるいは、このような残渣があってもＺｒＢＮ膜２１とその下地との間に十分な密着性が確保される構成であれば、上述するような前処理が割愛される構成であってもよい。このような構成であれば、ＺｒＢＮ膜２１に対する前処理が不要となることから、半導体装置の製造工程における工程数が低減可能となり、ひいては半導体装置の生産性が向上可能にもなる。   As described above, a configuration in which no residue adheres to the inside of the recess 20 or a configuration in which sufficient adhesion is ensured between the ZrBN film 21 and the underlying layer even if such a residue is present. It may be a configuration that omits pre-processing. With such a configuration, the pretreatment for the ZrBN film 21 is not necessary, so that the number of steps in the manufacturing process of the semiconductor device can be reduced, and thus the productivity of the semiconductor device can be improved.

・ＺｒＢＮ膜２１に関わる前処理、ＺｒＢＮ膜２１の成膜処理、ＺｒＢＮ膜２１に関わる後処理、及び銅シード膜２２の成膜処理については、共通する真空系において連続的にて実行される構成が好ましい。こうした構成であれば、凹部２０の内壁とＺｒＢＮ膜２１との界面、及びＺｒＢＮ膜２１と銅シード膜２２との界面の各々が、大気に曝されることなく形成される。それゆえに、凹部２０の内壁とＺｒＢＮ膜２１との界面、及びＺｒＢＮ膜２１と銅シード膜２２との界面の各々において、密着性が向上可能となる。   A configuration in which pre-processing related to the ZrBN film 21, film-forming processing of the ZrBN film 21, post-processing related to the ZrBN film 21, and film-forming processing of the copper seed film 22 are continuously executed in a common vacuum system. Is preferred. With such a configuration, each of the interface between the inner wall of the recess 20 and the ZrBN film 21 and the interface between the ZrBN film 21 and the copper seed film 22 is formed without being exposed to the atmosphere. Therefore, adhesion can be improved at each of the interface between the inner wall of the recess 20 and the ZrBN film 21 and the interface between the ZrBN film 21 and the copper seed film 22.

・ＺｒＢＮ膜２１の表面から窒素を取り除く処理としては、当該表面に水素ラジカルを照射する処理の他、例えば軽元素である窒素のみをＺｒＢＮ膜２１からスパッタする物理的な表面処理や、ＺｒＢＮ膜２１の表面における窒素のみを熱反応で還元して反応生成物として気化させる化学的な表面処理等が適用可能である。   As the process for removing nitrogen from the surface of the ZrBN film 21, in addition to the process of irradiating the surface with hydrogen radicals, for example, a physical surface process in which only light element nitrogen is sputtered from the ZrBN film 21, or the ZrBN film 21 A chemical surface treatment or the like in which only nitrogen on the surface of the metal is reduced by a thermal reaction and vaporized as a reaction product can be applied.

・凹部２０は接続孔１７及び配線溝１８から構成されるデュアルダマシンパターンに限定されない。凹部２０は例えば接続孔１７及び配線溝１８の一方から構成されてもよい。   The recess 20 is not limited to the dual damascene pattern configured by the connection hole 17 and the wiring groove 18. For example, the recess 20 may be composed of one of the connection hole 17 and the wiring groove 18.

Claims (5)

基板上の絶縁膜が有する凹部の内側を硼窒化ジルコニウム膜で被覆する工程と、
前記硼窒化ジルコニウム膜の表面をＰＶＤ法により銅シード膜で被覆する工程と、
前記銅シード膜で被覆された前記凹部の内側をめっき法により銅めっき膜で充填する工程と、
前記硼窒化ジルコニウム膜の表面を前記銅シード膜で被覆する前に、前記硼窒化ジルコニウム膜の表面から、少なくとも窒素を取り除いて当該表面を導体化させる工程とを備え、
前記導体化される前記硼窒化ジルコニウム膜の厚さが目標の厚さに到達するまでの目標処理時間を予め取得し、前記窒素を取り除く処理を当該目標処理時間だけ実行することを特徴とする半導体装置の製造方法。 Coating the inside of the recess of the insulating film on the substrate with a zirconium boronitride film;
Coating the surface of the zirconium boronitride film with a copper seed film by PVD method;
Filling the inside of the recess covered with the copper seed film with a copper plating film by a plating method;
Before covering the surface of the zirconium boronitride film with the copper seed film, removing at least nitrogen from the surface of the zirconium boronitride film, and making the surface conductive .
It wherein the thickness of said boronitride zirconium film is the conductor of the previously acquired the target process time to reach the target thickness, executes a process of removing the nitrogen only the target processing time A method for manufacturing a semiconductor device. 前記硼窒化ジルコニウム膜の表面に水素ラジカルを照射して当該表面を導体化させることを特徴とする請求項１に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the surface of the zirconium boronitride film is irradiated with hydrogen radicals to make the surface conductive. 前記絶縁膜上に形成された銅めっき膜、銅シード膜及び前記硼窒化ジルコニウム膜をＣＭＰ法により研削して前記基板上を平坦化する工程を備え、
前記研削する工程では前記硼窒化ジルコニウム膜を前記目標となる厚さだけ研削することを特徴とする請求項１又は２に記載の半導体装置の製造方法。 A step of flattening the substrate by grinding a copper plating film, a copper seed film and the zirconium boronitride film formed on the insulating film by a CMP method;
The method of manufacturing a semiconductor device according to claim 1 or 2 in the step of the grinding, wherein the grinding by a thickness which becomes the target of the boronitride zirconium film. 前記絶縁膜が有する凹部は、前記絶縁膜の下地である導電膜に接続された接続孔であり、
前記絶縁膜が有する接続孔の内側を前記硼窒化ジルコニウム膜で被覆する前に、前記絶縁膜及び前記導電膜の表面に水素ラジカルを照射することを特徴とする請求項１〜３のいずれか一項に記載の半導体装置の製造方法。 The concave portion of the insulating film is a connection hole connected to a conductive film that is a base of the insulating film,
Wherein an inner connection hole having an insulating film having before coating with the boronitride zirconium film, said insulating film and any one of claims 1-3, characterized in that irradiation of hydrogen radicals on the surface of the conductive layer A method for manufacturing the semiconductor device according to the item. 前記凹部は、配線溝と接続孔とを含むデュアルダマシンパターンであり、
前記配線溝と接続孔を前記硼窒化ジルコニウム膜で被覆し、
水素ラジカルの照射により、前記配線溝と接続孔を被覆する前記硼窒化ジルコニウム膜の表面から少なくとも窒素を取り除いて当該表面を導体化させ、
その後、前記配線溝と接続孔を被覆する前記硼窒化ジルコニウム膜を前記銅シード膜で被覆することを特徴とする請求項１〜３のいずれか一項に記載の半導体装置の製造方法。 The recess is a dual damascene pattern including a wiring groove and a connection hole,
The wiring groove and the connection hole are covered with the zirconium boronitride film,
By irradiation with hydrogen radicals, at least nitrogen is removed from the surface of the zirconium boronitride film covering the wiring groove and the connection hole, and the surface is made into a conductor,
Then, a method of manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that covering the boronitride zirconium film covering said wiring groove and the connection hole in the copper seed layer.
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