TW201125074A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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TW201125074A
TW201125074A TW099139087A TW99139087A TW201125074A TW 201125074 A TW201125074 A TW 201125074A TW 099139087 A TW099139087 A TW 099139087A TW 99139087 A TW99139087 A TW 99139087A TW 201125074 A TW201125074 A TW 201125074A
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Taiwan
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film
zrbn
copper seed
insulating film
wiring
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TW099139087A
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Chinese (zh)
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Masanobu Hatanaka
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Ulvac Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76823—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. transforming an insulating layer into a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for manufacturing semiconductor device includes: forming a ZrBN film on a groove of an insulated film of a substrate; forming a copper seed layer on the ZrBN film; filling a copper plating film in the groove covered by the copper seed layer; and removing nitrogen from the surface of ZrBN film before the cooper seed layer is formed on the ZrBN film to metalize the surface of ZrBN film.

Description

201125074 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體裝置之製造方法，尤其是關 於一種在具有絕緣膜的凹部之内側，藉由鍍金屬法填充鍍 銅膜而成的半導體裝置之製造方法。 【先前技術】 在半導體裝置之配線技術中，隨著配線結構之細微化 或多層化進展，伴隨著電流密度之增加所引起的電子遷移 (EM)問題就更加嚴重。為了避免此種問題而需要具有較高 之EM耐性的銅（Cu)配線之多層配線結構。因此，在難以 進行化學蝕刻的Cu配線之多層配線技術中，用以取代利用 蝕刻法之加工方法的鑲嵌法或雙重鑲嵌法是不可或缺的。 在鑲嵌法或雙重鑲嵌法中，首先係將配合配線形狀的 凹部事先形成於層間絕緣膜，接著將埋設於該凹部内側的 配線形成塊（Bulk)狀Cu膜的形狀。然後藉由化學機械研 磨去除形成層間絕緣膜的Cu膜等、形成於凹部外側的Cu 膜，藉此形成以Cu膜為主的配線結構。 在上述的配線形成製程中，首先係對具有配線槽或連 接孔等之凹部的層間絕緣膜應用濺鍍法等，並藉由用以抑 制Cu擴散至層間絕緣膜中的障壁膜，被覆包含凹部内側的 層間絕緣膜之表面全體。接著對形成有障壁膜的半導體基 板應用減:鍍法等，並藉由用以使Cu膜成長的銅晶種膜，被 覆上述障壁膜之表面全體、即包含凹部内側全體的基板表 面。然後對形成有銅晶種膜的半導體基板應用鍍金屬法， 201125074 以埋設於凹部内側之形式形成Cu膜。藉由執行如此的各種 成膜製程，玎形成由障壁膜、銅晶種膜、及Cu膜所構成的 Cu配線。 抑止Cu擴散的障壁膜之構成材料中，為人周知者有 例如钽(Ta)或硼氮化鍅(ZrBN)。此等的Ta膜或zrBN膜均 被發現具有優異的障壁性，但另一方面，在各別具有的導 電性之基底依存性方面，有較大的差異。換句話說，無論 基底是否為導電性，相對於具有導電性的Ta獏，ZrBN膜 係成為基底的膜為導電性就會具有導電性，而成為底層的 膜為絕緣性就會具有絕緣性(例如，專利文獻丨）。因此，在 具有此種障壁膜的Cu配線中，按照障壁膜之構成材料為 Ta、或是ZrBN，接續於障壁膜之成膜製程的後段製程之内 容就有所不同。 例如’若以Ta膜作為障壁膜而適用於凹部，則除了 凹部之内側全體’就連層間絕緣膜上也會沉積有Ta膜。故 而，為了要確保層間的絕緣性，就有必要藉由化學機械研 磨完全地去除沉積於層間絕緣膜上的此種Ta膜。相對於 此’若以ZrBN膜作為障壁膜而適用於凹部，則沉積於凹 部底部的Ζι:ΒΝ膜會具有導電性，而沉積於層間絕緣膜上 的Z，膜會具有絕緣性。故而，在確保層間的絕緣性之 ，而s ’也無必要完全地去除沉積於層間絕緣膜上的此種 膜。因此’關於Cu配線之障壁膜’為了謀求此種後 又1程之便利性’以致於精心地檢討如上述的2疆膜。 [利文獻1]日本專利公開公報特開 2008-211079 ^ 4 201125074 ί發明内容】 (發明所欲解決之課題） 如上所述，當ZrBN膜為障壁膜時，若與該障壁膜相 接的基底層為導電體，則障壁膜(ZrBN膜）也會成為導電 體，反之，若與該障壁臈相接的基底層為絕緣體，則障壁 膜(ZrBN膜）也會成為絕緣體。然後，利用pvD法的銅晶種 膜係形成於具有如此導電率之分佈的ZrBN膜上，再者， 利用鍵金屬法的Cu膜係形成於該銅晶種膜上。參照圖 4(a)、（b)，說明ZrBN骐、銅晶種膜、及Cu膜。 如圖4(a)所示，在形成於基板的第一層間絕緣膜D1 上，疊層有由障壁膜BM與蝕刻阻擋膜ESa所包夾的第一 配線膜Ml。在該第一配線膜Ml上，曼層有由钱刻阻擋膜 ESa、ESb所包夾的第二層間絕緣膜，且在第二層間絕 緣膜D2上’疊層有由蝕刻阻擋膜ESb、ESC所包夾的第三 層間絕緣膜D3。在第二層間絕緣膜D2及包夾此第二層間 絕緣膜D2的一對蝕刻阻擋膜ESa ' ESb，係穿設有以貫穿 該一對蝕刻阻擋膜ESa、ESb之形式，向疊層方向延伸的 連接孔CH。又在第三層間絕緣獏D3及疊層於第三層間絕 緣膜D3的蝕刻阻擋膜ESC中，貫穿此等第三層間絕緣膜 D3及蚀刻阻擋膜ESC的配線槽LG係以從連接孔CH擴開 之形式穿a又。然後’在此專連接孔ch之内侧、配線槽LG 之内侧、及配線槽LG之開口外側，以覆蓋此等全體的方 式疊層有ZrBN膜51。 在如此構成的ZrBN膜之中，與亦為第一配線膜Ml 之一部分的連接孔CH之底部相接的部分，ZrBN膜係發揮 作為導電體的功能。另一方面，在與連接孔CH之周面及 201125074 配線槽LG之槽侧面相接的部分，ZrBN膜係發揮作為絕緣、 體的功能。在此’當相對於具有此種導電率之分佈的ZrBN 膜’疊層利用PVD法的銅晶種膜時，由於缺乏銅晶種膜對 絕緣體之密接性，所以特別在成膜速度變慢的連接孔CH 之底部周圍，Cu粒子會以底部側壁為中心而凝聚使銅晶種 膜成為粒狀之成膜狀態（參照圖4(a))。若對於處於此種极狀 之成膜狀態的銅晶種膜應用鍍金屬法，則表面處理用之酸 性液體會進入Cu粒子之間、進而進入連接孔CH與粒 子之間，而在處於⑽之成難_部分，侧速度會變 大。其結果’如圖4(b)所示，在連接孔CH之底部周圍， 由於藉由鍍金屬法難以成長〇^膜53,所以〇11膜53與第 -配線膜Mi之間的接觸電阻會增加，最終就連電性連接 也難以獲得。在配線結構之細微化進展的近年，也由於 晶種膜之薄膜化的需求’所以上述㈣題漸漸地顯著化。 本發f係有鑒於上述問題而開發完成者，其目的在於 提供一種半導體裝置之製造方&，Mg Λ 4万凌以耠鬲藉由鍍金屬法填 充於，、有、，邑緣膜的凹部内側之鍍銅膜的埋嗖 (解決課題之手段） ° 將用以解決上述課題的手段及其作用效 本發明之第-態樣的半導體裝置之:且 備：以硼氮化賴被覆基板上之具有 凹 而沾―種膜被覆㈣魏化錯膜之表 ’製，# Μ金屬法，㈣賴填充 膜所被覆之前述凹部内側的製程；以及在以種 被覆前述喊憾歡表面前 面至少去除掉氣，##▲ 魏化錯膜之表 面至/舌除掉1使該表面導體化的製程。 6 201125074 ，導電體的銅晶種膜之構成材料與相異於此的絕緣體 之間的密接性，與導電體彼此間之密接性或絕緣體彼此間 之密接性相較，一般係較低。因此，若藉由PVD法將銅晶 種膜形成於絕緣體上，則與如此的銅晶種膜形成於導電體 上的情況相較’容易發生銅晶種膜中的凝聚。尤其是若在 具有絕緣膜的凹部之内侧，藉由PVD法被覆銅晶種膜，則 隨著具有絕緣膜的凹部變深，鋼晶種膜之構成元素就難以 到達凹部之底面，由於該處的鋼晶種膜之成長速度變慢， 所以更容易發生如上所述的凝聚現象。 此點’若依據第一態樣’則在表面被導體化的硼氮化 锆膜上，形成有藉由PVD法所得的銅晶種膜。換句話說， 即使在具有絕緣膜的凹部之内側，硼氮化錘膜之表面被導 體化，並在如此被導體化的硼氮化鍅膜上形成銅晶種膜。 故而，可在具有絕緣體的凹部之内側全體，提高成為障壁 膜的爛氮化結膜與銅晶種膜之密接性，於凹部之内側全 體，抑制上述在銅晶種膜中的凝聚現象。 其結果，在形成銅晶種膜之後的鍍金屬製程中，由於 可抑制銅晶種膜的粒狀體本身之成長，所以鑛金屬的溶液 難以滲入如此的粒狀體之間。然後，鍍金屬的溶液之蝕刻 速度大於鍍金屬膜之成長速度本身即受到抑制。因而，對 於具有絕緣膜的凹部可提向錄銅膜之埋設性。故而，若為 僅蝴氮化錯膜之表面被導體化的構成，也容易研磨如此的 表面並予以去除。因此，即使是對於被覆於絕緣膜上的棚 氮化錯膜需要絕緣性的情況，也可容易引出硼氮化锆膜之 本來所具有的導電率之選擇性。 其一例中，係在前述硼氮化锆膜之表面照射氫基，使 201125074 該表面導體化。 ，從领氮化錯膜之表面去除掉氣的處理，例如可 從魏化⑽濺驗元素之氮的物理性表面處理 熱反應來縣魏㈣叙表面賴， 為 生成物的化學性表面處理等。氫基之照射 :的物理性或化學性表面處理中，也:= 膜之電氣性及熱性損傷。 ⑽化錯 产之,事先取得前述導體化的厚度到達目標厚 僅以該目標處理時間執行前述去除掉 若過度進行如上述之去除掉氮的處理，則硼氮化錯膜 t來所具有的導電率之選擇性也會消失。反之，若去除掉 氮的處料足’則會_氮祕膜之表㈣導體化之不足 而難以獲得所期望賴娜之埋設性 =來執行去除掉氮的處理，即可抑制= 其―例中，係更具備藉由⑽法研削已形成於前述絕 、^膜上的鍍銅膜、銅晶種膜及前述简化 t平坦化的製程。在前述研削之製程中，將前述棚^ 錯膜研削成為前述目標的厚度。 從形成於絕緣膜上的硼氮化锆犋來看，由於僅被導體 2的部分被研肖彳，所以即使在被平垣化後的基板上殘留蝴 氮化錘膜，如此的硼氮化锆膜也會具有絕緣性。因而，可 更確實地實現蝴氮化鍅膜本來所具有的導電率之選擇性。 其一例中，前述具有絕緣膜的凹部係被連接於前述絕 緣膜之基底的導電臈之連接孔，在以前述硼氮化锆膜被覆 201125074 前述具有絕緣膜的連接孔之内側之前，在前述絕緣膜及前 述導電膜之表面照射氫基。其一例中，前述凹部係包含配 線槽與連接孔的雙重鑲嵌圖案’以前述硼氮化錯膜被覆前 述配線溝與連接孔’藉由氫基之照射，從被覆前述配線槽 與連接孔的前述硼氮化锫膜之表面至少去除掉氮，使該表 面導體化，之後，以前述銅晶種膜被覆用以被覆前述配線 槽與連接孔的前述硼氮化錘膜。 由於在硼氮化鍅膜之基底的絕緣膜及導電膜之表面 施予氫基之還原處理，所以即使在此等絕緣膜及導電膜之 表面存在有機物等之絕緣性異物的情況，也可去除掉此等 的異物。其結果，可提高硼氮化锆膜與絕緣膜之間的密接 性。再者’由於可更確實地獲得硼氮化錘膜與導電膜之間 的電性連接’所以可更確實地獲得被填充於具有絕緣膜之 連接孔的鍍銅膜與導電膜之間的電性連接性。 【實施方式】 以下’參照圖式說明將本發明具體化的一實施形態。 如圖1所示，在構成半導體裝置之製造方法的CU配線之形 成方法中’係依序執行如下製程：於基板上的絕緣膜形成 作為凹部之雙重鑲嵌圖案的製程(；步驟S1);對於該凹部施 予前處理的製程（步驟S2);及以硼氮化锆膜(ZrBN膜)被覆 該凹部之内側的製程（步驟S3)。接著，依序執行如下製程： 對於ZrBN膜施予後處理的製程（步驟S4);藉由PVD法， 以铜晶種膜被覆ZrBN膜之表面的製程（步驟S5);藉由鍍 金屬法，以鍍銅膜填充於由銅晶種膜所被覆的凹部之内側 201125074 的製程（步驟S6);以及將絕緣膜上平坦化的cmp製程（步 驟 S7)。 在上述凹部之形成製程之前，如圖2(a)、（b)所示，先 在基板上形成有第一層間絕緣膜11。在該第一層間絕緣膜 11上，係疊層有由障壁膜12與蝕刻阻擋膜13a所包夾的配 線膜14。在該配線膜14上，係疊層有由触刻阻擔膜13 a^ 13b所包夾的第二層間絕緣膜15，另在第二層間絕緣膜15 上，係疊層有由姓刻阻擋膜13b、13c所包夾的第三層間絕 緣膜16。 另外’各層間絕緣膜11、15、16,例如是由矽氧化物 或含碳矽氧化物等所構成的絕緣膜，且藉由化學氣相沉積 法（Chemical Vapor Deposition法：CVD法）或旋塗法等之成 膜方法所形成。配線臈14，例如是由鋁或鈦、銅或鈕等所 構成的多層之導電膜，且藉由物理氣相沉積法（physical Vapor Deposition法：PVD法）或CVD法等之成膜方法所形 成。由第一層間絕緣膜n與配線膜14所包夾的障壁膜12 係具有抑制配線膜14之構成材料擴散於層間絕緣膜的功 能，由金屬氮化物或矽碳化物等所構成的薄膜，藉由CVD 法或PVD法、旋塗法等之成膜方法所形成。各餃刻阻指膜 13a、13b、13c係具有對層間絕緣膜之適當的蝕刻選擇性、 及抑制配_ 14之構紐料缝至層㈣賴的功能，由 矽碳化物或矽氧氮化鎢等所構成，藉由CVD法或旋塗法等 之成膜方法所形成。 如圖2所示，在上述凹部之形成製程（步驟si)中，在 第三層間絕緣膜16及疊層於第三層間絕緣膜16之餘刻阻 擋膜⑼，藉&乾㈣法，形成有貫穿此㈣並從連接孔 10 201125074 '16擴開之配線槽18。又，在第二層間絕緣膜15及包夾第 二層間絕緣膜15之一對蝕刻阻擋膜13a、13b，藉由乾蝕 刻法，形成貫穿此等膜之連接孔17。然後，以配線膜14 之一部分露出外側的形式，形成由此等連接孔（穿孔）17及 配線槽18所構成的凹部20。 另外，如上所述，在形成凹部20之過程中，由於是 使用含碳之有機系的光阻，所以在凹部20之内部或蝕刻阻 擋膜13c上，容易附著此種光阻之殘渣異物。又，即使以 含碳之構成材料形成蝕刻阻擋膜13a、13b、13c的情況時， 此種含碳之異物也容易附著於凹部20之内部。 在對上述凹部20施予前處理的製程（步驟S2)中，在 包含該凹部20的基板表面之全體照射氫基。當如此地在基 板表面之全體照射氫基時，依氫基所進行的碳之還原處 理，會在包含凹部20的基板表面之全體進行。其結果，構 成凹部20之底面的配線膜14之一部分、構成凹部20之側 面的第二層間絕緣膜15或第三層間絕緣膜16之一部分、 進而蝕刻阻擋膜13b、13c等附著於此等膜之表面的有機系 之異物，就可從該表面去除掉。 此種前處理的態樣之一例，可舉例如以下態樣：即接 收微波之氫氣生成氫基，並在容納有基板的真空室内供給 該氫基。將如此使用微波與氫氣之前處理中的處理條件之 一例顯示如下。 •基板溫度：l〇〇°C至250°c •氫氣流量：200sccm •氬氣流量：30sccm •處理壓力：50Pa至500Pa 11 201125074BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, and more particularly to a semiconductor in which a copper plating film is filled by a metal plating method on the inner side of a recess having an insulating film. The manufacturing method of the device. [Prior Art] In the wiring technology of a semiconductor device, as the wiring structure is made finer or multilayered, the problem of electron migration (EM) caused by an increase in current density is more serious. In order to avoid such a problem, a multilayer wiring structure of copper (Cu) wiring having high EM resistance is required. Therefore, in the multilayer wiring technique of Cu wiring which is difficult to perform chemical etching, a damascene method or a dual damascene method which is used in place of the processing method using an etching method is indispensable. In the damascene method or the dual damascene method, first, a recessed portion in which a wiring shape is formed is formed in advance on an interlayer insulating film, and then a wiring buried inside the recessed portion is formed into a shape of a Bulk-like Cu film. Then, a Cu film formed on the outer side of the concave portion, such as a Cu film forming an interlayer insulating film, is removed by chemical mechanical polishing to form a wiring structure mainly composed of a Cu film. In the above-described wiring forming process, first, a sputtering method or the like is applied to an interlayer insulating film having a recessed portion such as a wiring trench or a connection hole, and the recessed portion is covered by a barrier film for suppressing diffusion of Cu into the interlayer insulating film. The entire surface of the interlayer insulating film on the inside. Then, the semiconductor substrate on which the barrier film is formed is subjected to a subtractive plating method or the like, and the entire surface of the barrier film, that is, the substrate surface including the entire inner side of the concave portion, is covered by the copper seed film for growing the Cu film. Then, a metal plating method is applied to the semiconductor substrate on which the copper seed film is formed, and 201125074 forms a Cu film in the form of being buried inside the concave portion. By performing such various film forming processes, a Cu wiring composed of a barrier film, a copper seed film, and a Cu film is formed. Among the constituent materials of the barrier film which suppresses the diffusion of Cu, for example, tantalum (Ta) or lanthanum borohydride (ZrBN) is known. Each of these Ta films and zrBN films was found to have excellent barrier properties, but on the other hand, there was a large difference in the substrate dependence of the respective conductivity. In other words, regardless of whether or not the substrate is electrically conductive, the film which becomes the base of the ZrBN film is electrically conductive with respect to the conductive Ta貘, and the film which becomes the underlayer is insulating and has insulation ( For example, the patent document 丨). Therefore, in the Cu wiring having such a barrier film, the composition of the barrier film is Ta or ZrBN, and the content of the subsequent process of the film formation process of the barrier film is different. For example, when the Ta film is used as the barrier film and is applied to the concave portion, the Ta film is deposited on the interlayer insulating film except for the entire inner side of the concave portion. Therefore, in order to ensure insulation between the layers, it is necessary to completely remove such a Ta film deposited on the interlayer insulating film by chemical mechanical polishing. With respect to this, if the ZrBN film is used as the barrier film and is applied to the concave portion, the Ζ: ΒΝ film deposited on the bottom of the concave portion may have conductivity, and the Z deposited on the interlayer insulating film may have insulating properties. Therefore, in order to ensure insulation between the layers, it is not necessary to completely remove such a film deposited on the interlayer insulating film. Therefore, the "barrier film for Cu wiring" has been carefully reviewed in order to achieve such a convenience. [Problems to be Solved by the Invention] As described above, when the ZrBN film is a barrier film, if the substrate is in contact with the barrier film When the layer is a conductor, the barrier film (ZrBN film) also becomes a conductor. On the other hand, if the base layer that is in contact with the barrier 臈 is an insulator, the barrier film (ZrBN film) also becomes an insulator. Then, a copper seed film formed by the pvD method is formed on the ZrBN film having such a distribution of conductivity, and a Cu film formed by a bond metal method is formed on the copper seed film. Referring to Figures 4(a) and 4(b), ZrBN骐, a copper seed film, and a Cu film will be described. As shown in Fig. 4 (a), a first wiring film M1 sandwiched by the barrier film BM and the etching stopper film ESa is laminated on the first interlayer insulating film D1 formed on the substrate. On the first wiring film M1, the gate layer has a second interlayer insulating film sandwiched by the etching mask films ESa and ESb, and the interlayer insulating film D2 is laminated with an etching stopper film ESb and ESC. The sandwiched third interlayer insulating film D3. The second interlayer insulating film D2 and the pair of etching stopper films ESa' ESb sandwiching the second interlayer insulating film D2 are formed to penetrate the pair of etching stopper films ESa and ESb and extend in the lamination direction. Connection hole CH. Further, in the third interlayer insulating layer D3 and the etching stopper film ESC laminated on the third interlayer insulating film D3, the wiring trenches LG penetrating through the third interlayer insulating film D3 and the etching stopper film ESC are expanded from the connection holes CH. Open the form to wear a again. Then, the ZrBN film 51 is laminated on the inside of the dedicated connection hole ch, the inside of the wiring groove LG, and the outside of the opening of the wiring groove LG so as to cover the entire surface. Among the ZrBN films thus constituted, the ZrBN film functions as a conductor in a portion in contact with the bottom of the connection hole CH which is also a part of the first wiring film M1. On the other hand, the ZrBN film functions as an insulator or a body in a portion that is in contact with the circumferential surface of the connection hole CH and the groove side surface of the 201125074 wiring groove LG. Here, when a copper seed film using a PVD method is laminated on a ZrBN film having a distribution of such conductivity, since the adhesion of the copper seed film to the insulator is lacking, the film formation speed is particularly slow. Around the bottom of the connection hole CH, the Cu particles are aggregated around the bottom side wall to form a film state in which the copper seed film is formed into a granular shape (see FIG. 4(a)). When a metal plating method is applied to a copper seed film in such a polar film forming state, the acidic liquid for surface treatment enters between the Cu particles and further enters the connection hole CH and the particles, and is at (10). In the difficult part, the side speed will become larger. As a result, as shown in FIG. 4(b), since it is difficult to grow the film 53 by the metal plating method around the bottom of the connection hole CH, the contact resistance between the 〇11 film 53 and the first wiring film Mi is Increase, and ultimately even the electrical connection is difficult to obtain. In recent years, in the progress of the miniaturization of the wiring structure, the above-mentioned (4) problems have gradually become more prominent due to the demand for thinning of the seed crystal film. The present invention has been developed in view of the above problems, and an object of the present invention is to provide a semiconductor device manufacturing device, which is filled with a metal film by a metal plating method. Buried copper plating film on the inner side of the concave portion (means for solving the problem) ° A means for solving the above problems and a semiconductor device according to the first aspect of the invention, and comprising: a boron nitride-coated substrate The surface has a concave and smear-film coating (4) Weihua mis-filming method, #Μ metal method, (4) the inner side of the concave portion covered by the filling film; and at least the surface of the aforementioned shouting Remove the gas, ##▲ The surface of the Weihua wrong film to / tongue removed 1 to make the surface conductor process. 6 201125074 The adhesion between the constituent materials of the copper seed film of the conductor and the insulator different therefrom is generally lower than the adhesion between the conductors or the adhesion between the insulators. Therefore, when the copper seed film is formed on the insulator by the PVD method, aggregation of the copper seed film is likely to occur as compared with the case where such a copper seed film is formed on the conductor. In particular, when the copper seed crystal film is coated by the PVD method inside the concave portion having the insulating film, the constituent elements of the steel seed crystal film hardly reach the bottom surface of the concave portion as the concave portion having the insulating film becomes deep, because The growth rate of the steel seed crystal film becomes slow, so that the agglomeration phenomenon as described above is more likely to occur. At this point, according to the first aspect, a copper seed film obtained by a PVD method is formed on a boron nitride film having a surface on which a surface is formed. In other words, even on the inner side of the concave portion having the insulating film, the surface of the borax nitride film is guided, and a copper seed film is formed on the thus-conducted lanthanum borohydride film. Therefore, the adhesion between the ruined tantalum film which is a barrier film and the copper seed film can be improved in the entire inner side of the recessed portion having the insulator, and the entire surface of the recessed portion can be suppressed to suppress the agglomeration in the copper seed film. As a result, in the metal plating process after the formation of the copper seed film, since the growth of the granular body itself of the copper seed film can be suppressed, it is difficult for the solution of the mineral metal to infiltrate between such granular bodies. Then, the etching rate of the metal plating solution is greater than the growth rate of the metal plating film itself, which is suppressed. Therefore, the recessed portion having the insulating film can be provided with the embedding property to the copper film. Therefore, if the surface of the nitriding film is conductor-conducted, it is easy to polish and remove such a surface. Therefore, even if it is necessary to insulate the lining nitride film coated on the insulating film, the conductivity selectivity inherent to the borozirconium nitride film can be easily extracted. In one example, a hydrogen group is applied to the surface of the zirconium oxynitride film to electrically conduct the surface of 201125074. The treatment for removing the gas from the surface of the collar nitride film, for example, the physical surface treatment heat reaction of the nitrogen of the element of the Weihua (10) can be used to treat the surface of the chemical, such as the chemical surface treatment of the product. . Hydrogen-based irradiation: In the physical or chemical surface treatment, also: = electrical and thermal damage of the membrane. (10) If the thickness of the conductor is obtained in advance, the thickness of the conductor is obtained to reach the target thickness, and the removal is performed only at the target processing time. If the treatment for removing nitrogen as described above is excessively performed, the conductivity of the boron nitride barrier film t is obtained. The selectivity of the rate will also disappear. On the other hand, if the nitrogen removal material is sufficient, the surface of the nitrogen film (4) is insufficiently conductive and it is difficult to obtain the desired burial property of the rya = to perform the process of removing the nitrogen, so that it can be suppressed = In addition, the copper plating film, the copper seed crystal film which has been formed on the above-mentioned insulating film, and the above-described simplified t planarization process are further provided by the method (10). In the above-described grinding process, the above-mentioned smear film is ground to the thickness of the aforementioned target. From the viewpoint of the zirconium borozide formed on the insulating film, since only a portion of the conductor 2 is etched, such a zirconium nitride is left even on the substrate which is flattened. The film will also be insulating. Therefore, the selectivity of the conductivity originally possessed by the hafnium nitride film can be more surely achieved. In one example, the recessed portion having the insulating film is connected to the connection hole of the conductive crucible on the base of the insulating film, and the insulating layer is coated on the inner side of the connection hole having the insulating film of 201125074 after the boron oxynitride film is coated. The surface of the film and the foregoing conductive film is irradiated with a hydrogen group. In one example, the recessed portion includes a double damascene pattern of a wiring groove and a connection hole, wherein the wiring hole and the connection hole are covered with the boron nitride film by a hydrogen base, and the aforementioned wiring groove and the connection hole are covered. At least the nitrogen is removed from the surface of the lanthanum boronitride film to conduct the surface, and then the boron nitride film is coated with the copper seed film to cover the wiring groove and the connection hole. Since the hydrogen substrate is subjected to a reduction treatment on the surface of the insulating film and the conductive film on the base of the lanthanum arsenide film, even if an insulating foreign matter such as an organic substance is present on the surface of the insulating film or the conductive film, it can be removed. Drop such foreign objects. As a result, the adhesion between the boron nitridation film and the insulating film can be improved. Furthermore, since the electrical connection between the boron nitride hammer film and the conductive film can be obtained more surely, the electric power between the copper plating film and the conductive film filled in the connection hole having the insulating film can be more surely obtained. Sexual connectivity. [Embodiment] Hereinafter, an embodiment in which the present invention is embodied will be described with reference to the drawings. As shown in FIG. 1, in the method of forming a CU wiring constituting a manufacturing method of a semiconductor device, a process of forming a double damascene pattern as a concave portion on an insulating film on a substrate is sequentially performed (step S1); The concave portion is subjected to a pretreatment process (step S2); and a process of coating the inner side of the concave portion with a zirconium oxynitride film (ZrBN film) (step S3). Then, the following processes are sequentially performed: a process for applying a post-treatment to the ZrBN film (step S4); a process of coating the surface of the ZrBN film with a copper seed film by a PVD method (step S5); The copper plating film is filled in the process of the inner side 201125074 of the concave portion covered by the copper seed crystal film (step S6); and the cmp process for flattening the insulating film (step S7). Before the formation process of the above-described concave portion, as shown in Figs. 2(a) and 2(b), a first interlayer insulating film 11 is formed on the substrate. On the first interlayer insulating film 11, a wiring film 14 surrounded by the barrier film 12 and the etching stopper film 13a is laminated. On the wiring film 14, a second interlayer insulating film 15 sandwiched by the etch resist film 13a 13b is laminated, and on the second interlayer insulating film 15, the laminated film is blocked by a surname. The third interlayer insulating film 16 sandwiched by the films 13b and 13c. Further, each of the interlayer insulating films 11, 15, 16 is, for example, an insulating film made of tantalum oxide or carbon-containing tantalum oxide, and is subjected to chemical vapor deposition (Chemical Vapor Deposition: CVD) or spin. It is formed by a film forming method such as coating. The wiring layer 14 is, for example, a multilayer conductive film made of aluminum or titanium, copper or a button, and is formed by a film forming method such as physical vapor deposition (PVD) or CVD. . The barrier film 12 sandwiched between the first interlayer insulating film n and the wiring film 14 has a function of suppressing diffusion of a constituent material of the wiring film 14 to the interlayer insulating film, and is composed of a metal nitride or a tantalum carbide. It is formed by a film formation method such as a CVD method, a PVD method, or a spin coating method. Each of the dumping resisting films 13a, 13b, and 13c has a function of appropriately etching the interlayer insulating film and suppressing the function of the bonding of the bonding layer to the layer (4), and the ruthenium carbide or niobium oxynitride. It is formed of tungsten or the like and formed by a film formation method such as a CVD method or a spin coating method. As shown in FIG. 2, in the forming process of the recess (step si), the third interlayer insulating film 16 and the remaining barrier film (9) laminated on the third interlayer insulating film 16 are formed by the & dry method. There is a wiring slot 18 extending through this (4) and extending from the connection hole 10 201125074 '16. Further, in the second interlayer insulating film 15 and one of the second interlayer insulating films 15, the etching stopper films 13a and 13b are formed by the dry etching method to form the connection holes 17 penetrating the films. Then, a portion of the wiring film 14 is exposed to the outside to form a recess 20 formed by the connection holes (perforations) 17 and the wiring grooves 18. Further, as described above, in the process of forming the concave portion 20, since the organic-based photoresist is used, the residue foreign matter of such a photoresist is easily adhered to the inside of the concave portion 20 or the etching stopper film 13c. Further, even when the etching stopper films 13a, 13b, and 13c are formed of a carbon-containing constituent material, such carbon-containing foreign matter easily adheres to the inside of the concave portion 20. In the process of applying the pretreatment to the concave portion 20 (step S2), the entire surface of the substrate including the concave portion 20 is irradiated with a hydrogen radical. When the hydrogen radical is irradiated on the entire surface of the substrate in this manner, the reduction treatment of carbon by the hydrogen radical is performed on the entire surface of the substrate including the concave portion 20. As a result, a portion of the wiring film 14 constituting the bottom surface of the concave portion 20, a portion of the second interlayer insulating film 15 or the third interlayer insulating film 16 constituting the side surface of the concave portion 20, and further etching barrier films 13b, 13c and the like are attached thereto. The organic foreign matter on the surface can be removed from the surface. An example of such a pretreatment aspect is, for example, a hydrogen gas which receives microwaves to generate a hydrogen group, and supplies the hydrogen group in a vacuum chamber in which a substrate is accommodated. An example of the processing conditions in the previous treatment using microwaves and hydrogen in this manner is shown below. • Substrate temperature: l〇〇°C to 250°c • Hydrogen flow rate: 200sccm • Argon flow rate: 30sccm • Processing pressure: 50Pa to 500Pa 11 201125074

•微波輸出：l〇〇W 在以ZrBN膜被覆上述凹部20的製程（步驟S3)中，藉 由CVD法或PVD法等之成膜方法，在包含凹部2〇的基^ 表面之全體形成有ZrBN膜21。當形成有此種ZrBN膜21 時’若ZrBN膜21之基底為導電體則該ZrBN膜21會具有 導電性，而若ZrBN膜21之基底為絕緣體則該2出1^膜21 會具有絕緣性。例如與構成凹部2〇之底面的配線膜14相 接的ZrBN膜21之部分係成為具有5至8以Ω · cm之比電 阻值的導電體，而與構成凹部2〇之内侧面的第二層間絕緣 膜15或第二層間絕緣膜16相接的ZrBN膜21之部分係成 為具有102Ω · cm以上之比電阻值的絕緣體。 作為此種ZrBN膜21之成膜態樣的一例，例如可列舉 如下態樣：即接收微波之氮氣生成氮基，並在容納有基板 的真空室内供給該氮基與4-硼氫化锆（Zr(BH4) 4)。將如 此使用氮基與4-硼氩化鍅之處理條件的一例顯示如下。 •基板溫度：220°C • Zr ( BH4) 4 : 55sccm •氮氣流量(MFC2) : 50sccm •微波輸出：100W •處理壓力：400Pa 另外，在ZrBN膜21之成膜態樣的一例中，例如可列 舉如下態樣：即以錯(Zr)為主成分的靶材、與以氮化硼(BN) 為主成分的靶材’同時在基板上濺鍍。 當如此地形成ZrBN膜時，ZrBN膜的基底之層間絕 緣膜及配線膜14之表面，藉由先進行的前處理去除掉有機 系的異物。故而，與此種異物存在於基底的情況相較，可 12 201125074 提高ZrBN膜21與各層間絕緣膜之間的密接性，以及ZrBN 膜21與蝕刻阻擋膜之間的密接性。 在上述ZrBN膜21施予後處理的製程中，係在包含該 ZrBN膜21的基板表面之全體照射氫基。圖3(a)係顯示該 後處理後的ZrBN膜之剖面結構。如圖3(a)所示，當在ZrBN 膜之表面全體照射氫基時，依氫基所進行的氮之還原處理 會在ZrBN膜21之表面21a全體進行。然後，可從ZrBN 膜21之表面21a至少將成為氨等之揮發性氣體之氮去除 掉，使該表面21a成為金屬Zr或是導電性之硼化鍅(ZrB)。 其結果，與構成凹部20之底面的配線膜14相接的ZrBN 膜21之部分，會維持其導電性，而與構成凹部2〇之内側 面的第二層間絕緣膜15或第三層間絕緣膜16的ZrBN膜 21之部分，會將其表面21a(圖3(a)中附有點的區域)從絕緣 性改質成導電性。 另外’此種後處理的處理時間，如上所述，事先取得 被導體化的厚度到達成為目標之厚度（目標厚度T1)為止的 目標處理時間，僅以該目標處理時間執行的構成為佳。去 除掉氮的處理若過度地進行，則ZrBN膜21本來所具有的 導電率之選擇性也會消失。反之，去除掉氮的處理若不足， 則會因ZrBlS[膜21之表面21a的導體化不足而難以獲得所 期望的鍍鋼膜之埋設性。此點，若為僅以目標處理時間實 施後處理的構成，則可依設為目標的厚度來實現被導體化 ZrBN膜之厚度，且可抑制如上述的導體化之過度或不足。 又為使ZrBN膜21之表面2la具有導電性，最低一 原子層之ZrBN膜21必須改質成☆或是具導電’性之ZrB。 如此，被導體化的ZrBN膜21之厚度，有時會依凹部2〇 13 201125074 之結構或上述後處理之條件而有所不同。依此，上述的目、 標處理時間，有時也會因在凹部20中之何部分實現目標厚 度T1而有所不同。在此種情況下，以將上述目標處理時間 設定為於凹部20之底面周邊的部位實現目標厚度T1的構 成為佳。若為此種構成，則至少在凹部20之底面周邊可擔 保ZrBN膜21之導體化。 此種後處理的態樣之一例係與上述的前處理之態樣 相同地，例如有以下態樣：即接受微波之氫氣生成氫基， 並在容納有基板的真空室内供給該氫基。將如此使用微波 與氫氣之前處理中的處理條件之一例顯示如下。• Microwave output: l〇〇W In the process of coating the concave portion 20 with a ZrBN film (step S3), a film formation method such as a CVD method or a PVD method is used to form the entire surface of the substrate including the concave portion 2〇. ZrBN film 21. When such a ZrBN film 21 is formed, the ZrBN film 21 may have conductivity if the base of the ZrBN film 21 is a conductor, and the insulation of the ZrBN film 21 if the base of the ZrBN film 21 is an insulator. . For example, a portion of the ZrBN film 21 that is in contact with the wiring film 14 constituting the bottom surface of the concave portion 2 is a conductor having a specific resistance value of 5 to 8 in an Ω·cm ratio, and a second body constituting the inner side surface of the concave portion 2〇. The portion of the ZrBN film 21 where the interlayer insulating film 15 or the second interlayer insulating film 16 is in contact with each other is an insulator having a specific resistance value of 102 Ω·cm or more. As an example of the film formation of the ZrBN film 21, for example, nitrogen gas which receives microwaves generates a nitrogen group, and the nitrogen group and the zirconium borohydride (Zr) are supplied in a vacuum chamber in which the substrate is housed. (BH4) 4). An example of the treatment conditions using a nitrogen group and a 4-boron argon hydride as described below is shown below. • Substrate temperature: 220 ° C • Zr ( BH4) 4 : 55 sccm • Nitrogen flow rate (MFC2): 50 sccm • Microwave output: 100 W • Processing pressure: 400 Pa Further, in an example of the film formation of the ZrBN film 21, for example, The following is a case where a target having a wrong (Zr) as a main component and a target having a boron nitride (BN) as a main component are simultaneously sputtered on a substrate. When the ZrBN film is formed in this manner, the surface of the interlayer insulating film of the ZrBN film and the surface of the wiring film 14 are removed by the pretreatment which is performed first. Therefore, compared with the case where such foreign matter is present on the substrate, the adhesion between the ZrBN film 21 and the interlayer insulating film and the adhesion between the ZrBN film 21 and the etching stopper film can be improved by 12 201125074. In the process of applying the post-treatment of the ZrBN film 21, the entire surface of the substrate including the ZrBN film 21 is irradiated with a hydrogen group. Fig. 3(a) shows the cross-sectional structure of the post-treated ZrBN film. As shown in Fig. 3 (a), when the entire surface of the ZrBN film is irradiated with a hydrogen group, the reduction treatment of nitrogen by the hydrogen group is performed on the entire surface 21a of the ZrBN film 21. Then, at least the nitrogen which is a volatile gas such as ammonia can be removed from the surface 21a of the ZrBN film 21, and the surface 21a can be made of a metal Zr or a conductive lanthanum boride (ZrB). As a result, the portion of the ZrBN film 21 that is in contact with the wiring film 14 constituting the bottom surface of the concave portion 20 maintains its conductivity, and the second interlayer insulating film 15 or the third interlayer insulating film that constitutes the inner side surface of the concave portion 2〇. The portion of the ZrBN film 21 of 16 is modified from the insulating property to the electrical conductivity of the surface 21a (the region slightly attached to Fig. 3(a)). In addition, as described above, the processing time of the post-processing is preferably such that the target processing time until the target thickness is reached (target thickness T1) is obtained in advance. If the treatment for removing nitrogen is excessively performed, the selectivity of the conductivity of the ZrBN film 21 is also lost. On the other hand, if the treatment for removing nitrogen is insufficient, it is difficult to obtain the desired embedding property of the steel-plated film due to insufficient ZrBlS [conductivity of the surface 21a of the film 21). In this regard, in the case where the post-processing is performed only for the target processing time, the thickness of the conductor-formed ZrBN film can be realized in accordance with the target thickness, and excessive or insufficient conductorization as described above can be suppressed. Further, in order to make the surface 2la of the ZrBN film 21 conductive, the ZrBN film 21 of the lowest atomic layer must be modified into ☆ or ZrB having conductivity. Thus, the thickness of the ZrBN film 21 to be conductorized may differ depending on the structure of the recess 2 〇 13 201125074 or the conditions of the post-treatment described above. Accordingly, the above-described target and standard processing time may be different depending on which part of the concave portion 20 is used to achieve the target thickness T1. In this case, it is preferable to set the target processing time to a position around the bottom surface of the concave portion 20 to achieve the target thickness T1. According to this configuration, the conductor of the ZrBN film 21 can be ensured at least around the bottom surface of the concave portion 20. An example of such a post-treatment aspect is the same as the above-described pretreatment, for example, a hydrogen gas is received from a microwave to generate a hydrogen group, and the hydrogen group is supplied in a vacuum chamber in which a substrate is housed. An example of the processing conditions in the previous treatment using microwaves and hydrogen in this manner is shown below.

•基板溫度：l〇〇°C至250°C •氫氣流量：200sccm •氬氣流量：30sccm •處理壓力：50Pa至500Pa •微波輸出：100W 在以銅晶種膜22被覆凹部20内侧的製程（步驟S5) 中，如圖3(b)所示，在上述ZrBN膜21之表面21a全體， 藉由使用銅靶材之PVD法，形成有具有發揮作為鍍銅膜 23之供電膜的功能、及提高ZrBN膜21與鍍銅膜23間之 密接性的功能之銅晶種18。導電體的銅晶種膜22之構成 材料及與此相異的絕緣體之間的密接性，與導電體彼此間 之密接性或絕緣體彼此間之密接性相較，一般係較低。因 此，若依據PVD法使銅晶種膜22形成於絕緣體上，則與 此種銅晶種膜22形成於導電體上的情況相較，銅晶種膜 22之構成刼料較易凝聚成粒狀。尤其是若在具有絕緣性的 凹部20之底面周邊，藉由PVD法被覆銅晶種膜22，則隨 14 201125074 著凹部20變深，銅晶種膜22之構成元素就難以到達凹部 20之底面’由於該處的銅晶種膜22之成長速度會變慢， 所以更容易發生如上述的凝聚現象。 另一方面’若為如上述的構成，則當形成銅晶種膜22 時，銅晶種膜22之基底的ZrBN膜21之表面21a、尤其是 凹部20之底面周邊，係依先前進行的上述後處理而賦予導 電性。故而’與在未施予上述後處理的ZrBN膜21上形成 銅晶種膜22的情況相較，亦即與在具有絕緣性的Ζγβν膜 21上形成銅晶種膜22的情況相較，可提高ZrBN膜21與 銅晶種膜22之間的密接性。因而，不論是凹部2〇之側壁， 或成膜速度變慢的凹部20之底面周邊，仍可抑制銅晶種膜 22中之凝聚現象。 如圖3(c)所示，在藉由鍍金屬法以鍍鋼臈23填充於凹部2〇 内側的製程(步驟S6)中，係在上述銅晶種膜22之表面全體，以埋 設於凹部2G内側之形式，藉由電解鍵金屬法形成有鑛銅膜23。 此時，若對於處於凝聚狀態的銅晶種膜22應用電解鍍金屬法，則 會在Cu粒子之間滲入酸性的鍍金屬的溶液，而使鍍金屬的溶液 之韻刻速度崎麵23之綠速度還大。其絲，贿金屬法= 得之鍍銅膜23反而很難成長。 X /汁 可提高錢 此點，在上述銅晶種膜22形成之後的錢金屬製程中， 由於銅晶種膜22中之粒狀體本身的成長會受到抑制，所以 鍍金屬的溶液不會滲入此種粒狀體之間。故而，铲金屬 溶液之姓刻速度比鍵銅膜之成長速度還大本身即^受到抑 制。因而’如圖3(c)所示，遍及凹部2〇之全體 銅膜23的埋設性。 在研削疊層於⑽13e上的錢之製程(化與 15 201125074 機械性拋光製程；Chemical Mechanical Polishing 製程；CMP， 製程(步驟S7))中’例如藉由使用以氧化銘為主要材料的研 磨漿（slurry)之CMP法，依序研削沉積於蝕刻阻擋膜13c 上之剩餘膜、即鍍銅膜23、銅晶種膜22、及ZrBN膜21。 此時’在第三層間絕緣膜16上形成有其他的配線構造的情 況時，為了確保層間的絕緣性，比須完全地去除沉積於第 三層間絕緣膜16上的導電體。 如上所述，右為僅ZrBN膜21之表面21a被導體化的 構成，與去除全部的2戍>|膜21之構成相較，也容易研磨 去除此種表面21a。因此，即使對於蝕刻阻擋膜13e上之 ZrBN獏21需要絕緣性的情況，ZrBN膜21之本來所具有 的導電率之選擇性也可容易在該2出]^膜21之下層部21b 引出故而，若被導體化的ZrBN膜21之厚度以目標厚度 T1規格化，則藉由CMP法研削的膜厚也可被規格化，成 為將累計鍍銅膜23之膜厚與銅晶種膜22之膜厚所得的膜 厚T2與目標厚度T1相加後的膜厚。 因此，由於可抑制藉由CMP法研削的膜厚之過度或 不足，所以可更破實地實現上述導電率之選擇性。 如以上說明，依據上述實施形態可獲得下列效果。 (1)由於在表面被導體化的ZrBN膜21上，形成有依 PVD去所得的銅晶種膜22 ’所以即使在凹部20之底面周 邊’ 膜21之表面也被導體化，並在如此被導體化的• Substrate temperature: l 〇〇 ° C to 250 ° C • Hydrogen flow rate: 200 sccm • Argon flow rate: 30 sccm • Processing pressure: 50 Pa to 500 Pa • Microwave output: 100 W In the process of coating the inside of the recess 20 with the copper seed film 22 ( In the step S5), as shown in FIG. 3(b), the entire surface 21a of the ZrBN film 21 is formed by a PVD method using a copper target, and has a function of providing a power supply film as the copper plating film 23, and A copper seed crystal 18 having a function of improving the adhesion between the ZrBN film 21 and the copper plating film 23. The adhesion between the constituent material of the copper seed film 22 of the conductor and the insulator different therefrom is generally lower than the adhesion between the conductors or the adhesion between the insulators. Therefore, when the copper seed film 22 is formed on the insulator according to the PVD method, the composition of the copper seed film 22 is more easily condensed into particles than when the copper seed film 22 is formed on the conductor. shape. In particular, when the copper seed crystal film 22 is coated by the PVD method around the bottom surface of the insulating recessed portion 20, the concave portion 20 becomes deeper as 14201125074, and the constituent elements of the copper seed crystal film 22 hardly reach the bottom surface of the concave portion 20. Since the growth rate of the copper seed film 22 at this place is slow, the aggregation phenomenon as described above is more likely to occur. On the other hand, in the case of the above-described configuration, when the copper seed film 22 is formed, the surface 21a of the ZrBN film 21 on the base of the copper seed film 22, particularly the periphery of the bottom surface of the concave portion 20, is the same as previously described. Post-treatment imparts conductivity. Therefore, compared with the case where the copper seed film 22 is formed on the ZrBN film 21 to which the post-treatment described above is not applied, that is, as compared with the case where the copper seed film 22 is formed on the insulating Ζγβν film 21, The adhesion between the ZrBN film 21 and the copper seed film 22 is improved. Therefore, the aggregation phenomenon in the copper seed film 22 can be suppressed regardless of the side wall of the concave portion 2 or the periphery of the bottom surface of the concave portion 20 where the film formation speed is slow. As shown in FIG. 3(c), in the process of filling the inside of the concave portion 2 by the plating of the steel plate 23 by the metal plating method (step S6), the entire surface of the copper seed film 22 is embedded in the concave portion. In the form of the inner side of 2G, a mineralized copper film 23 is formed by an electrolytic bond metal method. At this time, when the electrolytic metal plating method is applied to the copper seed crystal film 22 in a state of aggregation, an acidic metal plating solution is infiltrated between the Cu particles, and the rhythmic speed of the metal plating solution is 23 green. The speed is still big. Its silk, bribery metal method = the copper film 23 is difficult to grow. X / juice can increase the money. In the money metal process after the formation of the above-mentioned copper seed film 22, since the growth of the granular body itself in the copper seed film 22 is suppressed, the metal plating solution does not penetrate. Between such granules. Therefore, the speed at which the shovel metal solution is wound is greater than the growth rate of the bond copper film itself. Therefore, as shown in Fig. 3(c), the embedding property of the entire copper film 23 is spread over the concave portion 2A. In the process of grinding the money laminated on (10) 13e (Chemical and 15 201125074 mechanical polishing process; Chemical Mechanical Polishing process; CMP, process (step S7)), for example, by using a polishing slurry with oxidized crystal as the main material ( The CMP method of slurry) sequentially grinds the remaining films deposited on the etching stopper film 13c, that is, the copper plating film 23, the copper seed film 22, and the ZrBN film 21. At this time, when another wiring structure is formed on the third interlayer insulating film 16, in order to ensure insulation between the layers, it is necessary to completely remove the conductor deposited on the third interlayer insulating film 16. As described above, the right side is a structure in which only the surface 21a of the ZrBN film 21 is electrically formed, and it is easy to polish and remove such a surface 21a as compared with the configuration in which all of the 2戍>| films 21 are removed. Therefore, even if the insulating property of the ZrBN貘21 on the etching stopper film 13e is required, the selectivity of the conductivity of the ZrBN film 21 can be easily extracted from the lower layer portion 21b of the film 21, When the thickness of the conductive ZrBN film 21 is normalized to the target thickness T1, the film thickness which is ground by the CMP method can be normalized, and the film thickness of the copper plating film 23 and the film of the copper seed film 22 can be obtained. The thickness of the film thickness T2 obtained by the thickness is added to the target thickness T1. Therefore, since the excessive or insufficient film thickness which is ground by the CMP method can be suppressed, the selectivity of the above conductivity can be achieved more compactly. As described above, according to the above embodiment, the following effects can be obtained. (1) Since the copper seed film 22' obtained by PVD is formed on the ZrBN film 21 whose surface is formed, the surface of the film 21 is electrically conductive even at the periphery of the bottom surface of the concave portion 20, and is thus Conductorized

ZrBN犋21上形成有銅晶種膜22。故而，在凹部20之内 側全體，可提高ZrBN膜21與銅晶種臈22之密接性，且 可在四邹20之内侧全體抑制銅晶種膜22之凝聚現象。 其結果，在形成有銅晶種膜22之後的鍍金屬製程中， 16 201125074 由於銅晶種膜22中的粒狀體本身之成長成 金屬的溶液難以滲入此種粒狀體之間。=到抑制’所以鍍 液之蝕刻速度會比鍍銅膜23之成長逮度變食曰，鍍金屬的溶 可受到抑制。因而，可提高鍍軸23=’得還大’其本身 埋設性。 對凹部20之全體的 (2) 此外’銅晶種膜22與ZrBN膜 此等之全體而提高，因此，亦可抑制 <間的密接性因 溶液之渗人而不必要地增厚銅晶軸U了抑制了鐘金屬的 可減薄銅晶種膜22之膜厚本身。 之犋厚’甚至於也A copper seed film 22 is formed on the ZrBN犋21. Therefore, in the entire inner side of the concave portion 20, the adhesion between the ZrBN film 21 and the copper seed crystal 22 can be improved, and the aggregation phenomenon of the copper seed film 22 can be suppressed on the entire inner side of the four. As a result, in the metal plating process after the formation of the copper seed film 22, 16 201125074 is difficult to infiltrate between the granular bodies due to the growth of the granular body itself in the copper seed crystal film 22 into a metal. = to suppression 'The etching rate of the plating solution is changed to the growth rate of the copper plating film 23, and the dissolution of the metal plating can be suppressed. Therefore, it is possible to improve the burying property of the plating shaft 23 = 'too large'. (2) of the whole of the concave portion 20 is improved by the whole of the 'copper seed crystal film 22 and the ZrBN film. Therefore, it is also possible to suppress the adhesion between the <unequal thickening of the copper crystal due to the infiltration of the solution. The axis U suppresses the film thickness itself of the thin metal film 22 of the bell metal. Thickness, even

(3) 由於藉由氫基之照射使ZrBN 化，所以即使在可實現此種導體化的、21之表面導體 的表面處理之中，也可減輕對ΖγΒν種物理性或化學性 傷。 、21之電氣及熱的損 (4) 正因為可僅以目標處理時間 _ 之表面去除掉氮的處理，所以可以目：從ZrBN、膜21 化的厚度，且可抑制Z腿膜21中之導二T1實現被導體 L 丁^導體化的過度或不足。 (5) 從形成於蝕刻阻擋膜13c上的剩餘 皮導體化的部分。因此，即使在被平坦丄板 上殘留有2簡膜21’由於此種的ZrB㈣21具有絕緣性， =以可更確實地實現2趣膜21本來所具有的導電率之選 擇性。 ⑹由於在2测膜2R基底的表面施予氫基的還原 所以即使在該基底之表面存在有機物等之絕緣性的 、 也可去除掉此等的異物。其結果，可提高ZrBN膜 21與這些基底間的密接性。 (7)由於ZrBN膜21之前處理與ΖγΒν.21之後處理， 201125074 為共通的氫基之照射處理，所以在實施此等前處理及後處、 理之方面，可使用共通的氫基照射機構。因此，從半導體 裝置之製造系統的觀點來看，可就實施上述之前處理與後 處理用的裝置謀求共通化，且在製造此種半導體裝置方 面’也可抑制裝置佔有面積之擴大。 另外’上述實施形態亦可變更如下來實施。 •若為於形成ZrBN膜21之前去除掉附著於凹部20 内侧的殘渣的處理，則亦可以在還原性之環境下對基板進 行熱處理的構成，取代如上述的氫基之照射處理。即使是 此種構成’也可提高ZrBN獏21與ZrBN膜21之基底的密 接性。 •去除疊層於蝕刻阻擋膜13c上的各膜之方法，除了 上述的OMP法以外，還可應用物理性的蝕刻法。若為此種 構成，則可去除疊層於蝕刻阻擋膜13c上的各膜之一部分。 •若為未在凹部20内侧附著有殘渣的構成，或是即 使有此種殘渣，仍可在ZrBN膜21與ZrBN膜21之基底之 間確保充分密接性的構成，則亦玎為省略如上述的前處理 之構成。若為此種構成，則由於不需要對ZrBN膜21之前 處理’所以可減低半導體裝置之製程的製程數，甚至可提 高半導體裴置之生產性。 •針對與ZrBN膜21相關之前處理、ZrBN膜21之成 膜處理、與ZrBN膜21相關之後處理、及銅晶種膜22之 成膜處理，以在共通的真空系統中連續執行的構成為佳。 若為此種構成，則凹部2〇之内璧與ZrBN膜21之界面、 及ZrBN膜21與銅晶種膜22之界面的各界面，不用暴露 於大氣中就可形成。故而，在四部20之内壁與ZrBN膜21 201125074 之界面、及ZrBN膜21與銅晶種膜22之界面的各界面中， 可提高密接性。 •從ZrBN膜21之表面去除掉氮的處理，除了在該表 面照射氫基的處理以外’例如也可應用從ZrBN膜21只機 鍍輕元素之氮的物理性之表面處理、或以熱反應只還原 ZrBN膜21之表面的氮，並使之氣化作為反應生成物的化 學性之表面處理等。 •凹部20並未被限定於由連接孔17及配線槽18所 構成的雙重鑲嵌圖案。凹部20亦可例如由連接孔17及配 線槽18之一方所構成。 【圖式簡單說明】 圖1係顯示構成本實施形態之半導體裝置之製造方法的Cu 配線之形成方法的流程圖。 圖2(a)係形成於絕緣膜的雙重鑲嵌圖案之俯視圖； 圖2⑷之A-A線剖視圖。 為 之製程圖。 圖3⑷至(c)係顯示 圖4⑻、㈨係顯示 泰Cu配線之形成方法中的各製程之製程圖。 示習知例的Cu配線之形成方法中的各製程 【主4元件符號說明 11、D1 笛 12障壁骐 層間絕緣膜(3) Since ZrBN is formed by irradiation of a hydrogen group, physical or chemical damage to ΖγΒν can be alleviated even in the surface treatment of the surface conductor of 21 which can realize such conductorization. , electric and thermal damage of (21) Because the treatment of removing the nitrogen only on the surface of the target treatment time _, it is possible to reduce the thickness from the ZrBN, the film 21, and suppress the Z leg film 21. The second T1 realizes the excessive or insufficient conductorization of the conductor L. (5) A portion from the remaining skin conductor formed on the etching stopper film 13c. Therefore, even if the two thin films 21' remain on the flat ruthenium plate, since such ZrB (four) 21 has insulation properties, the selectivity of the conductivity of the film 21 can be more reliably achieved. (6) Since the reduction of the hydrogen group is carried out on the surface of the 2R film 2R substrate, even if there is insulation of an organic substance or the like on the surface of the substrate, such foreign matter can be removed. As a result, the adhesion between the ZrBN film 21 and these substrates can be improved. (7) Since the ZrBN film 21 is treated before and after the ΖγΒν.21, 201125074 is a common hydrogen-based irradiation treatment, a common hydrogen-based irradiation mechanism can be used for performing such pre-treatment and post-treatment. Therefore, from the viewpoint of the manufacturing system of the semiconductor device, it is possible to achieve commonality between the devices for performing the above-described pre-processing and post-processing, and to prevent the enlargement of the device occupying area in the manufacture of such a semiconductor device. Further, the above embodiment may be modified as follows. In the case where the residue adhering to the inside of the concave portion 20 is removed before the formation of the ZrBN film 21, the substrate may be heat-treated in a reducing environment instead of the above-described hydrogen-based irradiation treatment. Even in such a configuration, the adhesion between the ZrBN貘21 and the base of the ZrBN film 21 can be improved. • A method of removing each film laminated on the etching stopper film 13c, in addition to the above-described OMP method, a physical etching method can be applied. With such a configuration, one portion of each of the films laminated on the etching stopper film 13c can be removed. In the case where the residue is not adhered to the inside of the concave portion 20, or a structure in which sufficient adhesion can be ensured between the ZrBN film 21 and the base of the ZrBN film 21 even if such a residue is present, the above-described configuration is omitted. The composition of the pre-processing. According to this configuration, since the ZrBN film 21 is not processed beforehand, the number of processes of the semiconductor device can be reduced, and the productivity of the semiconductor device can be improved. • The pre-treatment associated with the ZrBN film 21, the film formation process of the ZrBN film 21, the post-treatment with the ZrBN film 21, and the film formation process of the copper seed film 22 are preferably performed continuously in a common vacuum system. . With such a configuration, the interface between the inner crucible of the concave portion 2 and the ZrBN film 21 and the interface between the ZrBN film 21 and the copper seed film 22 can be formed without being exposed to the atmosphere. Therefore, in the interface between the inner wall of the four portions 20 and the ZrBN film 21 201125074 and the interface between the ZrBN film 21 and the copper seed film 22, the adhesion can be improved. • The treatment for removing nitrogen from the surface of the ZrBN film 21, except for the treatment of irradiating the surface with a hydrogen group, for example, a physical surface treatment of a nitrogen element of a light element from the ZrBN film 21 or a thermal reaction may be applied. Only the nitrogen on the surface of the ZrBN film 21 is reduced and vaporized to form a chemical surface treatment or the like as a reaction product. The recess 20 is not limited to the double damascene pattern formed by the connection hole 17 and the wiring groove 18. The recess 20 can also be formed, for example, by one of the connection hole 17 and the wiring groove 18. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing a method of forming a Cu wiring constituting a method of manufacturing a semiconductor device of the present embodiment. Fig. 2(a) is a plan view showing a double damascene pattern formed on an insulating film; and Fig. 2(4) is a cross-sectional view taken along line A-A. For the process map. Fig. 3 (4) to (c) show Fig. 4 (8) and (9) show process diagrams of the respective processes in the method of forming the Thai Cu wiring. Each process in the method of forming the Cu wiring of the prior art is shown. [Main 4 component symbol description 11. D1 flute 12 barrier 骐 interlayer insulating film

Ha，、％ 14配綠祺 ESa、ESb、ESC 钱刻阻擒膜 19 201125074 15 > D2 第二層間絕緣膜 16、 D3 第三層間絕緣膜 17、 CH 連接孔（穿孔） 18、 LG 配線槽 20 凹部 21 ' 51 ZrBN 膜 21a 表面 21b 下層部 22 銅晶種膜 23 鍍銅膜 53 Cu 膜Ha,,%14 with green 祺ESa, ESb, ESC etched film 19 201125074 15 > D2 second interlayer insulating film 16, D3 third interlayer insulating film 17, CH connecting hole (perforation) 18, LG wiring groove 20 recess 21 ' 51 ZrBN film 21a surface 21b lower layer 22 copper seed film 23 copper plating film 53 Cu film

Ml 第一配線膜 T1目標厚度 T2 膜厚 20Ml first wiring film T1 target thickness T2 film thickness 20

Claims (1)

201125074 七、申請專利範園： 1.一種半導體裝置之製造方法，係具備. 以魏化錯膜被覆基板上之具有絕緣膜之凹部内側的 製程； 藉由PVD法，以銅晶種膜被覆前述魏化錯膜之表面 的製程； 乂藉由鑛金屬法’以鍍峨填充於前述銅晶種膜所被覆 之前述凹部内侧的製程；以及 在以前述銅晶種膜被覆前述蝴氮化錐膜之表面之前， 魏化錯膜之表面至少去除掉氮，使該表面導體化 去專利範圍帛1項所述之半導體裝置之製造方 在祕錢化賴之表面闕氫基，使該表面 法，3二申項所述之半 Ϊ時間’僅⑽目標處理時間執行前述去除掉氮的處 4·如申請專利範圍第3項所述之半導體 法，其中’更具備:藉由CMp法研削已形』，方 上的鍍銅膜、銅晶種膜 、J迷絕緣膜 平坦化的製程，膜及_硼氮化㈣，將前述基板上 在月J述研削之製程中，將前述哪氮化錯膜研削成為前 201125074 述目標的厚度。 5. 如申請專利範圍第1至4項中任一項所述之半導體 裝置之製造方法，其中，前述具有絕緣膜的凹部係被連接 於前述絕緣膜之基底的導電膜之連接孔， 在以前述硼氮化锆膜被覆前述具有絕緣膜的連接孔之 内側之前，在前述絕緣膜及前述導電膜之表面照射氫基。 6. 如申請專利範圍第1至4項中任一項所述之半導體 裝置之製造方法，其中，前述凹部係包含配線槽與連接孔 的雙重鑲嵌圖案， 以前述硼氮化鍅膜被覆前述配線溝與連接孔， 藉由氫基之照射，從被覆前述配線槽與連接孔的前述 硼氮化鍅膜之表面至少去除掉氮，使該表面導體化， 之後，以前述銅晶種膜被覆用以被覆前述配線槽與連 接孔的前述硼氮化锆膜。 22201125074 VII. Application for a patent garden: 1. A method for manufacturing a semiconductor device, comprising: a process of coating a inside of a concave portion having an insulating film on a substrate with a Weihua fault film; and coating the copper seed film by a PVD method a process for preparing a surface of a smear film; a process of filling the inside of the concave portion covered by the copper seed film by ruthenium plating by a mineral metal method; and coating the ruthenium nitride film with the copper seed film Before the surface, the surface of the Weihua wrong film is at least removed from the surface of the surface of the film, and the surface of the semiconductor device is manufactured by the manufacturer of the semiconductor device described in the above paragraph. The semi-defective time described in the 3nd application refers to only the (10) target processing time to perform the aforementioned removal of nitrogen. 4. The semiconductor method as described in claim 3, wherein 'more possessed: by CMp method The process of flattening the copper plating film, the copper seed film, and the J insulating film on the square, the film and the borax nitride (4), and the above-mentioned substrate is subjected to the process of grinding in the above-mentioned substrate, Membrane grinding becomes the first 2011250 74 The thickness of the target. 5. The method of manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the recess having the insulating film is connected to a connection hole of the conductive film on the base of the insulating film, Before the zirconium oxynitride film is coated on the inner side of the connection hole having the insulating film, a hydrogen group is applied to the surfaces of the insulating film and the conductive film. 6. The method of manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the recessed portion includes a double damascene pattern of a wiring trench and a connection hole, and the wiring is covered with the borofluoride film. In the groove and the connection hole, at least the nitrogen is removed from the surface of the borofluoride film covering the wiring groove and the connection hole by the irradiation of the hydrogen group, and the surface is made conductive, and then the copper seed film is coated. The borozide film of boron nitride is coated on the wiring trench and the connection hole. twenty two
TW099139087A 2009-11-12 2010-11-12 Method for manufacturing semiconductor device TW201125074A (en)

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JP2002146535A (en) * 2000-11-02 2002-05-22 Anelva Corp Zirconium nitride thin film, method and apparatus for producing the thin film, and method and apparatus for forming copper wiring
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